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5c9efb36 | 1 | /* |
1b77ca8a | 2 | * Copyright 2006, 2010-2011 Freescale Semiconductor. |
5c9efb36 | 3 | * |
debb7354 JL |
4 | * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) |
5 | * | |
3765b3e7 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
debb7354 JL |
7 | */ |
8 | ||
9 | /* | |
5c9efb36 | 10 | * MPC8641HPCN board configuration file |
debb7354 JL |
11 | * |
12 | * Make sure you change the MAC address and other network params first, | |
92ac5208 | 13 | * search for CONFIG_SERVERIP, etc. in this file. |
debb7354 JL |
14 | */ |
15 | ||
16 | #ifndef __CONFIG_H | |
17 | #define __CONFIG_H | |
18 | ||
19 | /* High Level Configuration Options */ | |
7649a590 | 20 | #define CONFIG_MP 1 /* support multiple processors */ |
53677ef1 | 21 | #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ |
d591a80e | 22 | #define CONFIG_ADDR_MAP 1 /* Use addr map */ |
debb7354 | 23 | |
2ae18241 WD |
24 | /* |
25 | * default CCSRBAR is at 0xff700000 | |
26 | * assume U-Boot is less than 0.5MB | |
27 | */ | |
28 | #define CONFIG_SYS_TEXT_BASE 0xeff00000 | |
29 | ||
debb7354 | 30 | #ifdef RUN_DIAG |
6bf98b13 | 31 | #define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE |
debb7354 | 32 | #endif |
5c9efb36 | 33 | |
1266df88 BB |
34 | /* |
35 | * virtual address to be used for temporary mappings. There | |
36 | * should be 128k free at this VA. | |
37 | */ | |
38 | #define CONFIG_SYS_SCRATCH_VA 0xe0000000 | |
39 | ||
1b77ca8a KG |
40 | #define CONFIG_SYS_SRIO |
41 | #define CONFIG_SRIO1 /* SRIO port 1 */ | |
af5d100e | 42 | |
b38eaec5 RD |
43 | #define CONFIG_PCIE1 1 /* PCIE controller 1 (ULI bridge) */ |
44 | #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot) */ | |
63cec581 | 45 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ |
8ba93f68 | 46 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
5c9efb36 | 47 | |
53677ef1 | 48 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
debb7354 | 49 | #define CONFIG_ENV_OVERWRITE |
debb7354 | 50 | |
4bbfd3e2 | 51 | #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ |
31d82672 | 52 | #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ |
d591a80e | 53 | #define CONFIG_SYS_NUM_ADDR_MAP 8 /* Number of addr map slots = 8 dbats */ |
debb7354 | 54 | |
53677ef1 | 55 | #define CONFIG_ALTIVEC 1 |
debb7354 | 56 | |
5c9efb36 | 57 | /* |
debb7354 JL |
58 | * L2CR setup -- make sure this is right for your board! |
59 | */ | |
6d0f6bcf | 60 | #define CONFIG_SYS_L2 |
debb7354 JL |
61 | #define L2_INIT 0 |
62 | #define L2_ENABLE (L2CR_L2E) | |
63 | ||
64 | #ifndef CONFIG_SYS_CLK_FREQ | |
63cec581 ES |
65 | #ifndef __ASSEMBLY__ |
66 | extern unsigned long get_board_sys_clk(unsigned long dummy); | |
67 | #endif | |
53677ef1 | 68 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) |
debb7354 JL |
69 | #endif |
70 | ||
6d0f6bcf JCPV |
71 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ |
72 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
debb7354 | 73 | |
3111d32c BB |
74 | /* |
75 | * With the exception of PCI Memory and Rapid IO, most devices will simply | |
76 | * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA | |
77 | * when 36-bit is enabled. When 36-bit is not enabled, these bits are 0. | |
78 | */ | |
79 | #ifdef CONFIG_PHYS_64BIT | |
1605cc9e | 80 | #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f |
3111d32c | 81 | #else |
1605cc9e | 82 | #define CONFIG_SYS_PHYS_ADDR_HIGH 0x00000000 |
3111d32c BB |
83 | #endif |
84 | ||
debb7354 JL |
85 | /* |
86 | * Base addresses -- Note these are effective addresses where the | |
87 | * actual resources get mapped (not physical addresses) | |
88 | */ | |
c759a01a | 89 | #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ |
6d0f6bcf | 90 | #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ |
debb7354 | 91 | |
3111d32c BB |
92 | /* Physical addresses */ |
93 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
1605cc9e BB |
94 | #define CONFIG_SYS_CCSRBAR_PHYS_HIGH CONFIG_SYS_PHYS_ADDR_HIGH |
95 | #define CONFIG_SYS_CCSRBAR_PHYS \ | |
96 | PAIRED_PHYS_TO_PHYS(CONFIG_SYS_CCSRBAR_PHYS_LOW, \ | |
97 | CONFIG_SYS_CCSRBAR_PHYS_HIGH) | |
3111d32c | 98 | |
076bff8f YS |
99 | #define CONFIG_HWCONFIG /* use hwconfig to control memory interleaving */ |
100 | ||
debb7354 JL |
101 | /* |
102 | * DDR Setup | |
103 | */ | |
e02eae6f | 104 | #define CONFIG_FSL_DDR_INTERACTIVE |
6a8e5692 KG |
105 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ |
106 | #define CONFIG_DDR_SPD | |
107 | ||
108 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ | |
109 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
110 | ||
6d0f6bcf JCPV |
111 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ |
112 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
1266df88 | 113 | #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ |
fcb28e76 | 114 | #define CONFIG_VERY_BIG_RAM |
debb7354 | 115 | |
6a8e5692 KG |
116 | #define CONFIG_DIMM_SLOTS_PER_CTLR 2 |
117 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
118 | ||
119 | /* | |
120 | * I2C addresses of SPD EEPROMs | |
121 | */ | |
122 | #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ | |
123 | #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 0 DIMM 1 */ | |
124 | #define SPD_EEPROM_ADDRESS3 0x53 /* CTLR 1 DIMM 0 */ | |
125 | #define SPD_EEPROM_ADDRESS4 0x54 /* CTLR 1 DIMM 1 */ | |
126 | ||
6a8e5692 KG |
127 | /* |
128 | * These are used when DDR doesn't use SPD. | |
129 | */ | |
6d0f6bcf JCPV |
130 | #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ |
131 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F | |
132 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ | |
133 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 | |
134 | #define CONFIG_SYS_DDR_TIMING_0 0x00260802 | |
135 | #define CONFIG_SYS_DDR_TIMING_1 0x39357322 | |
136 | #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 | |
137 | #define CONFIG_SYS_DDR_MODE_1 0x00480432 | |
138 | #define CONFIG_SYS_DDR_MODE_2 0x00000000 | |
139 | #define CONFIG_SYS_DDR_INTERVAL 0x06090100 | |
140 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef | |
141 | #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 | |
142 | #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 | |
143 | #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 | |
144 | #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ | |
145 | #define CONFIG_SYS_DDR_CONTROL2 0x04400000 | |
6a8e5692 | 146 | |
ad8f8687 | 147 | #define CONFIG_ID_EEPROM |
6d0f6bcf | 148 | #define CONFIG_SYS_I2C_EEPROM_NXID |
32628c50 | 149 | #define CONFIG_ID_EEPROM |
6d0f6bcf JCPV |
150 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
151 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
debb7354 | 152 | |
c759a01a | 153 | #define CONFIG_SYS_FLASH_BASE 0xef800000 /* start of FLASH 8M */ |
1605cc9e BB |
154 | #define CONFIG_SYS_FLASH_BASE_PHYS_LOW CONFIG_SYS_FLASH_BASE |
155 | #define CONFIG_SYS_FLASH_BASE_PHYS \ | |
156 | PAIRED_PHYS_TO_PHYS(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \ | |
157 | CONFIG_SYS_PHYS_ADDR_HIGH) | |
3111d32c | 158 | |
b81b773e | 159 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} |
debb7354 | 160 | |
3111d32c BB |
161 | #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ |
162 | | 0x00001001) /* port size 16bit */ | |
163 | #define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/ | |
debb7354 | 164 | |
3111d32c BB |
165 | #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE_PHYS) \ |
166 | | 0x00001001) /* port size 16bit */ | |
167 | #define CONFIG_SYS_OR2_PRELIM 0xffffeff7 /* 32k Compact Flash */ | |
debb7354 | 168 | |
3111d32c BB |
169 | #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) \ |
170 | | 0x00000801) /* port size 8bit */ | |
171 | #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32k PIXIS area*/ | |
debb7354 | 172 | |
c759a01a BB |
173 | /* |
174 | * The LBC_BASE is the base of the region that contains the PIXIS and the CF. | |
175 | * The PIXIS and CF by themselves aren't large enough to take up the 128k | |
176 | * required for the smallest BAT mapping, so there's a 64k hole. | |
177 | */ | |
178 | #define CONFIG_SYS_LBC_BASE 0xffde0000 | |
1605cc9e | 179 | #define CONFIG_SYS_LBC_BASE_PHYS_LOW CONFIG_SYS_LBC_BASE |
debb7354 | 180 | |
7608d75f | 181 | #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ |
c759a01a | 182 | #define PIXIS_BASE (CONFIG_SYS_LBC_BASE + 0x00010000) |
1605cc9e BB |
183 | #define PIXIS_BASE_PHYS_LOW (CONFIG_SYS_LBC_BASE_PHYS_LOW + 0x00010000) |
184 | #define PIXIS_BASE_PHYS PAIRED_PHYS_TO_PHYS(PIXIS_BASE_PHYS_LOW, \ | |
185 | CONFIG_SYS_PHYS_ADDR_HIGH) | |
c759a01a | 186 | #define PIXIS_SIZE 0x00008000 /* 32k */ |
5c9efb36 JL |
187 | #define PIXIS_ID 0x0 /* Board ID at offset 0 */ |
188 | #define PIXIS_VER 0x1 /* Board version at offset 1 */ | |
189 | #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ | |
190 | #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ | |
191 | #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */ | |
192 | #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ | |
193 | #define PIXIS_VCTL 0x10 /* VELA Control Register */ | |
194 | #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ | |
195 | #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ | |
196 | #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ | |
9af9c6bd KG |
197 | #define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */ |
198 | #define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */ | |
5c9efb36 JL |
199 | #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ |
200 | #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ | |
201 | #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ | |
202 | #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ | |
6d0f6bcf | 203 | #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ |
debb7354 | 204 | |
b5431560 | 205 | /* Compact flash shares a BAT with PIXIS; make sure they're contiguous */ |
c759a01a | 206 | #define CF_BASE (PIXIS_BASE + PIXIS_SIZE) |
3111d32c | 207 | #define CF_BASE_PHYS (PIXIS_BASE_PHYS + PIXIS_SIZE) |
b5431560 | 208 | |
170deacb | 209 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
6d0f6bcf | 210 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ |
debb7354 | 211 | |
6d0f6bcf JCPV |
212 | #undef CONFIG_SYS_FLASH_CHECKSUM |
213 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
214 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
14d0a02a | 215 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
bf9a8c34 | 216 | #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ |
debb7354 | 217 | |
00b1883a | 218 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
219 | #define CONFIG_SYS_FLASH_CFI |
220 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
debb7354 | 221 | |
6d0f6bcf JCPV |
222 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
223 | #define CONFIG_SYS_RAMBOOT | |
debb7354 | 224 | #else |
6d0f6bcf | 225 | #undef CONFIG_SYS_RAMBOOT |
debb7354 JL |
226 | #endif |
227 | ||
6d0f6bcf | 228 | #if defined(CONFIG_SYS_RAMBOOT) |
fa7db9c3 | 229 | #undef CONFIG_SPD_EEPROM |
6d0f6bcf | 230 | #define CONFIG_SYS_SDRAM_SIZE 256 |
debb7354 JL |
231 | #endif |
232 | ||
233 | #undef CONFIG_CLOCKS_IN_MHZ | |
234 | ||
6d0f6bcf JCPV |
235 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
236 | #ifndef CONFIG_SYS_INIT_RAM_LOCK | |
237 | #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ | |
debb7354 | 238 | #else |
6d0f6bcf | 239 | #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ |
debb7354 | 240 | #endif |
553f0982 | 241 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ |
debb7354 | 242 | |
25ddd1fb | 243 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 244 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
debb7354 | 245 | |
221fbd22 | 246 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ |
6d0f6bcf | 247 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ |
debb7354 JL |
248 | |
249 | /* Serial Port */ | |
250 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
251 | #define CONFIG_SYS_NS16550_SERIAL |
252 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
253 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
debb7354 | 254 | |
6d0f6bcf | 255 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
debb7354 JL |
256 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
257 | ||
6d0f6bcf JCPV |
258 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
259 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
debb7354 | 260 | |
586d1d5a JL |
261 | /* |
262 | * I2C | |
263 | */ | |
00f792e0 HS |
264 | #define CONFIG_SYS_I2C |
265 | #define CONFIG_SYS_I2C_FSL | |
266 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
267 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
268 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 | |
269 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
debb7354 | 270 | |
586d1d5a JL |
271 | /* |
272 | * RapidIO MMU | |
273 | */ | |
1b77ca8a | 274 | #define CONFIG_SYS_SRIO1_MEM_BASE 0x80000000 /* base address */ |
3111d32c | 275 | #ifdef CONFIG_PHYS_64BIT |
1605cc9e BB |
276 | #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW 0x00000000 |
277 | #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x0000000c | |
3111d32c | 278 | #else |
1605cc9e BB |
279 | #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW CONFIG_SYS_SRIO1_MEM_BASE |
280 | #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x00000000 | |
3111d32c | 281 | #endif |
1605cc9e BB |
282 | #define CONFIG_SYS_SRIO1_MEM_PHYS \ |
283 | PAIRED_PHYS_TO_PHYS(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \ | |
284 | CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) | |
1b77ca8a | 285 | #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */ |
debb7354 JL |
286 | |
287 | /* | |
288 | * General PCI | |
289 | * Addresses are mapped 1-1. | |
290 | */ | |
49f46f3b | 291 | |
64e55d5e | 292 | #define CONFIG_SYS_PCIE1_NAME "ULI" |
46f3e385 | 293 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 |
3111d32c | 294 | #ifdef CONFIG_PHYS_64BIT |
46f3e385 | 295 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 |
1605cc9e BB |
296 | #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW 0x00000000 |
297 | #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x0000000c | |
3111d32c | 298 | #else |
46f3e385 | 299 | #define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT |
1605cc9e BB |
300 | #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW CONFIG_SYS_PCIE1_MEM_VIRT |
301 | #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x00000000 | |
3111d32c | 302 | #endif |
1605cc9e BB |
303 | #define CONFIG_SYS_PCIE1_MEM_PHYS \ |
304 | PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \ | |
305 | CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) | |
46f3e385 KG |
306 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
307 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
308 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 | |
1605cc9e BB |
309 | #define CONFIG_SYS_PCIE1_IO_PHYS_LOW CONFIG_SYS_PCIE1_IO_VIRT |
310 | #define CONFIG_SYS_PCIE1_IO_PHYS \ | |
311 | PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \ | |
312 | CONFIG_SYS_PHYS_ADDR_HIGH) | |
46f3e385 | 313 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64K */ |
debb7354 | 314 | |
4c78d4a6 BB |
315 | #ifdef CONFIG_PHYS_64BIT |
316 | /* | |
46f3e385 | 317 | * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT. |
4c78d4a6 BB |
318 | * This will increase the amount of PCI address space available for |
319 | * for mapping RAM. | |
320 | */ | |
46f3e385 | 321 | #define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE1_MEM_BUS |
4c78d4a6 | 322 | #else |
46f3e385 KG |
323 | #define CONFIG_SYS_PCIE2_MEM_BUS (CONFIG_SYS_PCIE1_MEM_BUS \ |
324 | + CONFIG_SYS_PCIE1_MEM_SIZE) | |
4c78d4a6 | 325 | #endif |
46f3e385 KG |
326 | #define CONFIG_SYS_PCIE2_MEM_VIRT (CONFIG_SYS_PCIE1_MEM_VIRT \ |
327 | + CONFIG_SYS_PCIE1_MEM_SIZE) | |
1605cc9e BB |
328 | #define CONFIG_SYS_PCIE2_MEM_PHYS_LOW (CONFIG_SYS_PCIE1_MEM_PHYS_LOW \ |
329 | + CONFIG_SYS_PCIE1_MEM_SIZE) | |
330 | #define CONFIG_SYS_PCIE2_MEM_PHYS_HIGH CONFIG_SYS_PCIE1_MEM_PHYS_HIGH | |
46f3e385 KG |
331 | #define CONFIG_SYS_PCIE2_MEM_PHYS (CONFIG_SYS_PCIE1_MEM_PHYS \ |
332 | + CONFIG_SYS_PCIE1_MEM_SIZE) | |
333 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ | |
334 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
335 | #define CONFIG_SYS_PCIE2_IO_VIRT (CONFIG_SYS_PCIE1_IO_VIRT \ | |
336 | + CONFIG_SYS_PCIE1_IO_SIZE) | |
1605cc9e BB |
337 | #define CONFIG_SYS_PCIE2_IO_PHYS_LOW (CONFIG_SYS_PCIE1_IO_PHYS_LOW \ |
338 | + CONFIG_SYS_PCIE1_IO_SIZE) | |
46f3e385 KG |
339 | #define CONFIG_SYS_PCIE2_IO_PHYS (CONFIG_SYS_PCIE1_IO_PHYS \ |
340 | + CONFIG_SYS_PCIE1_IO_SIZE) | |
341 | #define CONFIG_SYS_PCIE2_IO_SIZE CONFIG_SYS_PCIE1_IO_SIZE | |
debb7354 | 342 | |
debb7354 JL |
343 | #if defined(CONFIG_PCI) |
344 | ||
53677ef1 | 345 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
debb7354 | 346 | |
debb7354 JL |
347 | #undef CONFIG_EEPRO100 |
348 | #undef CONFIG_TULIP | |
349 | ||
a81d1c0b ZW |
350 | /************************************************************ |
351 | * USB support | |
352 | ************************************************************/ | |
53677ef1 | 353 | #define CONFIG_PCI_OHCI 1 |
a81d1c0b | 354 | #define CONFIG_USB_OHCI_NEW 1 |
6d0f6bcf JCPV |
355 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" |
356 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 | |
357 | #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 | |
a81d1c0b | 358 | |
0f460a1e | 359 | /*PCIE video card used*/ |
46f3e385 | 360 | #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT |
0f460a1e JJ |
361 | |
362 | /*PCI video card used*/ | |
46f3e385 | 363 | /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT*/ |
0f460a1e JJ |
364 | |
365 | /* video */ | |
0f460a1e JJ |
366 | |
367 | #if defined(CONFIG_VIDEO) | |
368 | #define CONFIG_BIOSEMU | |
0f460a1e JJ |
369 | #define CONFIG_ATI_RADEON_FB |
370 | #define CONFIG_VIDEO_LOGO | |
46f3e385 | 371 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT |
0f460a1e JJ |
372 | #endif |
373 | ||
debb7354 | 374 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
debb7354 | 375 | |
dabf9ef8 JZ |
376 | #ifdef CONFIG_SCSI_AHCI |
377 | #define CONFIG_SATA_ULI5288 | |
6d0f6bcf JCPV |
378 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 |
379 | #define CONFIG_SYS_SCSI_MAX_LUN 1 | |
380 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) | |
381 | #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE | |
dabf9ef8 JZ |
382 | #endif |
383 | ||
debb7354 JL |
384 | #endif /* CONFIG_PCI */ |
385 | ||
debb7354 JL |
386 | #if defined(CONFIG_TSEC_ENET) |
387 | ||
debb7354 JL |
388 | #define CONFIG_MII 1 /* MII PHY management */ |
389 | ||
53677ef1 WD |
390 | #define CONFIG_TSEC1 1 |
391 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
392 | #define CONFIG_TSEC2 1 | |
393 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
394 | #define CONFIG_TSEC3 1 | |
395 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
396 | #define CONFIG_TSEC4 1 | |
397 | #define CONFIG_TSEC4_NAME "eTSEC4" | |
debb7354 | 398 | |
debb7354 JL |
399 | #define TSEC1_PHY_ADDR 0 |
400 | #define TSEC2_PHY_ADDR 1 | |
401 | #define TSEC3_PHY_ADDR 2 | |
402 | #define TSEC4_PHY_ADDR 3 | |
403 | #define TSEC1_PHYIDX 0 | |
404 | #define TSEC2_PHYIDX 0 | |
405 | #define TSEC3_PHYIDX 0 | |
406 | #define TSEC4_PHYIDX 0 | |
3a79013e AF |
407 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
408 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
409 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
410 | #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
debb7354 JL |
411 | |
412 | #define CONFIG_ETHPRIME "eTSEC1" | |
413 | ||
414 | #endif /* CONFIG_TSEC_ENET */ | |
415 | ||
1605cc9e | 416 | #ifdef CONFIG_PHYS_64BIT |
3111d32c BB |
417 | #define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8) |
418 | #define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2) | |
419 | ||
1605cc9e BB |
420 | /* Put physical address into the BAT format */ |
421 | #define BAT_PHYS_ADDR(low, high) \ | |
422 | (low | PHYS_HIGH_TO_BXPN(high) | PHYS_HIGH_TO_BX(high)) | |
423 | /* Convert high/low pairs to actual 64-bit value */ | |
424 | #define PAIRED_PHYS_TO_PHYS(low, high) (low | ((u64)high << 32)) | |
425 | #else | |
426 | /* 32-bit systems just ignore the "high" bits */ | |
427 | #define BAT_PHYS_ADDR(low, high) (low) | |
428 | #define PAIRED_PHYS_TO_PHYS(low, high) (low) | |
429 | #endif | |
430 | ||
586d1d5a | 431 | /* |
c759a01a | 432 | * BAT0 DDR |
debb7354 | 433 | */ |
6d0f6bcf | 434 | #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) |
9ff32d8c | 435 | #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) |
debb7354 | 436 | |
586d1d5a | 437 | /* |
c759a01a | 438 | * BAT1 LBC (PIXIS/CF) |
af5d100e | 439 | */ |
1605cc9e BB |
440 | #define CONFIG_SYS_DBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \ |
441 | CONFIG_SYS_PHYS_ADDR_HIGH) \ | |
3111d32c BB |
442 | | BATL_PP_RW | BATL_CACHEINHIBIT | \ |
443 | BATL_GUARDEDSTORAGE) | |
c759a01a BB |
444 | #define CONFIG_SYS_DBAT1U (CONFIG_SYS_LBC_BASE | BATU_BL_128K \ |
445 | | BATU_VS | BATU_VP) | |
1605cc9e BB |
446 | #define CONFIG_SYS_IBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \ |
447 | CONFIG_SYS_PHYS_ADDR_HIGH) \ | |
3111d32c | 448 | | BATL_PP_RW | BATL_MEMCOHERENCE) |
c759a01a | 449 | #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U |
af5d100e BB |
450 | |
451 | /* if CONFIG_PCI: | |
46f3e385 | 452 | * BAT2 PCIE1 and PCIE1 MEM |
af5d100e | 453 | * if CONFIG_RIO |
c759a01a | 454 | * BAT2 Rapidio Memory |
debb7354 | 455 | */ |
af5d100e | 456 | #ifdef CONFIG_PCI |
842033e6 | 457 | #define CONFIG_PCI_INDIRECT_BRIDGE |
1605cc9e BB |
458 | #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \ |
459 | CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \ | |
3111d32c BB |
460 | | BATL_PP_RW | BATL_CACHEINHIBIT \ |
461 | | BATL_GUARDEDSTORAGE) | |
46f3e385 | 462 | #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \ |
af5d100e | 463 | | BATU_VS | BATU_VP) |
1605cc9e BB |
464 | #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \ |
465 | CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \ | |
3111d32c | 466 | | BATL_PP_RW | BATL_CACHEINHIBIT) |
af5d100e BB |
467 | #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U |
468 | #else /* CONFIG_RIO */ | |
1605cc9e BB |
469 | #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \ |
470 | CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \ | |
3111d32c BB |
471 | | BATL_PP_RW | BATL_CACHEINHIBIT | \ |
472 | BATL_GUARDEDSTORAGE) | |
1b77ca8a | 473 | #define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \ |
3111d32c | 474 | | BATU_VS | BATU_VP) |
1605cc9e BB |
475 | #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \ |
476 | CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \ | |
3111d32c | 477 | | BATL_PP_RW | BATL_CACHEINHIBIT) |
6d0f6bcf | 478 | #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U |
af5d100e | 479 | #endif |
debb7354 | 480 | |
586d1d5a | 481 | /* |
c759a01a | 482 | * BAT3 CCSR Space |
debb7354 | 483 | */ |
1605cc9e BB |
484 | #define CONFIG_SYS_DBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \ |
485 | CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ | |
3111d32c BB |
486 | | BATL_PP_RW | BATL_CACHEINHIBIT \ |
487 | | BATL_GUARDEDSTORAGE) | |
c759a01a BB |
488 | #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \ |
489 | | BATU_VP) | |
1605cc9e BB |
490 | #define CONFIG_SYS_IBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \ |
491 | CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ | |
3111d32c | 492 | | BATL_PP_RW | BATL_CACHEINHIBIT) |
6d0f6bcf | 493 | #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U |
debb7354 | 494 | |
3111d32c BB |
495 | #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) |
496 | #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ | |
497 | | BATL_PP_RW | BATL_CACHEINHIBIT \ | |
498 | | BATL_GUARDEDSTORAGE) | |
499 | #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ | |
500 | | BATU_BL_1M | BATU_VS | BATU_VP) | |
501 | #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ | |
502 | | BATL_PP_RW | BATL_CACHEINHIBIT) | |
503 | #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU | |
504 | #endif | |
505 | ||
586d1d5a | 506 | /* |
46f3e385 | 507 | * BAT4 PCIE1_IO and PCIE2_IO |
debb7354 | 508 | */ |
1605cc9e BB |
509 | #define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \ |
510 | CONFIG_SYS_PHYS_ADDR_HIGH) \ | |
3111d32c BB |
511 | | BATL_PP_RW | BATL_CACHEINHIBIT \ |
512 | | BATL_GUARDEDSTORAGE) | |
46f3e385 | 513 | #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \ |
c759a01a | 514 | | BATU_VS | BATU_VP) |
1605cc9e BB |
515 | #define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \ |
516 | CONFIG_SYS_PHYS_ADDR_HIGH) \ | |
3111d32c | 517 | | BATL_PP_RW | BATL_CACHEINHIBIT) |
6d0f6bcf | 518 | #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U |
debb7354 | 519 | |
586d1d5a | 520 | /* |
c759a01a | 521 | * BAT5 Init RAM for stack in the CPU DCache (no backing memory) |
debb7354 | 522 | */ |
6d0f6bcf JCPV |
523 | #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) |
524 | #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) | |
525 | #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L | |
526 | #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U | |
debb7354 | 527 | |
586d1d5a | 528 | /* |
c759a01a | 529 | * BAT6 FLASH |
debb7354 | 530 | */ |
1605cc9e BB |
531 | #define CONFIG_SYS_DBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \ |
532 | CONFIG_SYS_PHYS_ADDR_HIGH) \ | |
3111d32c BB |
533 | | BATL_PP_RW | BATL_CACHEINHIBIT \ |
534 | | BATL_GUARDEDSTORAGE) | |
170deacb BB |
535 | #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \ |
536 | | BATU_VP) | |
1605cc9e BB |
537 | #define CONFIG_SYS_IBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \ |
538 | CONFIG_SYS_PHYS_ADDR_HIGH) \ | |
3111d32c | 539 | | BATL_PP_RW | BATL_MEMCOHERENCE) |
6d0f6bcf | 540 | #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U |
debb7354 | 541 | |
bf9a8c34 BB |
542 | /* Map the last 1M of flash where we're running from reset */ |
543 | #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ | |
544 | | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
14d0a02a | 545 | #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) |
bf9a8c34 BB |
546 | #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ |
547 | | BATL_MEMCOHERENCE) | |
548 | #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY | |
549 | ||
c759a01a BB |
550 | /* |
551 | * BAT7 FREE - used later for tmp mappings | |
552 | */ | |
6d0f6bcf JCPV |
553 | #define CONFIG_SYS_DBAT7L 0x00000000 |
554 | #define CONFIG_SYS_DBAT7U 0x00000000 | |
555 | #define CONFIG_SYS_IBAT7L 0x00000000 | |
556 | #define CONFIG_SYS_IBAT7U 0x00000000 | |
debb7354 | 557 | |
debb7354 JL |
558 | /* |
559 | * Environment | |
560 | */ | |
6d0f6bcf | 561 | #ifndef CONFIG_SYS_RAMBOOT |
221fbd22 SW |
562 | #define CONFIG_ENV_ADDR \ |
563 | (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) | |
0e8d1586 | 564 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ |
5c9efb36 | 565 | #else |
6d0f6bcf | 566 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
5c9efb36 | 567 | #endif |
0f2d6602 | 568 | #define CONFIG_ENV_SIZE 0x2000 |
debb7354 JL |
569 | |
570 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 571 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
debb7354 | 572 | |
659e2f67 JL |
573 | /* |
574 | * BOOTP options | |
575 | */ | |
576 | #define CONFIG_BOOTP_BOOTFILESIZE | |
577 | #define CONFIG_BOOTP_BOOTPATH | |
578 | #define CONFIG_BOOTP_GATEWAY | |
579 | #define CONFIG_BOOTP_HOSTNAME | |
580 | ||
debb7354 JL |
581 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
582 | ||
583 | /* | |
584 | * Miscellaneous configurable options | |
585 | */ | |
6d0f6bcf | 586 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
53677ef1 | 587 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
6d0f6bcf | 588 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
debb7354 | 589 | |
debb7354 JL |
590 | /* |
591 | * For booting Linux, the board info and command line data | |
592 | * have to be in the first 8 MB of memory, since this is | |
593 | * the maximum mapped by the Linux kernel during initialization. | |
594 | */ | |
e1efe43c SW |
595 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ |
596 | #define CONFIG_SYS_BOOTM_LEN (256 << 20) /* Increase max gunzip size */ | |
debb7354 | 597 | |
2f9c19e4 JL |
598 | #if defined(CONFIG_CMD_KGDB) |
599 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
debb7354 JL |
600 | #endif |
601 | ||
debb7354 JL |
602 | /* |
603 | * Environment Configuration | |
604 | */ | |
605 | ||
10327dc5 | 606 | #define CONFIG_HAS_ETH0 1 |
5c9efb36 JL |
607 | #define CONFIG_HAS_ETH1 1 |
608 | #define CONFIG_HAS_ETH2 1 | |
609 | #define CONFIG_HAS_ETH3 1 | |
debb7354 | 610 | |
18b6c8cd | 611 | #define CONFIG_IPADDR 192.168.1.100 |
debb7354 JL |
612 | |
613 | #define CONFIG_HOSTNAME unknown | |
8b3637c6 | 614 | #define CONFIG_ROOTPATH "/opt/nfsroot" |
b3f44c21 | 615 | #define CONFIG_BOOTFILE "uImage" |
32922cdc | 616 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ |
debb7354 | 617 | |
5c9efb36 | 618 | #define CONFIG_SERVERIP 192.168.1.1 |
18b6c8cd | 619 | #define CONFIG_GATEWAYIP 192.168.1.1 |
5c9efb36 | 620 | #define CONFIG_NETMASK 255.255.255.0 |
debb7354 | 621 | |
5c9efb36 | 622 | /* default location for tftp and bootm */ |
e1efe43c | 623 | #define CONFIG_LOADADDR 0x10000000 |
debb7354 | 624 | |
53677ef1 WD |
625 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
626 | "netdev=eth0\0" \ | |
5368c55d | 627 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ |
53677ef1 | 628 | "tftpflash=tftpboot $loadaddr $uboot; " \ |
5368c55d MV |
629 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ |
630 | " +$filesize; " \ | |
631 | "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
632 | " +$filesize; " \ | |
633 | "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
634 | " $filesize; " \ | |
635 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
636 | " +$filesize; " \ | |
637 | "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
638 | " $filesize\0" \ | |
53677ef1 | 639 | "consoledev=ttyS0\0" \ |
e1efe43c | 640 | "ramdiskaddr=0x18000000\0" \ |
53677ef1 | 641 | "ramdiskfile=your.ramdisk.u-boot\0" \ |
e1efe43c | 642 | "fdtaddr=0x17c00000\0" \ |
53677ef1 | 643 | "fdtfile=mpc8641_hpcn.dtb\0" \ |
3111d32c BB |
644 | "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0" \ |
645 | "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \ | |
53677ef1 WD |
646 | "maxcpus=2" |
647 | ||
53677ef1 WD |
648 | #define CONFIG_NFSBOOTCOMMAND \ |
649 | "setenv bootargs root=/dev/nfs rw " \ | |
650 | "nfsroot=$serverip:$rootpath " \ | |
651 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
652 | "console=$consoledev,$baudrate $othbootargs;" \ | |
653 | "tftp $loadaddr $bootfile;" \ | |
654 | "tftp $fdtaddr $fdtfile;" \ | |
655 | "bootm $loadaddr - $fdtaddr" | |
656 | ||
657 | #define CONFIG_RAMBOOTCOMMAND \ | |
658 | "setenv bootargs root=/dev/ram rw " \ | |
659 | "console=$consoledev,$baudrate $othbootargs;" \ | |
660 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
661 | "tftp $loadaddr $bootfile;" \ | |
662 | "tftp $fdtaddr $fdtfile;" \ | |
663 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
debb7354 JL |
664 | |
665 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
666 | ||
667 | #endif /* __CONFIG_H */ |