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c2042f59 | 1 | /* |
2 | * Configuation settings for the Renesas Solutions Migo-R board | |
3 | * | |
4 | * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | #ifndef __MIGO_R_H | |
26 | #define __MIGO_R_H | |
27 | ||
28 | #undef DEBUG | |
29 | #define CONFIG_SH 1 | |
30 | #define CONFIG_SH4 1 | |
31 | #define CONFIG_CPU_SH7722 1 | |
32 | #define CONFIG_MIGO_R 1 | |
33 | ||
34 | #define CONFIG_CMD_LOADB | |
35 | #define CONFIG_CMD_LOADS | |
36 | #define CONFIG_CMD_FLASH | |
37 | #define CONFIG_CMD_MEMORY | |
38 | #define CONFIG_CMD_NET | |
39 | #define CONFIG_CMD_PING | |
40 | #define CONFIG_CMD_NFS | |
c2042f59 | 41 | #define CONFIG_CMD_SDRAM |
bdab39d3 | 42 | #define CONFIG_CMD_SAVEENV |
c2042f59 | 43 | |
44 | #define CONFIG_BAUDRATE 115200 | |
45 | #define CONFIG_BOOTDELAY 3 | |
46 | #define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01" | |
c2042f59 | 47 | |
48 | #define CONFIG_VERSION_VARIABLE | |
49 | #undef CONFIG_SHOW_BOOT_PROGRESS | |
50 | ||
51 | /* SMC9111 */ | |
7194ab80 | 52 | #define CONFIG_SMC91111 |
c2042f59 | 53 | #define CONFIG_SMC91111_BASE (0xB0000000) |
54 | ||
55 | /* MEMORY */ | |
56 | #define MIGO_R_SDRAM_BASE (0x8C000000) | |
57 | #define MIGO_R_FLASH_BASE_1 (0xA0000000) | |
58 | #define MIGO_R_FLASH_BANK_SIZE (64 * 1024 * 1024) | |
59 | ||
8cd7379e | 60 | #define CONFIG_SYS_TEXT_BASE 0x8FFC0000 |
6d0f6bcf JCPV |
61 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
62 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
63 | #define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */ | |
64 | #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ | |
65 | #define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */ | |
66 | #define CONFIG_SYS_BARGSIZE 512 /* Buffer size for Boot Arguments passed to kernel */ | |
67 | #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */ | |
c2042f59 | 68 | |
69 | /* SCIF */ | |
6c58a030 | 70 | #define CONFIG_SCIF_CONSOLE 1 |
c2042f59 | 71 | #define CONFIG_CONS_SCIF0 1 |
6d0f6bcf | 72 | #undef CONFIG_SYS_CONSOLE_INFO_QUIET /* Suppress display of console |
c2042f59 | 73 | information at boot */ |
6d0f6bcf JCPV |
74 | #undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE |
75 | #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE | |
c2042f59 | 76 | |
6d0f6bcf JCPV |
77 | #define CONFIG_SYS_MEMTEST_START (MIGO_R_SDRAM_BASE) |
78 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024)) | |
c2042f59 | 79 | |
80 | /* Enable alternate, more extensive, memory test */ | |
6d0f6bcf | 81 | #undef CONFIG_SYS_ALT_MEMTEST |
c2042f59 | 82 | /* Scratch address used by the alternate memory test */ |
6d0f6bcf | 83 | #undef CONFIG_SYS_MEMTEST_SCRATCH |
c2042f59 | 84 | |
85 | /* Enable temporary baudrate change while serial download */ | |
6d0f6bcf | 86 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE |
c2042f59 | 87 | |
6d0f6bcf | 88 | #define CONFIG_SYS_SDRAM_BASE (MIGO_R_SDRAM_BASE) |
c2042f59 | 89 | /* maybe more, but if so u-boot doesn't know about it... */ |
6d0f6bcf | 90 | #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) |
c2042f59 | 91 | /* default load address for scripts ?!? */ |
6d0f6bcf | 92 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024) |
c2042f59 | 93 | |
94 | /* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */ | |
6d0f6bcf | 95 | #define CONFIG_SYS_MONITOR_BASE (MIGO_R_FLASH_BASE_1) |
c2042f59 | 96 | /* Monitor size */ |
6d0f6bcf | 97 | #define CONFIG_SYS_MONITOR_LEN (128 * 1024) |
c2042f59 | 98 | /* Size of DRAM reserved for malloc() use */ |
6d0f6bcf | 99 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) |
6d0f6bcf | 100 | #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) |
c2042f59 | 101 | |
102 | /* FLASH */ | |
6d0f6bcf | 103 | #define CONFIG_SYS_FLASH_CFI |
00b1883a | 104 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf | 105 | #undef CONFIG_SYS_FLASH_QUIET_TEST |
c2042f59 | 106 | /* print 'E' for empty sector on flinfo */ |
6d0f6bcf | 107 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
c2042f59 | 108 | /* Physical start address of Flash memory */ |
6d0f6bcf | 109 | #define CONFIG_SYS_FLASH_BASE (MIGO_R_FLASH_BASE_1) |
c2042f59 | 110 | /* Max number of sectors on each Flash chip */ |
6d0f6bcf | 111 | #define CONFIG_SYS_MAX_FLASH_SECT 512 |
c2042f59 | 112 | |
113 | /* if you use all NOR Flash , you change dip-switch. Please see MIGO_R01 Manual. */ | |
6d0f6bcf JCPV |
114 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
115 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + (0 * MIGO_R_FLASH_BANK_SIZE) } | |
c2042f59 | 116 | |
117 | /* Timeout for Flash erase operations (in ms) */ | |
6d0f6bcf | 118 | #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) |
c2042f59 | 119 | /* Timeout for Flash write operations (in ms) */ |
6d0f6bcf | 120 | #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) |
c2042f59 | 121 | /* Timeout for Flash set sector lock bit operations (in ms) */ |
6d0f6bcf | 122 | #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) |
c2042f59 | 123 | /* Timeout for Flash clear lock bit operations (in ms) */ |
6d0f6bcf | 124 | #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) |
c2042f59 | 125 | |
126 | /* Use hardware flash sectors protection instead of U-Boot software protection */ | |
6d0f6bcf JCPV |
127 | #undef CONFIG_SYS_FLASH_PROTECTION |
128 | #undef CONFIG_SYS_DIRECT_FLASH_TFTP | |
c2042f59 | 129 | |
130 | /* ENV setting */ | |
5a1aceb0 | 131 | #define CONFIG_ENV_IS_IN_FLASH |
c2042f59 | 132 | #define CONFIG_ENV_OVERWRITE 1 |
0e8d1586 JCPV |
133 | #define CONFIG_ENV_SECT_SIZE (128 * 1024) |
134 | #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) | |
6d0f6bcf JCPV |
135 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) |
136 | /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */ | |
137 | #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) | |
0e8d1586 | 138 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) |
c2042f59 | 139 | |
140 | /* Board Clock */ | |
141 | #define CONFIG_SYS_CLK_FREQ 33333333 | |
be45c632 | 142 | #define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */ |
8dd29c87 | 143 | #define CONFIG_SYS_HZ 1000 |
c2042f59 | 144 | |
145 | #endif /* __MIGO_R_H */ |