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Commit | Line | Data |
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b6e4c403 WD |
1 | /* |
2 | * (C) Copyright 2003 | |
3 | * Denis Peter d.peter@mpl.ch | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
b6e4c403 WD |
6 | */ |
7 | ||
8 | /* | |
9 | * File: PATI.h | |
10 | */ | |
11 | ||
12 | #ifndef __CONFIG_H | |
13 | #define __CONFIG_H | |
14 | ||
15 | /* | |
16 | * High Level Configuration Options | |
17 | */ | |
18 | ||
19 | #define CONFIG_MPC555 1 /* This is an MPC555 CPU */ | |
53677ef1 | 20 | #define CONFIG_PATI 1 /* ...On a PATI board */ |
2ae18241 WD |
21 | |
22 | #define CONFIG_SYS_TEXT_BASE 0xFFF00000 | |
23 | ||
b6e4c403 WD |
24 | /* Serial Console Configuration */ |
25 | #define CONFIG_5xx_CONS_SCI1 | |
26 | #undef CONFIG_5xx_CONS_SCI2 | |
27 | ||
a1aa0bb5 JL |
28 | /* |
29 | * BOOTP options | |
30 | */ | |
31 | #define CONFIG_BOOTP_BOOTFILESIZE | |
32 | #define CONFIG_BOOTP_BOOTPATH | |
33 | #define CONFIG_BOOTP_GATEWAY | |
34 | #define CONFIG_BOOTP_HOSTNAME | |
35 | ||
acf02697 JL |
36 | /* |
37 | * Command line configuration. | |
38 | */ | |
acf02697 | 39 | #define CONFIG_CMD_REGINFO |
acf02697 | 40 | #define CONFIG_CMD_REGINFO |
acf02697 | 41 | |
53677ef1 | 42 | #define CONFIG_BOOTCOMMAND "" /* autoboot command */ |
b6e4c403 WD |
43 | |
44 | #define CONFIG_BOOTARGS "" /* */ | |
45 | ||
53677ef1 | 46 | #define CONFIG_WATCHDOG /* turn on platform specific watchdog */ |
b6e4c403 | 47 | |
b6e4c403 WD |
48 | #define CONFIG_LOADS_ECHO 1 /* Echo on for serial download */ |
49 | ||
50 | /* | |
51 | * Miscellaneous configurable options | |
52 | */ | |
b6e4c403 WD |
53 | #define CONFIG_PREBOOT |
54 | ||
6d0f6bcf | 55 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
acf02697 | 56 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 57 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
b6e4c403 | 58 | #else |
6d0f6bcf | 59 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
b6e4c403 | 60 | #endif |
6d0f6bcf JCPV |
61 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
62 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
63 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
b6e4c403 | 64 | |
6d0f6bcf JCPV |
65 | #define CONFIG_SYS_MEMTEST_START 0x00010000 /* memtest works on */ |
66 | #define CONFIG_SYS_MEMTEST_END 0x00A00000 /* 10 MB in SRAM */ | |
b6e4c403 | 67 | |
6d0f6bcf | 68 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
b6e4c403 | 69 | |
6d0f6bcf | 70 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 1250000 } |
b6e4c403 | 71 | |
b6e4c403 WD |
72 | /*********************************************************************** |
73 | * Last Stage Init | |
74 | ***********************************************************************/ | |
75 | #define CONFIG_LAST_STAGE_INIT | |
76 | ||
77 | /* | |
78 | * Low Level Configuration Settings | |
79 | */ | |
80 | ||
81 | /* | |
82 | * Internal Memory Mapped (This is not the IMMR content) | |
83 | */ | |
6d0f6bcf | 84 | #define CONFIG_SYS_IMMR 0x01C00000 /* Physical start adress of internal memory map */ |
b6e4c403 WD |
85 | |
86 | /* | |
87 | * Definitions for initial stack pointer and data area | |
88 | */ | |
6d0f6bcf | 89 | #define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */ |
553f0982 | 90 | #define CONFIG_SYS_INIT_RAM_SIZE (CONFIG_SYS_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */ |
25ddd1fb | 91 | #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_RAM_ADDR) - GENERATED_GBL_DATA_SIZE) /* Offset from the beginning of ram */ |
6d0f6bcf | 92 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_IMMR + 0x03fa000) /* Physical start adress of inital stack */ |
b6e4c403 WD |
93 | /* |
94 | * Start addresses for the final memory configuration | |
6d0f6bcf | 95 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
b6e4c403 | 96 | */ |
6d0f6bcf JCPV |
97 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */ |
98 | #define CONFIG_SYS_FLASH_BASE 0xffC00000 /* External flash */ | |
b6e4c403 WD |
99 | #define PCI_BASE 0x03000000 /* PCI Base (CS2) */ |
100 | #define PCI_CONFIG_BASE 0x04000000 /* PCI & PLD (CS3) */ | |
101 | #define PLD_CONFIG_BASE 0x04001000 /* PLD (CS3) */ | |
102 | ||
6d0f6bcf | 103 | #define CONFIG_SYS_MONITOR_BASE 0xFFF00000 |
14d0a02a | 104 | /* CONFIG_SYS_FLASH_BASE */ /* CONFIG_SYS_TEXT_BASE is defined in the board config.mk file. */ |
53677ef1 WD |
105 | /* This adress is given to the linker with -Ttext to */ |
106 | /* locate the text section at this adress. */ | |
6d0f6bcf JCPV |
107 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 192 kB for Monitor */ |
108 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
b6e4c403 | 109 | |
6d0f6bcf | 110 | #define CONFIG_SYS_RESET_ADDRESS (PLD_CONFIG_BASE + 0x10) /* Adress which causes reset */ |
b6e4c403 WD |
111 | |
112 | /* | |
113 | * For booting Linux, the board info and command line data | |
114 | * have to be in the first 8 MB of memory, since this is | |
115 | * the maximum mapped by the Linux kernel during initialization. | |
116 | */ | |
6d0f6bcf | 117 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
b6e4c403 | 118 | |
b6e4c403 WD |
119 | /*----------------------------------------------------------------------- |
120 | * FLASH organization | |
121 | *----------------------------------------------------------------------- | |
122 | * | |
123 | */ | |
124 | ||
d49f5b1c DM |
125 | #define CONFIG_SYS_FLASH_PROTECTION |
126 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
b6e4c403 | 127 | |
d49f5b1c DM |
128 | #define CONFIG_SYS_FLASH_CFI |
129 | #define CONFIG_FLASH_CFI_DRIVER | |
130 | ||
131 | #define CONFIG_FLASH_SHOW_PROGRESS 45 | |
132 | ||
133 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
134 | #define CONFIG_SYS_MAX_FLASH_SECT 128 | |
b6e4c403 | 135 | |
bb1f8b4f JCPV |
136 | #define CONFIG_ENV_IS_IN_EEPROM |
137 | #ifdef CONFIG_ENV_IS_IN_EEPROM | |
0e8d1586 JCPV |
138 | #define CONFIG_ENV_OFFSET 0 |
139 | #define CONFIG_ENV_SIZE 2048 | |
b6e4c403 WD |
140 | #endif |
141 | ||
5a1aceb0 JCPV |
142 | #undef CONFIG_ENV_IS_IN_FLASH |
143 | #ifdef CONFIG_ENV_IS_IN_FLASH | |
0e8d1586 | 144 | #define CONFIG_ENV_SIZE 0x00002000 /* Set whole sector as env */ |
6d0f6bcf | 145 | #define CONFIG_ENV_OFFSET ((0 - CONFIG_SYS_FLASH_BASE) - CONFIG_ENV_SIZE) /* Environment starts at this adress */ |
b6e4c403 WD |
146 | #endif |
147 | ||
b6e4c403 | 148 | #define CONFIG_SPI 1 |
6d0f6bcf JCPV |
149 | #define CONFIG_SYS_SPI_CS_USED 0x09 /* CS0 and CS3 are used */ |
150 | #define CONFIG_SYS_SPI_CS_BASE 0x08 /* CS3 is active low */ | |
151 | #define CONFIG_SYS_SPI_CS_ACT 0x00 /* CS3 is active low */ | |
b6e4c403 WD |
152 | /*----------------------------------------------------------------------- |
153 | * SYPCR - System Protection Control | |
154 | * SYPCR can only be written once after reset! | |
155 | *----------------------------------------------------------------------- | |
156 | * SW Watchdog freeze | |
157 | */ | |
158 | #undef CONFIG_WATCHDOG | |
159 | #if defined(CONFIG_WATCHDOG) | |
6d0f6bcf | 160 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
b6e4c403 WD |
161 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
162 | #else | |
6d0f6bcf | 163 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
b6e4c403 WD |
164 | SYPCR_SWP) |
165 | #endif /* CONFIG_WATCHDOG */ | |
166 | ||
b6e4c403 WD |
167 | /*----------------------------------------------------------------------- |
168 | * TBSCR - Time Base Status and Control | |
169 | *----------------------------------------------------------------------- | |
170 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
171 | */ | |
6d0f6bcf | 172 | #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
b6e4c403 WD |
173 | |
174 | /*----------------------------------------------------------------------- | |
175 | * PISCR - Periodic Interrupt Status and Control | |
176 | *----------------------------------------------------------------------- | |
177 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
178 | */ | |
6d0f6bcf | 179 | #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
b6e4c403 WD |
180 | |
181 | /*----------------------------------------------------------------------- | |
182 | * SCCR - System Clock and reset Control Register | |
183 | *----------------------------------------------------------------------- | |
184 | * Set clock output, timebase and RTC source and divider, | |
185 | * power management and some other internal clocks | |
186 | */ | |
187 | #define SCCR_MASK SCCR_EBDF00 | |
6d0f6bcf | 188 | #define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_RTDIV | SCCR_RTSEL | \ |
b6e4c403 WD |
189 | SCCR_COM01 | SCCR_DFNL000 | SCCR_DFNH000) |
190 | ||
191 | /*----------------------------------------------------------------------- | |
192 | * SIUMCR - SIU Module Configuration | |
193 | *----------------------------------------------------------------------- | |
194 | * Data show cycle | |
195 | */ | |
6d0f6bcf | 196 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_EARB | SIUMCR_GPC01 | SIUMCR_MLRC11) /* Disable data show cycle */ |
b6e4c403 WD |
197 | |
198 | /*----------------------------------------------------------------------- | |
199 | * PLPRCR - PLL, Low-Power, and Reset Control Register | |
200 | *----------------------------------------------------------------------- | |
201 | * Set all bits to 40 Mhz | |
202 | * | |
203 | */ | |
6d0f6bcf | 204 | #define CONFIG_SYS_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */ |
b6e4c403 | 205 | |
6d0f6bcf | 206 | #define CONFIG_SYS_PLPRCR (PLPRCR_MF_9 | PLPRCR_DIVF_0) |
b6e4c403 WD |
207 | |
208 | /*----------------------------------------------------------------------- | |
209 | * UMCR - UIMB Module Configuration Register | |
210 | *----------------------------------------------------------------------- | |
211 | * | |
212 | */ | |
6d0f6bcf | 213 | #define CONFIG_SYS_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */ |
b6e4c403 WD |
214 | |
215 | /*----------------------------------------------------------------------- | |
216 | * ICTRL - I-Bus Support Control Register | |
217 | */ | |
6d0f6bcf | 218 | #define CONFIG_SYS_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */ |
b6e4c403 WD |
219 | |
220 | /*----------------------------------------------------------------------- | |
221 | * USIU - Memory Controller Register | |
222 | *----------------------------------------------------------------------- | |
223 | */ | |
6d0f6bcf JCPV |
224 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_V | BR_BI | BR_PS_16 | BR_SETA) |
225 | #define CONFIG_SYS_OR0_PRELIM (0xffc00000) /* SCY is not used if external TA is set */ | |
b6e4c403 | 226 | /* SDRAM */ |
6d0f6bcf JCPV |
227 | #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_SDRAM_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA) |
228 | #define CONFIG_SYS_OR1_PRELIM (OR_ADDR_MK_FF) /* SCY is not used if external TA is set */ | |
b6e4c403 | 229 | /* PCI */ |
6d0f6bcf JCPV |
230 | #define CONFIG_SYS_BR2_PRELIM (PCI_BASE | BR_V | BR_PS_32 | BR_SETA) |
231 | #define CONFIG_SYS_OR2_PRELIM (OR_ADDR_MK_FF) | |
b6e4c403 | 232 | /* config registers: */ |
6d0f6bcf JCPV |
233 | #define CONFIG_SYS_BR3_PRELIM (PCI_CONFIG_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA) |
234 | #define CONFIG_SYS_OR3_PRELIM (0xffff0000) | |
b6e4c403 | 235 | |
6d0f6bcf | 236 | #define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* We don't realign the flash */ |
b6e4c403 WD |
237 | |
238 | /*----------------------------------------------------------------------- | |
239 | * DER - Timer Decrementer | |
240 | *----------------------------------------------------------------------- | |
241 | * Initialise to zero | |
242 | */ | |
6d0f6bcf | 243 | #define CONFIG_SYS_DER 0x00000000 |
b6e4c403 | 244 | |
b6e4c403 | 245 | #endif /* __CONFIG_H */ |