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Commit | Line | Data |
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b6e4c403 WD |
1 | /* |
2 | * (C) Copyright 2003 | |
3 | * Denis Peter d.peter@mpl.ch | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
b6e4c403 WD |
6 | */ |
7 | ||
8 | /* | |
9 | * File: PATI.h | |
10 | */ | |
11 | ||
12 | #ifndef __CONFIG_H | |
13 | #define __CONFIG_H | |
14 | ||
15 | /* | |
16 | * High Level Configuration Options | |
17 | */ | |
18 | ||
19 | #define CONFIG_MPC555 1 /* This is an MPC555 CPU */ | |
53677ef1 | 20 | #define CONFIG_PATI 1 /* ...On a PATI board */ |
2ae18241 WD |
21 | |
22 | #define CONFIG_SYS_TEXT_BASE 0xFFF00000 | |
23 | ||
6c4c9a7c DMEA |
24 | #define CONFIG_SYS_GENERIC_BOARD |
25 | ||
b6e4c403 WD |
26 | /* Serial Console Configuration */ |
27 | #define CONFIG_5xx_CONS_SCI1 | |
28 | #undef CONFIG_5xx_CONS_SCI2 | |
29 | ||
30 | #define CONFIG_BAUDRATE 9600 | |
31 | ||
b6e4c403 | 32 | |
a1aa0bb5 JL |
33 | /* |
34 | * BOOTP options | |
35 | */ | |
36 | #define CONFIG_BOOTP_BOOTFILESIZE | |
37 | #define CONFIG_BOOTP_BOOTPATH | |
38 | #define CONFIG_BOOTP_GATEWAY | |
39 | #define CONFIG_BOOTP_HOSTNAME | |
40 | ||
41 | ||
acf02697 JL |
42 | /* |
43 | * Command line configuration. | |
44 | */ | |
acf02697 | 45 | #define CONFIG_CMD_REGINFO |
acf02697 | 46 | #define CONFIG_CMD_REGINFO |
acf02697 | 47 | #define CONFIG_CMD_BSP |
acf02697 JL |
48 | #define CONFIG_CMD_EEPROM |
49 | #define CONFIG_CMD_IRQ | |
acf02697 | 50 | |
b6e4c403 WD |
51 | |
52 | #if 0 | |
53 | #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ | |
54 | #else | |
55 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
56 | #endif | |
53677ef1 | 57 | #define CONFIG_BOOTCOMMAND "" /* autoboot command */ |
b6e4c403 WD |
58 | |
59 | #define CONFIG_BOOTARGS "" /* */ | |
60 | ||
53677ef1 | 61 | #define CONFIG_WATCHDOG /* turn on platform specific watchdog */ |
b6e4c403 | 62 | |
3a473b2a | 63 | /*#define CONFIG_STATUS_LED 1 */ /* Enable status led */ |
b6e4c403 WD |
64 | |
65 | #define CONFIG_LOADS_ECHO 1 /* Echo on for serial download */ | |
66 | ||
67 | /* | |
68 | * Miscellaneous configurable options | |
69 | */ | |
6d0f6bcf | 70 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */ |
b6e4c403 WD |
71 | #define CONFIG_PREBOOT |
72 | ||
6d0f6bcf | 73 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
acf02697 | 74 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 75 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
b6e4c403 | 76 | #else |
6d0f6bcf | 77 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
b6e4c403 | 78 | #endif |
6d0f6bcf JCPV |
79 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
80 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
81 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
b6e4c403 | 82 | |
6d0f6bcf JCPV |
83 | #define CONFIG_SYS_MEMTEST_START 0x00010000 /* memtest works on */ |
84 | #define CONFIG_SYS_MEMTEST_END 0x00A00000 /* 10 MB in SRAM */ | |
b6e4c403 | 85 | |
6d0f6bcf | 86 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
b6e4c403 | 87 | |
6d0f6bcf | 88 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 1250000 } |
b6e4c403 | 89 | |
cf7d4505 | 90 | #define CONFIG_BOARD_EARLY_INIT_F |
b6e4c403 WD |
91 | |
92 | /*********************************************************************** | |
93 | * Last Stage Init | |
94 | ***********************************************************************/ | |
95 | #define CONFIG_LAST_STAGE_INIT | |
96 | ||
97 | /* | |
98 | * Low Level Configuration Settings | |
99 | */ | |
100 | ||
101 | /* | |
102 | * Internal Memory Mapped (This is not the IMMR content) | |
103 | */ | |
6d0f6bcf | 104 | #define CONFIG_SYS_IMMR 0x01C00000 /* Physical start adress of internal memory map */ |
b6e4c403 WD |
105 | |
106 | /* | |
107 | * Definitions for initial stack pointer and data area | |
108 | */ | |
6d0f6bcf | 109 | #define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */ |
553f0982 | 110 | #define CONFIG_SYS_INIT_RAM_SIZE (CONFIG_SYS_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */ |
25ddd1fb | 111 | #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_RAM_ADDR) - GENERATED_GBL_DATA_SIZE) /* Offset from the beginning of ram */ |
6d0f6bcf | 112 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_IMMR + 0x03fa000) /* Physical start adress of inital stack */ |
b6e4c403 WD |
113 | /* |
114 | * Start addresses for the final memory configuration | |
6d0f6bcf | 115 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
b6e4c403 | 116 | */ |
6d0f6bcf JCPV |
117 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */ |
118 | #define CONFIG_SYS_FLASH_BASE 0xffC00000 /* External flash */ | |
b6e4c403 WD |
119 | #define PCI_BASE 0x03000000 /* PCI Base (CS2) */ |
120 | #define PCI_CONFIG_BASE 0x04000000 /* PCI & PLD (CS3) */ | |
121 | #define PLD_CONFIG_BASE 0x04001000 /* PLD (CS3) */ | |
122 | ||
6d0f6bcf | 123 | #define CONFIG_SYS_MONITOR_BASE 0xFFF00000 |
14d0a02a | 124 | /* CONFIG_SYS_FLASH_BASE */ /* CONFIG_SYS_TEXT_BASE is defined in the board config.mk file. */ |
53677ef1 WD |
125 | /* This adress is given to the linker with -Ttext to */ |
126 | /* locate the text section at this adress. */ | |
6d0f6bcf JCPV |
127 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 192 kB for Monitor */ |
128 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
b6e4c403 | 129 | |
6d0f6bcf | 130 | #define CONFIG_SYS_RESET_ADDRESS (PLD_CONFIG_BASE + 0x10) /* Adress which causes reset */ |
b6e4c403 WD |
131 | |
132 | /* | |
133 | * For booting Linux, the board info and command line data | |
134 | * have to be in the first 8 MB of memory, since this is | |
135 | * the maximum mapped by the Linux kernel during initialization. | |
136 | */ | |
6d0f6bcf | 137 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
b6e4c403 WD |
138 | |
139 | ||
140 | /*----------------------------------------------------------------------- | |
141 | * FLASH organization | |
142 | *----------------------------------------------------------------------- | |
143 | * | |
144 | */ | |
145 | ||
d49f5b1c DM |
146 | #define CONFIG_SYS_FLASH_PROTECTION |
147 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
b6e4c403 | 148 | |
d49f5b1c DM |
149 | #define CONFIG_SYS_FLASH_CFI |
150 | #define CONFIG_FLASH_CFI_DRIVER | |
151 | ||
152 | #define CONFIG_FLASH_SHOW_PROGRESS 45 | |
153 | ||
154 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
155 | #define CONFIG_SYS_MAX_FLASH_SECT 128 | |
b6e4c403 | 156 | |
bb1f8b4f JCPV |
157 | #define CONFIG_ENV_IS_IN_EEPROM |
158 | #ifdef CONFIG_ENV_IS_IN_EEPROM | |
0e8d1586 JCPV |
159 | #define CONFIG_ENV_OFFSET 0 |
160 | #define CONFIG_ENV_SIZE 2048 | |
b6e4c403 WD |
161 | #endif |
162 | ||
5a1aceb0 JCPV |
163 | #undef CONFIG_ENV_IS_IN_FLASH |
164 | #ifdef CONFIG_ENV_IS_IN_FLASH | |
0e8d1586 | 165 | #define CONFIG_ENV_SIZE 0x00002000 /* Set whole sector as env */ |
6d0f6bcf | 166 | #define CONFIG_ENV_OFFSET ((0 - CONFIG_SYS_FLASH_BASE) - CONFIG_ENV_SIZE) /* Environment starts at this adress */ |
b6e4c403 WD |
167 | #endif |
168 | ||
169 | ||
170 | #define CONFIG_SPI 1 | |
6d0f6bcf JCPV |
171 | #define CONFIG_SYS_SPI_CS_USED 0x09 /* CS0 and CS3 are used */ |
172 | #define CONFIG_SYS_SPI_CS_BASE 0x08 /* CS3 is active low */ | |
173 | #define CONFIG_SYS_SPI_CS_ACT 0x00 /* CS3 is active low */ | |
b6e4c403 WD |
174 | /*----------------------------------------------------------------------- |
175 | * SYPCR - System Protection Control | |
176 | * SYPCR can only be written once after reset! | |
177 | *----------------------------------------------------------------------- | |
178 | * SW Watchdog freeze | |
179 | */ | |
180 | #undef CONFIG_WATCHDOG | |
181 | #if defined(CONFIG_WATCHDOG) | |
6d0f6bcf | 182 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
b6e4c403 WD |
183 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
184 | #else | |
6d0f6bcf | 185 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
b6e4c403 WD |
186 | SYPCR_SWP) |
187 | #endif /* CONFIG_WATCHDOG */ | |
188 | ||
b6e4c403 WD |
189 | /*----------------------------------------------------------------------- |
190 | * TBSCR - Time Base Status and Control | |
191 | *----------------------------------------------------------------------- | |
192 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
193 | */ | |
6d0f6bcf | 194 | #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
b6e4c403 WD |
195 | |
196 | /*----------------------------------------------------------------------- | |
197 | * PISCR - Periodic Interrupt Status and Control | |
198 | *----------------------------------------------------------------------- | |
199 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
200 | */ | |
6d0f6bcf | 201 | #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
b6e4c403 WD |
202 | |
203 | /*----------------------------------------------------------------------- | |
204 | * SCCR - System Clock and reset Control Register | |
205 | *----------------------------------------------------------------------- | |
206 | * Set clock output, timebase and RTC source and divider, | |
207 | * power management and some other internal clocks | |
208 | */ | |
209 | #define SCCR_MASK SCCR_EBDF00 | |
6d0f6bcf | 210 | #define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_RTDIV | SCCR_RTSEL | \ |
b6e4c403 WD |
211 | SCCR_COM01 | SCCR_DFNL000 | SCCR_DFNH000) |
212 | ||
213 | /*----------------------------------------------------------------------- | |
214 | * SIUMCR - SIU Module Configuration | |
215 | *----------------------------------------------------------------------- | |
216 | * Data show cycle | |
217 | */ | |
6d0f6bcf | 218 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_EARB | SIUMCR_GPC01 | SIUMCR_MLRC11) /* Disable data show cycle */ |
b6e4c403 WD |
219 | |
220 | /*----------------------------------------------------------------------- | |
221 | * PLPRCR - PLL, Low-Power, and Reset Control Register | |
222 | *----------------------------------------------------------------------- | |
223 | * Set all bits to 40 Mhz | |
224 | * | |
225 | */ | |
6d0f6bcf | 226 | #define CONFIG_SYS_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */ |
b6e4c403 WD |
227 | |
228 | ||
6d0f6bcf | 229 | #define CONFIG_SYS_PLPRCR (PLPRCR_MF_9 | PLPRCR_DIVF_0) |
b6e4c403 WD |
230 | |
231 | /*----------------------------------------------------------------------- | |
232 | * UMCR - UIMB Module Configuration Register | |
233 | *----------------------------------------------------------------------- | |
234 | * | |
235 | */ | |
6d0f6bcf | 236 | #define CONFIG_SYS_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */ |
b6e4c403 WD |
237 | |
238 | /*----------------------------------------------------------------------- | |
239 | * ICTRL - I-Bus Support Control Register | |
240 | */ | |
6d0f6bcf | 241 | #define CONFIG_SYS_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */ |
b6e4c403 WD |
242 | |
243 | /*----------------------------------------------------------------------- | |
244 | * USIU - Memory Controller Register | |
245 | *----------------------------------------------------------------------- | |
246 | */ | |
6d0f6bcf JCPV |
247 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_V | BR_BI | BR_PS_16 | BR_SETA) |
248 | #define CONFIG_SYS_OR0_PRELIM (0xffc00000) /* SCY is not used if external TA is set */ | |
b6e4c403 | 249 | /* SDRAM */ |
6d0f6bcf JCPV |
250 | #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_SDRAM_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA) |
251 | #define CONFIG_SYS_OR1_PRELIM (OR_ADDR_MK_FF) /* SCY is not used if external TA is set */ | |
b6e4c403 | 252 | /* PCI */ |
6d0f6bcf JCPV |
253 | #define CONFIG_SYS_BR2_PRELIM (PCI_BASE | BR_V | BR_PS_32 | BR_SETA) |
254 | #define CONFIG_SYS_OR2_PRELIM (OR_ADDR_MK_FF) | |
b6e4c403 | 255 | /* config registers: */ |
6d0f6bcf JCPV |
256 | #define CONFIG_SYS_BR3_PRELIM (PCI_CONFIG_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA) |
257 | #define CONFIG_SYS_OR3_PRELIM (0xffff0000) | |
b6e4c403 | 258 | |
6d0f6bcf | 259 | #define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* We don't realign the flash */ |
b6e4c403 WD |
260 | |
261 | /*----------------------------------------------------------------------- | |
262 | * DER - Timer Decrementer | |
263 | *----------------------------------------------------------------------- | |
264 | * Initialise to zero | |
265 | */ | |
6d0f6bcf | 266 | #define CONFIG_SYS_DER 0x00000000 |
b6e4c403 | 267 | |
b6e4c403 WD |
268 | #define VERSION_TAG "released" |
269 | #define CONFIG_ISO_STRING "MEV-10084-001" | |
270 | ||
271 | #define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG | |
272 | ||
273 | #endif /* __CONFIG_H */ |