[people/ms/u-boot.git] / include / configs / PATI.h

/*
 * (C) Copyright 2003
 * Denis Peter d.peter@mpl.ch
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation,
 */

/*
 * File:		PATI.h
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */

#define CONFIG_MPC555		1		/* This is an MPC555 CPU		*/
#define CONFIG_PATI		1		/* ...On a PATI board	*/

#define	CONFIG_SYS_TEXT_BASE	0xFFF00000

/* Serial Console Configuration */
#define	CONFIG_5xx_CONS_SCI1
#undef	CONFIG_5xx_CONS_SCI2

#define CONFIG_BAUDRATE		9600


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_LOADS
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_BDI
#define CONFIG_CMD_CONSOLE
#define CONFIG_CMD_RUN
#define CONFIG_CMD_BSP
#define CONFIG_CMD_IMI
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MISC


#if 0
#define CONFIG_BOOTDELAY	-1		/* autoboot disabled			*/
#else
#define CONFIG_BOOTDELAY	5		/* autoboot after 5 seconds		*/
#endif
#define CONFIG_BOOTCOMMAND	""	/* autoboot command			*/

#define CONFIG_BOOTARGS		""		/* */

#define CONFIG_WATCHDOG				/* turn on platform specific watchdog	*/

/*#define CONFIG_STATUS_LED	1		*/ /* Enable status led */

#define CONFIG_LOADS_ECHO	1		/* Echo on for serial download */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_CONSOLE_IS_IN_ENV	/* stdin, stdout and stderr are in evironment */
#define CONFIG_PREBOOT

#define	CONFIG_SYS_LONGHELP				/* undef to save memory		*/
#define	CONFIG_SYS_PROMPT		"pati=> "		/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define	CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size	*/
#else
#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
#endif
#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define	CONFIG_SYS_MAXARGS		16	       /* max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x00010000	/* memtest works on		*/
#define CONFIG_SYS_MEMTEST_END		0x00A00000	/* 10 MB in SRAM			*/

#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address		*/

#define	CONFIG_SYS_HZ			1000		/* Decrementer freq: 1 ms ticks	*/

#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 1250000 }


/***********************************************************************
 * Last Stage Init
 ***********************************************************************/
#define CONFIG_LAST_STAGE_INIT

/*
 * Low Level Configuration Settings
 */

/*
 * Internal Memory Mapped (This is not the IMMR content)
 */
#define CONFIG_SYS_IMMR		0x01C00000		/* Physical start adress of internal memory map */

/*
 * Definitions for initial stack pointer and data area
 */
#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_IMMR + 0x003f9800)	/* Physical start adress of internal MPC555 writable RAM */
#define	CONFIG_SYS_INIT_RAM_SIZE	(CONFIG_SYS_IMMR + 0x003fffff)	/* Physical end adress of internal MPC555 used RAM area	*/
#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_RAM_ADDR) - GENERATED_GBL_DATA_SIZE) /* Offset from the beginning of ram */
#define	CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_IMMR + 0x03fa000)	/* Physical start adress of inital stack */
/*
 * Start addresses for the final memory configuration
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define	CONFIG_SYS_SDRAM_BASE		0x00000000	/* Monitor won't change memory map			*/
#define CONFIG_SYS_FLASH_BASE		0xffC00000	/* External flash */
#define PCI_BASE		0x03000000	/* PCI Base (CS2) */
#define PCI_CONFIG_BASE		0x04000000	/* PCI & PLD  (CS3) */
#define PLD_CONFIG_BASE		0x04001000	/* PLD  (CS3) */

#define	CONFIG_SYS_MONITOR_BASE	0xFFF00000
/* CONFIG_SYS_FLASH_BASE	*/ /* CONFIG_SYS_TEXT_BASE is defined in the board config.mk file.	*/
						/* This adress is given to the linker with -Ttext to	*/
						/* locate the text section at this adress.		*/
#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 192 kB for Monitor				*/
#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()				*/

#define CONFIG_SYS_RESET_ADDRESS	(PLD_CONFIG_BASE + 0x10)	 /* Adress which causes reset */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux		*/


/*-----------------------------------------------------------------------
 * FLASH organization
 *-----------------------------------------------------------------------
 *
 */

#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_FLASH_EMPTY_INFO

#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER

#define CONFIG_FLASH_SHOW_PROGRESS	45

#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define CONFIG_SYS_MAX_FLASH_SECT	128

#define	CONFIG_ENV_IS_IN_EEPROM
#ifdef	CONFIG_ENV_IS_IN_EEPROM
#define CONFIG_ENV_OFFSET		0
#define CONFIG_ENV_SIZE		2048
#endif

#undef  CONFIG_ENV_IS_IN_FLASH
#ifdef	CONFIG_ENV_IS_IN_FLASH
#define	CONFIG_ENV_SIZE		0x00002000		/* Set whole sector as env		*/
#define CONFIG_ENV_OFFSET		((0 - CONFIG_SYS_FLASH_BASE) - CONFIG_ENV_SIZE)		/* Environment starts at this adress	*/
#endif


#define CONFIG_SPI		1
#define CONFIG_SYS_SPI_CS_USED	0x09 /* CS0 and CS3 are used */
#define CONFIG_SYS_SPI_CS_BASE	0x08 /* CS3 is active low */
#define CONFIG_SYS_SPI_CS_ACT	0x00 /* CS3 is active low */
/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * SW Watchdog freeze
 */
#undef CONFIG_WATCHDOG
#if defined(CONFIG_WATCHDOG)
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
#else
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWP)
#endif	/* CONFIG_WATCHDOG */

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF00
#define CONFIG_SYS_SCCR	(SCCR_TBS     | SCCR_RTDIV    | SCCR_RTSEL    | \
			 SCCR_COM01   | SCCR_DFNL000 | SCCR_DFNH000)

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration
 *-----------------------------------------------------------------------
 * Data show cycle
 */
#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_EARB | SIUMCR_GPC01 | SIUMCR_MLRC11) /* Disable data show cycle	*/

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register
 *-----------------------------------------------------------------------
 * Set all bits to 40 Mhz
 *
 */
#define CONFIG_SYS_OSC_CLK	((uint)4000000)		/* Oscillator clock is 4MHz	*/


#define CONFIG_SYS_PLPRCR	(PLPRCR_MF_9 | PLPRCR_DIVF_0)

/*-----------------------------------------------------------------------
 * UMCR - UIMB Module Configuration Register
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_SYS_UMCR	(UMCR_FSPEED)		/* IMB clock same as U-bus	*/

/*-----------------------------------------------------------------------
 * ICTRL - I-Bus Support Control Register
 */
#define CONFIG_SYS_ICTRL	(ICTRL_ISCT_SER_7)	/* Take out of serialized mode	*/

/*-----------------------------------------------------------------------
 * USIU - Memory Controller Register
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | BR_V | BR_BI | BR_PS_16 | BR_SETA)
#define CONFIG_SYS_OR0_PRELIM		(0xffc00000) /* SCY is not used if external TA is set */
/* SDRAM */
#define CONFIG_SYS_BR1_PRELIM		(CONFIG_SYS_SDRAM_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA)
#define CONFIG_SYS_OR1_PRELIM		(OR_ADDR_MK_FF) /* SCY is not used if external TA is set */
/* PCI */
#define CONFIG_SYS_BR2_PRELIM		(PCI_BASE | BR_V | BR_PS_32 | BR_SETA)
#define CONFIG_SYS_OR2_PRELIM		(OR_ADDR_MK_FF)
/* config registers: */
#define CONFIG_SYS_BR3_PRELIM		(PCI_CONFIG_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA)
#define CONFIG_SYS_OR3_PRELIM		(0xffff0000)

#define FLASH_BASE0_PRELIM	CONFIG_SYS_FLASH_BASE	/* We don't realign the flash	*/

/*-----------------------------------------------------------------------
 * DER - Timer Decrementer
 *-----------------------------------------------------------------------
 * Initialise to zero
 */
#define CONFIG_SYS_DER			0x00000000

#define VERSION_TAG "released"
#define CONFIG_ISO_STRING "MEV-10084-001"

#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG

#endif	/* __CONFIG_H */
Commit	Line	Data
b6e4c403 WD	1	/*
	2	* (C) Copyright 2003
	3	* Denis Peter d.peter@mpl.ch
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation,
	21	*/
	22
	23	/*
	24	* File: PATI.h
	25	*/
	26
	27	#ifndef __CONFIG_H
	28	#define __CONFIG_H
	29
	30	/*
	31	* High Level Configuration Options
	32	*/
	33
	34	#define CONFIG_MPC555 1 /* This is an MPC555 CPU */
53677ef1	35	#define CONFIG_PATI 1 /* ...On a PATI board */
2ae18241 WD	36
	37	#define CONFIG_SYS_TEXT_BASE 0xFFF00000
	38
b6e4c403 WD	39	/* Serial Console Configuration */
	40	#define CONFIG_5xx_CONS_SCI1
	41	#undef CONFIG_5xx_CONS_SCI2
	42
	43	#define CONFIG_BAUDRATE 9600
	44
b6e4c403	45
a1aa0bb5 JL	46	/*
	47	* BOOTP options
	48	*/
	49	#define CONFIG_BOOTP_BOOTFILESIZE
	50	#define CONFIG_BOOTP_BOOTPATH
	51	#define CONFIG_BOOTP_GATEWAY
	52	#define CONFIG_BOOTP_HOSTNAME
	53
	54
acf02697 JL	55	/*
	56	* Command line configuration.
	57	*/
	58	#define CONFIG_CMD_MEMORY
	59	#define CONFIG_CMD_LOADB
	60	#define CONFIG_CMD_REGINFO
	61	#define CONFIG_CMD_FLASH
	62	#define CONFIG_CMD_LOADS
bdab39d3	63	#define CONFIG_CMD_SAVEENV
acf02697 JL	64	#define CONFIG_CMD_REGINFO
	65	#define CONFIG_CMD_BDI
	66	#define CONFIG_CMD_CONSOLE
	67	#define CONFIG_CMD_RUN
	68	#define CONFIG_CMD_BSP
	69	#define CONFIG_CMD_IMI
	70	#define CONFIG_CMD_EEPROM
	71	#define CONFIG_CMD_IRQ
	72	#define CONFIG_CMD_MISC
	73
b6e4c403 WD	74
	75	#if 0
	76	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
	77	#else
	78	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	79	#endif
53677ef1	80	#define CONFIG_BOOTCOMMAND "" /* autoboot command */
b6e4c403 WD	81
	82	#define CONFIG_BOOTARGS "" /* */
	83
53677ef1	84	#define CONFIG_WATCHDOG /* turn on platform specific watchdog */
b6e4c403	85
3a473b2a	86	/#define CONFIG_STATUS_LED 1 / /* Enable status led */
b6e4c403 WD	87
	88	#define CONFIG_LOADS_ECHO 1 /* Echo on for serial download */
	89
	90	/*
	91	* Miscellaneous configurable options
	92	*/
6d0f6bcf	93	#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */
b6e4c403 WD	94	#define CONFIG_PREBOOT
b6e4c403 WD	95
6d0f6bcf JCPV	96	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	97	#define CONFIG_SYS_PROMPT "pati=> " /* Monitor Command Prompt */
acf02697	98	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	99	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
b6e4c403	100	#else
6d0f6bcf	101	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
b6e4c403	102	#endif
6d0f6bcf JCPV	103	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	104	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	105	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
b6e4c403	106
6d0f6bcf JCPV	107	#define CONFIG_SYS_MEMTEST_START 0x00010000 /* memtest works on */
6d0f6bcf JCPV	108	#define CONFIG_SYS_MEMTEST_END 0x00A00000 /* 10 MB in SRAM */
b6e4c403	109
6d0f6bcf	110	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
b6e4c403	111
6d0f6bcf	112	#define CONFIG_SYS_HZ 1000 /* Decrementer freq: 1 ms ticks */
b6e4c403	113
6d0f6bcf	114	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 1250000 }
b6e4c403 WD	115
	116
	117	/***********************************************************************
	118	* Last Stage Init
	119	***********************************************************************/
	120	#define CONFIG_LAST_STAGE_INIT
	121
	122	/*
	123	* Low Level Configuration Settings
	124	*/
	125
	126	/*
	127	* Internal Memory Mapped (This is not the IMMR content)
	128	*/
6d0f6bcf	129	#define CONFIG_SYS_IMMR 0x01C00000 /* Physical start adress of internal memory map */
b6e4c403 WD	130
	131	/*
	132	* Definitions for initial stack pointer and data area
	133	*/
6d0f6bcf	134	#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */
553f0982	135	#define CONFIG_SYS_INIT_RAM_SIZE (CONFIG_SYS_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */
25ddd1fb	136	#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_RAM_ADDR) - GENERATED_GBL_DATA_SIZE) /* Offset from the beginning of ram */
6d0f6bcf	137	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_IMMR + 0x03fa000) /* Physical start adress of inital stack */
b6e4c403 WD	138	/*
b6e4c403 WD	139	* Start addresses for the final memory configuration
6d0f6bcf	140	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
b6e4c403	141	*/
6d0f6bcf JCPV	142	#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */
6d0f6bcf JCPV	143	#define CONFIG_SYS_FLASH_BASE 0xffC00000 /* External flash */
b6e4c403 WD	144	#define PCI_BASE 0x03000000 /* PCI Base (CS2) */
	145	#define PCI_CONFIG_BASE 0x04000000 /* PCI & PLD (CS3) */
	146	#define PLD_CONFIG_BASE 0x04001000 /* PLD (CS3) */
	147
6d0f6bcf	148	#define CONFIG_SYS_MONITOR_BASE 0xFFF00000
14d0a02a	149	/* CONFIG_SYS_FLASH_BASE / / CONFIG_SYS_TEXT_BASE is defined in the board config.mk file. */
53677ef1 WD	150	/* This adress is given to the linker with -Ttext to */
53677ef1 WD	151	/* locate the text section at this adress. */
6d0f6bcf JCPV	152	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 192 kB for Monitor */
6d0f6bcf JCPV	153	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
b6e4c403	154
6d0f6bcf	155	#define CONFIG_SYS_RESET_ADDRESS (PLD_CONFIG_BASE + 0x10) /* Adress which causes reset */
b6e4c403 WD	156
	157	/*
	158	* For booting Linux, the board info and command line data
	159	* have to be in the first 8 MB of memory, since this is
	160	* the maximum mapped by the Linux kernel during initialization.
	161	*/
6d0f6bcf	162	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
b6e4c403 WD	163
	164
	165	/*-----------------------------------------------------------------------
	166	* FLASH organization
	167	*-----------------------------------------------------------------------
	168	*
	169	*/
	170
d49f5b1c DM	171	#define CONFIG_SYS_FLASH_PROTECTION
d49f5b1c DM	172	#define CONFIG_SYS_FLASH_EMPTY_INFO
b6e4c403	173
d49f5b1c DM	174	#define CONFIG_SYS_FLASH_CFI
	175	#define CONFIG_FLASH_CFI_DRIVER
	176
	177	#define CONFIG_FLASH_SHOW_PROGRESS 45
	178
	179	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	180	#define CONFIG_SYS_MAX_FLASH_SECT 128
b6e4c403	181
bb1f8b4f JCPV	182	#define CONFIG_ENV_IS_IN_EEPROM
bb1f8b4f JCPV	183	#ifdef CONFIG_ENV_IS_IN_EEPROM
0e8d1586 JCPV	184	#define CONFIG_ENV_OFFSET 0
0e8d1586 JCPV	185	#define CONFIG_ENV_SIZE 2048
b6e4c403 WD	186	#endif
b6e4c403 WD	187
5a1aceb0 JCPV	188	#undef CONFIG_ENV_IS_IN_FLASH
5a1aceb0 JCPV	189	#ifdef CONFIG_ENV_IS_IN_FLASH
0e8d1586	190	#define CONFIG_ENV_SIZE 0x00002000 /* Set whole sector as env */
6d0f6bcf	191	#define CONFIG_ENV_OFFSET ((0 - CONFIG_SYS_FLASH_BASE) - CONFIG_ENV_SIZE) /* Environment starts at this adress */
b6e4c403 WD	192	#endif
	193
	194
	195	#define CONFIG_SPI 1
6d0f6bcf JCPV	196	#define CONFIG_SYS_SPI_CS_USED 0x09 /* CS0 and CS3 are used */
	197	#define CONFIG_SYS_SPI_CS_BASE 0x08 /* CS3 is active low */
	198	#define CONFIG_SYS_SPI_CS_ACT 0x00 /* CS3 is active low */
b6e4c403 WD	199	/*-----------------------------------------------------------------------
	200	* SYPCR - System Protection Control
	201	* SYPCR can only be written once after reset!
	202	*-----------------------------------------------------------------------
	203	* SW Watchdog freeze
	204	*/
	205	#undef CONFIG_WATCHDOG
	206	#if defined(CONFIG_WATCHDOG)
6d0f6bcf	207	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
b6e4c403 WD	208	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
b6e4c403 WD	209	#else
6d0f6bcf	210	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
b6e4c403 WD	211	SYPCR_SWP)
	212	#endif /* CONFIG_WATCHDOG */
	213
b6e4c403 WD	214	/*-----------------------------------------------------------------------
	215	* TBSCR - Time Base Status and Control
	216	*-----------------------------------------------------------------------
	217	* Clear Reference Interrupt Status, Timebase freezing enabled
	218	*/
6d0f6bcf	219	#define CONFIG_SYS_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF)
b6e4c403 WD	220
	221	/*-----------------------------------------------------------------------
	222	* PISCR - Periodic Interrupt Status and Control
	223	*-----------------------------------------------------------------------
	224	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	225	*/
6d0f6bcf	226	#define CONFIG_SYS_PISCR (PISCR_PS \| PISCR_PITF)
b6e4c403 WD	227
	228	/*-----------------------------------------------------------------------
	229	* SCCR - System Clock and reset Control Register
	230	*-----------------------------------------------------------------------
	231	* Set clock output, timebase and RTC source and divider,
	232	* power management and some other internal clocks
	233	*/
	234	#define SCCR_MASK SCCR_EBDF00
6d0f6bcf	235	#define CONFIG_SYS_SCCR (SCCR_TBS \| SCCR_RTDIV \| SCCR_RTSEL \| \
b6e4c403 WD	236	SCCR_COM01 \| SCCR_DFNL000 \| SCCR_DFNH000)
	237
	238	/*-----------------------------------------------------------------------
	239	* SIUMCR - SIU Module Configuration
	240	*-----------------------------------------------------------------------
	241	* Data show cycle
	242	*/
6d0f6bcf	243	#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 \| SIUMCR_EARB \| SIUMCR_GPC01 \| SIUMCR_MLRC11) /* Disable data show cycle */
b6e4c403 WD	244
	245	/*-----------------------------------------------------------------------
	246	* PLPRCR - PLL, Low-Power, and Reset Control Register
	247	*-----------------------------------------------------------------------
	248	* Set all bits to 40 Mhz
	249	*
	250	*/
6d0f6bcf	251	#define CONFIG_SYS_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */
b6e4c403 WD	252
b6e4c403 WD	253
6d0f6bcf	254	#define CONFIG_SYS_PLPRCR (PLPRCR_MF_9 \| PLPRCR_DIVF_0)
b6e4c403 WD	255
	256	/*-----------------------------------------------------------------------
	257	* UMCR - UIMB Module Configuration Register
	258	*-----------------------------------------------------------------------
	259	*
	260	*/
6d0f6bcf	261	#define CONFIG_SYS_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */
b6e4c403 WD	262
	263	/*-----------------------------------------------------------------------
	264	* ICTRL - I-Bus Support Control Register
	265	*/
6d0f6bcf	266	#define CONFIG_SYS_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */
b6e4c403 WD	267
	268	/*-----------------------------------------------------------------------
	269	* USIU - Memory Controller Register
	270	*-----------------------------------------------------------------------
	271	*/
6d0f6bcf JCPV	272	#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \| BR_V \| BR_BI \| BR_PS_16 \| BR_SETA)
6d0f6bcf JCPV	273	#define CONFIG_SYS_OR0_PRELIM (0xffc00000) /* SCY is not used if external TA is set */
b6e4c403	274	/* SDRAM */
6d0f6bcf JCPV	275	#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_SDRAM_BASE \| BR_V \| BR_BI \| BR_PS_32 \| BR_SETA)
6d0f6bcf JCPV	276	#define CONFIG_SYS_OR1_PRELIM (OR_ADDR_MK_FF) /* SCY is not used if external TA is set */
b6e4c403	277	/* PCI */
6d0f6bcf JCPV	278	#define CONFIG_SYS_BR2_PRELIM (PCI_BASE \| BR_V \| BR_PS_32 \| BR_SETA)
6d0f6bcf JCPV	279	#define CONFIG_SYS_OR2_PRELIM (OR_ADDR_MK_FF)
b6e4c403	280	/* config registers: */
6d0f6bcf JCPV	281	#define CONFIG_SYS_BR3_PRELIM (PCI_CONFIG_BASE \| BR_V \| BR_BI \| BR_PS_32 \| BR_SETA)
6d0f6bcf JCPV	282	#define CONFIG_SYS_OR3_PRELIM (0xffff0000)
b6e4c403	283
6d0f6bcf	284	#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* We don't realign the flash */
b6e4c403 WD	285
	286	/*-----------------------------------------------------------------------
	287	* DER - Timer Decrementer
	288	*-----------------------------------------------------------------------
	289	* Initialise to zero
	290	*/
6d0f6bcf	291	#define CONFIG_SYS_DER 0x00000000
b6e4c403	292
b6e4c403 WD	293	#define VERSION_TAG "released"
	294	#define CONFIG_ISO_STRING "MEV-10084-001"
	295
	296	#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
	297
	298	#endif /* __CONFIG_H */