]>
Commit | Line | Data |
---|---|---|
8ba132ca | 1 | /* |
76b565b6 | 2 | * (C) Copyright 2007-2008 |
8ba132ca MF |
3 | * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com. |
4 | * Based on the sequoia configuration file. | |
5 | * | |
6 | * (C) Copyright 2006-2007 | |
7 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
8 | * | |
9 | * (C) Copyright 2006 | |
10 | * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com | |
11 | * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or | |
14 | * modify it under the terms of the GNU General Public License as | |
15 | * published by the Free Software Foundation; either version 2 of | |
16 | * the License, or (at your option) any later version. | |
17 | * | |
18 | * This program is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
22 | * | |
23 | * You should have received a copy of the GNU General Public License | |
24 | * along with this program; if not, write to the Free Software | |
25 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
26 | * MA 02111-1307 USA | |
27 | */ | |
28 | ||
29 | /************************************************************************ | |
30 | * PMC440.h - configuration for esd PMC440 boards | |
31 | ***********************************************************************/ | |
32 | #ifndef __CONFIG_H | |
33 | #define __CONFIG_H | |
34 | ||
35 | /*----------------------------------------------------------------------- | |
36 | * High Level Configuration Options | |
37 | *----------------------------------------------------------------------*/ | |
38 | #define CONFIG_440EPX 1 /* Specific PPC440EPx */ | |
39 | #define CONFIG_440 1 /* ... PPC440 family */ | |
40 | #define CONFIG_4xx 1 /* ... PPC4xx family */ | |
41 | ||
2ae18241 WD |
42 | #ifndef CONFIG_SYS_TEXT_BASE |
43 | #define CONFIG_SYS_TEXT_BASE 0xFFF90000 | |
44 | #endif | |
45 | ||
8ba132ca MF |
46 | #define CONFIG_SYS_CLK_FREQ 33333400 |
47 | ||
ff41ffc9 | 48 | #if 0 /* temporary disabled because OS/9 does not like dcache on startup */ |
8ba132ca | 49 | #define CONFIG_4xx_DCACHE /* enable dcache */ |
ff41ffc9 | 50 | #endif |
8ba132ca MF |
51 | |
52 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ | |
76b565b6 | 53 | #define CONFIG_MISC_INIT_F 1 |
8ba132ca MF |
54 | #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ |
55 | #define CONFIG_BOARD_TYPES 1 /* support board types */ | |
56 | /*----------------------------------------------------------------------- | |
57 | * Base addresses -- Note these are effective addresses where the | |
58 | * actual resources get mapped (not physical addresses) | |
59 | *----------------------------------------------------------------------*/ | |
14d0a02a | 60 | #define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1) |
6d0f6bcf | 61 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserve 256 kB for malloc() */ |
8ba132ca MF |
62 | |
63 | #define CONFIG_PRAM 0 /* use pram variable to overwrite */ | |
64 | ||
6d0f6bcf JCPV |
65 | #define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000 |
66 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ | |
67 | #define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */ | |
14d0a02a | 68 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf JCPV |
69 | #define CONFIG_SYS_NAND_ADDR 0xd0000000 /* NAND Flash */ |
70 | #define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */ | |
71 | #define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_OCM_BASE | |
72 | #define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */ | |
73 | #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ | |
74 | #define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000 | |
75 | #define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000 | |
76 | #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000 | |
77 | #define CONFIG_SYS_PCI_MEMSIZE 0x80000000 /* 2GB! */ | |
8ba132ca | 78 | |
6d0f6bcf JCPV |
79 | #define CONFIG_SYS_USB2D0_BASE 0xe0000100 |
80 | #define CONFIG_SYS_USB_DEVICE 0xe0000000 | |
81 | #define CONFIG_SYS_USB_HOST 0xe0000400 | |
82 | #define CONFIG_SYS_FPGA_BASE0 0xef000000 /* 32 bit */ | |
83 | #define CONFIG_SYS_FPGA_BASE1 0xef100000 /* 16 bit */ | |
76b565b6 | 84 | #define CONFIG_SYS_RESET_BASE 0xef200000 |
8ba132ca MF |
85 | |
86 | /*----------------------------------------------------------------------- | |
87 | * Initial RAM & stack pointer | |
88 | *----------------------------------------------------------------------*/ | |
89 | /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */ | |
6d0f6bcf | 90 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */ |
553f0982 | 91 | #define CONFIG_SYS_INIT_RAM_SIZE (4 << 10) |
25ddd1fb | 92 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
800eb096 | 93 | #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) |
8ba132ca MF |
94 | |
95 | /*----------------------------------------------------------------------- | |
96 | * Serial Port | |
97 | *----------------------------------------------------------------------*/ | |
550650dd SR |
98 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
99 | #define CONFIG_SYS_NS16550 | |
100 | #define CONFIG_SYS_NS16550_SERIAL | |
101 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
102 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() | |
6d0f6bcf | 103 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK |
8ba132ca | 104 | #define CONFIG_BAUDRATE 115200 |
8ba132ca | 105 | |
6d0f6bcf | 106 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
8ba132ca MF |
107 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} |
108 | ||
109 | /*----------------------------------------------------------------------- | |
110 | * Environment | |
111 | *----------------------------------------------------------------------*/ | |
112 | #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) | |
bb1f8b4f | 113 | #define CONFIG_ENV_IS_IN_EEPROM 1 /* use FLASH for environment vars */ |
8ba132ca | 114 | #else |
51bfee19 | 115 | #define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ |
0e8d1586 | 116 | #define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */ |
8ba132ca MF |
117 | #endif |
118 | ||
119 | /*----------------------------------------------------------------------- | |
120 | * RTC | |
121 | *----------------------------------------------------------------------*/ | |
122 | #define CONFIG_RTC_RX8025 | |
123 | ||
124 | /*----------------------------------------------------------------------- | |
125 | * FLASH related | |
126 | *----------------------------------------------------------------------*/ | |
6d0f6bcf | 127 | #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ |
00b1883a | 128 | #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ |
8ba132ca | 129 | |
6d0f6bcf | 130 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } |
8ba132ca | 131 | |
6d0f6bcf JCPV |
132 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
133 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ | |
8ba132ca | 134 | |
6d0f6bcf JCPV |
135 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
136 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
8ba132ca | 137 | |
6d0f6bcf JCPV |
138 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ |
139 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */ | |
8ba132ca | 140 | |
6d0f6bcf JCPV |
141 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
142 | #define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ | |
8ba132ca | 143 | |
5a1aceb0 | 144 | #ifdef CONFIG_ENV_IS_IN_FLASH |
0e8d1586 | 145 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ |
6d0f6bcf | 146 | #define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE) |
76b565b6 | 147 | #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ |
8ba132ca MF |
148 | |
149 | /* Address and size of Redundant Environment Sector */ | |
0e8d1586 JCPV |
150 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) |
151 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
8ba132ca MF |
152 | #endif |
153 | ||
bb1f8b4f | 154 | #ifdef CONFIG_ENV_IS_IN_EEPROM |
0e8d1586 JCPV |
155 | #define CONFIG_ENV_OFFSET 0 /* environment starts at the beginning of the EEPROM */ |
156 | #define CONFIG_ENV_SIZE 0x1000 /* 4096 bytes may be used for env vars */ | |
8ba132ca MF |
157 | #endif |
158 | ||
159 | /* | |
160 | * IPL (Initial Program Loader, integrated inside CPU) | |
161 | * Will load first 4k from NAND (SPL) into cache and execute it from there. | |
162 | * | |
163 | * SPL (Secondary Program Loader) | |
164 | * Will load special U-Boot version (NUB) from NAND and execute it. This SPL | |
165 | * has to fit into 4kByte. It sets up the CPU and configures the SDRAM | |
166 | * controller and the NAND controller so that the special U-Boot image can be | |
167 | * loaded from NAND to SDRAM. | |
168 | * | |
169 | * NUB (NAND U-Boot) | |
170 | * This NAND U-Boot (NUB) is a special U-Boot version which can be started | |
171 | * from RAM. Therefore it mustn't (re-)configure the SDRAM controller. | |
172 | * | |
173 | * On 440EPx the SPL is copied to SDRAM before the NAND controller is | |
174 | * set up. While still running from cache, I experienced problems accessing | |
175 | * the NAND controller. sr - 2006-08-25 | |
176 | */ | |
7d5d7563 | 177 | #if defined (CONFIG_NAND_U_BOOT) |
6d0f6bcf JCPV |
178 | #define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */ |
179 | #define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */ | |
180 | #define CONFIG_SYS_NAND_BOOT_SPL_DST (CONFIG_SYS_OCM_BASE + (12 << 10)) /* Copy SPL here */ | |
181 | #define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */ | |
182 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr */ | |
183 | #define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST) | |
8ba132ca MF |
184 | |
185 | /* | |
186 | * Define the partitioning of the NAND chip (only RAM U-Boot is needed here) | |
187 | */ | |
6d0f6bcf JCPV |
188 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */ |
189 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */ | |
8ba132ca MF |
190 | |
191 | /* | |
192 | * Now the NAND chip has to be defined (no autodetection used!) | |
193 | */ | |
6d0f6bcf JCPV |
194 | #define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */ |
195 | #define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */ | |
196 | #define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */ | |
197 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */ | |
198 | #undef CONFIG_SYS_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */ | |
199 | ||
200 | #define CONFIG_SYS_NAND_ECCSIZE 256 | |
201 | #define CONFIG_SYS_NAND_ECCBYTES 3 | |
6d0f6bcf | 202 | #define CONFIG_SYS_NAND_OOBSIZE 16 |
6d0f6bcf | 203 | #define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7} |
7d5d7563 | 204 | #endif |
8ba132ca | 205 | |
51bfee19 | 206 | #ifdef CONFIG_ENV_IS_IN_NAND |
8ba132ca MF |
207 | /* |
208 | * For NAND booting the environment is embedded in the U-Boot image. Please take | |
209 | * look at the file board/amcc/sequoia/u-boot-nand.lds for details. | |
210 | */ | |
6d0f6bcf JCPV |
211 | #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE |
212 | #define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE) | |
0e8d1586 | 213 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) |
8ba132ca MF |
214 | #endif |
215 | ||
216 | /*----------------------------------------------------------------------- | |
217 | * DDR SDRAM | |
218 | *----------------------------------------------------------------------*/ | |
8ba132ca MF |
219 | #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) |
220 | #define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */ | |
221 | #endif | |
3aed3aa2 JCPV |
222 | #define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */ |
223 | /* 440EPx errata CHIP 11 */ | |
8ba132ca MF |
224 | |
225 | /*----------------------------------------------------------------------- | |
226 | * I2C | |
227 | *----------------------------------------------------------------------*/ | |
228 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
d0b0dcaa | 229 | #define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ |
76b565b6 | 230 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
6d0f6bcf | 231 | #define CONFIG_SYS_I2C_SLAVE 0x7F |
8ba132ca | 232 | |
8ba132ca MF |
233 | #define CONFIG_I2C_MULTI_BUS 1 |
234 | ||
6d0f6bcf | 235 | #define CONFIG_SYS_I2C_MULTI_EEPROMS |
8ba132ca | 236 | |
6d0f6bcf JCPV |
237 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 |
238 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
239 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 | |
240 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
241 | #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01 | |
8ba132ca | 242 | |
6d0f6bcf JCPV |
243 | #define CONFIG_SYS_EEPROM_WREN 1 |
244 | #define CONFIG_SYS_I2C_BOOT_EEPROM_ADDR 0x52 | |
8ba132ca MF |
245 | |
246 | /* | |
247 | * standard dtt sensor configuration - bottom bit will determine local or | |
248 | * remote sensor of the TMP401 | |
249 | */ | |
250 | #define CONFIG_DTT_SENSORS { 0, 1 } | |
251 | ||
252 | /* | |
253 | * The PMC440 uses a TI TMP401 temperature sensor. This part | |
254 | * is basically compatible to the ADM1021 that is supported | |
255 | * by U-Boot. | |
256 | * | |
257 | * - i2c addr 0x4c | |
258 | * - conversion rate 0x02 = 0.25 conversions/second | |
259 | * - ALERT ouput disabled | |
260 | * - local temp sensor enabled, min set to 0 deg, max set to 70 deg | |
261 | * - remote temp sensor enabled, min set to 0 deg, max set to 70 deg | |
262 | */ | |
263 | #define CONFIG_DTT_ADM1021 | |
6d0f6bcf | 264 | #define CONFIG_SYS_DTT_ADM1021 { { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} } |
8ba132ca | 265 | |
76b565b6 MF |
266 | #define CONFIG_PREBOOT "echo Add \\\"run fpga\\\" and " \ |
267 | "\\\"painit\\\" to preboot command" | |
8ba132ca MF |
268 | |
269 | #undef CONFIG_BOOTARGS | |
270 | ||
271 | /* Setup some board specific values for the default environment variables */ | |
272 | #define CONFIG_HOSTNAME pmc440 | |
76b565b6 MF |
273 | #define CONFIG_SYS_BOOTFILE "bootfile=/tftpboot/pmc440/uImage\0" |
274 | #define CONFIG_SYS_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0" | |
8ba132ca MF |
275 | |
276 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
76b565b6 MF |
277 | CONFIG_SYS_BOOTFILE \ |
278 | CONFIG_SYS_ROOTPATH \ | |
279 | "fdt_file=/tftpboot/pmc440/pmc440.dtb\0" \ | |
8ba132ca | 280 | "netdev=eth0\0" \ |
ff41ffc9 | 281 | "ethrotate=no\0" \ |
8ba132ca MF |
282 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
283 | "nfsroot=${serverip}:${rootpath}\0" \ | |
284 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
285 | "addip=setenv bootargs ${bootargs} " \ | |
76b565b6 MF |
286 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ |
287 | ":${hostname}:${netdev}:off panic=1\0" \ | |
8ba132ca | 288 | "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ |
76b565b6 MF |
289 | "addmisc=setenv bootargs ${bootargs} mem=${mem}\0" \ |
290 | "nandargs=setenv bootargs root=/dev/mtdblock6 rootfstype=jffs2 rw\0" \ | |
76b565b6 MF |
291 | "nand_boot_fdt=run nandargs addip addtty addmisc;" \ |
292 | "bootm ${kernel_addr} - ${fdt_addr}\0" \ | |
76b565b6 MF |
293 | "net_nfs_fdt=tftp ${kernel_addr_r} ${bootfile};" \ |
294 | "tftp ${fdt_addr_r} ${fdt_file};" \ | |
295 | "run nfsargs addip addtty addmisc;" \ | |
296 | "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ | |
297 | "kernel_addr=ffc00000\0" \ | |
298 | "kernel_addr_r=200000\0" \ | |
299 | "fpga_addr=fff00000\0" \ | |
300 | "fdt_addr=fff80000\0" \ | |
301 | "fdt_addr_r=800000\0" \ | |
302 | "fpga=fpga loadb 0 ${fpga_addr}\0" \ | |
8ba132ca | 303 | "load=tftp 200000 /tftpboot/pmc440/u-boot.bin\0" \ |
5baefbba MF |
304 | "update=protect off fff90000 ffffffff;era fff90000 ffffffff;" \ |
305 | "cp.b 200000 fff90000 70000\0" \ | |
8ba132ca MF |
306 | "" |
307 | ||
308 | #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ | |
309 | ||
310 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 311 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
8ba132ca | 312 | |
96e21f86 | 313 | #define CONFIG_PPC4xx_EMAC |
8ba132ca MF |
314 | #define CONFIG_IBM_EMAC4_V4 1 |
315 | #define CONFIG_MII 1 /* MII PHY management */ | |
316 | #define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */ | |
317 | ||
318 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
319 | ||
320 | #define CONFIG_HAS_ETH0 | |
6d0f6bcf | 321 | #define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ |
8ba132ca | 322 | |
8ba132ca MF |
323 | #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ |
324 | #define CONFIG_PHY1_ADDR 1 | |
325 | #define CONFIG_RESET_PHY_R 1 | |
326 | ||
327 | /* USB */ | |
328 | #define CONFIG_USB_OHCI_NEW | |
329 | #define CONFIG_USB_STORAGE | |
6d0f6bcf | 330 | #define CONFIG_SYS_OHCI_BE_CONTROLLER |
8ba132ca | 331 | |
6d0f6bcf JCPV |
332 | #define CONFIG_SYS_USB_OHCI_BOARD_INIT 1 |
333 | #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 | |
334 | #define CONFIG_SYS_USB_OHCI_REGS_BASE CONFIG_SYS_USB_HOST | |
335 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440" | |
336 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 | |
8ba132ca MF |
337 | |
338 | /* Comment this out to enable USB 1.1 device */ | |
339 | #define USB_2_0_DEVICE | |
340 | ||
341 | /* Partitions */ | |
342 | #define CONFIG_MAC_PARTITION | |
343 | #define CONFIG_DOS_PARTITION | |
344 | #define CONFIG_ISO_PARTITION | |
345 | ||
346 | #include <config_cmd_default.h> | |
347 | ||
348 | #define CONFIG_CMD_BSP | |
349 | #define CONFIG_CMD_DATE | |
8ba132ca MF |
350 | #define CONFIG_CMD_DHCP |
351 | #define CONFIG_CMD_DTT | |
8ba132ca MF |
352 | #define CONFIG_CMD_EEPROM |
353 | #define CONFIG_CMD_ELF | |
354 | #define CONFIG_CMD_FAT | |
355 | #define CONFIG_CMD_I2C | |
8ba132ca MF |
356 | #define CONFIG_CMD_MII |
357 | #define CONFIG_CMD_NAND | |
358 | #define CONFIG_CMD_NET | |
359 | #define CONFIG_CMD_NFS | |
360 | #define CONFIG_CMD_PCI | |
361 | #define CONFIG_CMD_PING | |
362 | #define CONFIG_CMD_USB | |
363 | #define CONFIG_CMD_REGINFO | |
8ba132ca MF |
364 | |
365 | /* POST support */ | |
6d0f6bcf JCPV |
366 | #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ |
367 | CONFIG_SYS_POST_CPU | \ | |
368 | CONFIG_SYS_POST_UART | \ | |
369 | CONFIG_SYS_POST_I2C | \ | |
370 | CONFIG_SYS_POST_CACHE | \ | |
371 | CONFIG_SYS_POST_FPU | \ | |
372 | CONFIG_SYS_POST_ETHER | \ | |
373 | CONFIG_SYS_POST_SPR) | |
8ba132ca | 374 | |
8ba132ca | 375 | #define CONFIG_LOGBUFFER |
76b565b6 | 376 | #define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */ |
8ba132ca | 377 | |
6d0f6bcf | 378 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ |
8ba132ca MF |
379 | |
380 | #define CONFIG_SUPPORT_VFAT | |
381 | ||
382 | /*----------------------------------------------------------------------- | |
383 | * Miscellaneous configurable options | |
384 | *----------------------------------------------------------------------*/ | |
6d0f6bcf JCPV |
385 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
386 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
be88b169 | 387 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 388 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
8ba132ca | 389 | #else |
6d0f6bcf | 390 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
8ba132ca | 391 | #endif |
6d0f6bcf JCPV |
392 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
393 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
394 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
8ba132ca | 395 | |
6d0f6bcf JCPV |
396 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
397 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
8ba132ca | 398 | |
6d0f6bcf JCPV |
399 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
400 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
8ba132ca | 401 | |
6d0f6bcf | 402 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
8ba132ca MF |
403 | |
404 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
405 | #define CONFIG_LOOPW 1 /* enable loopw command */ | |
406 | #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ | |
407 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ | |
408 | #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ | |
409 | ||
410 | #define CONFIG_AUTOBOOT_KEYED 1 | |
c37207d7 WD |
411 | #define CONFIG_AUTOBOOT_PROMPT \ |
412 | "Press SPACE to abort autoboot in %d seconds\n", bootdelay | |
8ba132ca MF |
413 | #undef CONFIG_AUTOBOOT_DELAY_STR |
414 | #define CONFIG_AUTOBOOT_STOP_STR " " | |
415 | ||
416 | /*----------------------------------------------------------------------- | |
417 | * PCI stuff | |
418 | *----------------------------------------------------------------------*/ | |
419 | /* General PCI */ | |
420 | #define CONFIG_PCI /* include pci support */ | |
842033e6 | 421 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
8ba132ca | 422 | #define CONFIG_PCI_PNP /* do (not) pci plug-and-play */ |
6d0f6bcf | 423 | #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */ |
8ba132ca | 424 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
6d0f6bcf | 425 | #define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */ |
8ba132ca MF |
426 | |
427 | /* Board-specific PCI */ | |
6d0f6bcf JCPV |
428 | #define CONFIG_SYS_PCI_TARGET_INIT |
429 | #define CONFIG_SYS_PCI_MASTER_INIT | |
a760b020 | 430 | #define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ |
8ba132ca | 431 | |
2fe6b7f7 MF |
432 | #define CONFIG_PCI_BOOTDELAY 0 |
433 | ||
8ba132ca | 434 | /* PCI identification */ |
6d0f6bcf JCPV |
435 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ |
436 | #define CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH 0x0441 /* PCI Device ID: Non-Monarch */ | |
437 | #define CONFIG_SYS_PCI_SUBSYS_ID_MONARCH 0x0440 /* PCI Device ID: Monarch */ | |
1095493a SR |
438 | /* for weak __pci_target_init() */ |
439 | #define CONFIG_SYS_PCI_SUBSYS_ID CONFIG_SYS_PCI_SUBSYS_ID_MONARCH | |
6d0f6bcf JCPV |
440 | #define CONFIG_SYS_PCI_CLASSCODE_NONMONARCH PCI_CLASS_PROCESSOR_POWERPC |
441 | #define CONFIG_SYS_PCI_CLASSCODE_MONARCH PCI_CLASS_BRIDGE_HOST | |
8ba132ca MF |
442 | |
443 | /* | |
444 | * For booting Linux, the board info and command line data | |
445 | * have to be in the first 8 MB of memory, since this is | |
446 | * the maximum mapped by the Linux kernel during initialization. | |
447 | */ | |
6d0f6bcf | 448 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
8ba132ca MF |
449 | |
450 | /*----------------------------------------------------------------------- | |
451 | * FPGA stuff | |
452 | *----------------------------------------------------------------------*/ | |
453 | #define CONFIG_FPGA | |
454 | #define CONFIG_FPGA_XILINX | |
455 | #define CONFIG_FPGA_SPARTAN2 | |
456 | #define CONFIG_FPGA_SPARTAN3 | |
457 | ||
458 | #define CONFIG_FPGA_COUNT 2 | |
459 | /*----------------------------------------------------------------------- | |
460 | * External Bus Controller (EBC) Setup | |
461 | *----------------------------------------------------------------------*/ | |
462 | ||
463 | /* | |
464 | * On Sequoia CS0 and CS3 are switched when configuring for NAND booting | |
465 | */ | |
466 | #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) | |
6d0f6bcf | 467 | #define CONFIG_SYS_NAND_CS 2 /* NAND chip connected to CSx */ |
8ba132ca MF |
468 | |
469 | /* Memory Bank 0 (NOR-FLASH) initialization */ | |
6d0f6bcf JCPV |
470 | #define CONFIG_SYS_EBC_PB0AP 0x03017200 |
471 | #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE | 0xda000) | |
8ba132ca MF |
472 | |
473 | /* Memory Bank 2 (NAND-FLASH) initialization */ | |
6d0f6bcf JCPV |
474 | #define CONFIG_SYS_EBC_PB2AP 0x018003c0 |
475 | #define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_NAND_ADDR | 0x1c000) | |
8ba132ca | 476 | #else |
6d0f6bcf | 477 | #define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */ |
8ba132ca | 478 | /* Memory Bank 2 (NOR-FLASH) initialization */ |
6d0f6bcf JCPV |
479 | #define CONFIG_SYS_EBC_PB2AP 0x03017200 |
480 | #define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FLASH_BASE | 0xda000) | |
8ba132ca MF |
481 | |
482 | /* Memory Bank 0 (NAND-FLASH) initialization */ | |
6d0f6bcf JCPV |
483 | #define CONFIG_SYS_EBC_PB0AP 0x018003c0 |
484 | #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1c000) | |
8ba132ca MF |
485 | #endif |
486 | ||
76b565b6 | 487 | /* Memory Bank 1 (RESET) initialization */ |
455ae7e8 | 488 | #define CONFIG_SYS_EBC_PB1AP 0x7f817200 /* 0x03017200 */ |
3aed3aa2 | 489 | #define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_RESET_BASE | 0x1c000) |
76b565b6 | 490 | |
8ba132ca | 491 | /* Memory Bank 4 (FPGA / 32Bit) initialization */ |
6d0f6bcf JCPV |
492 | #define CONFIG_SYS_EBC_PB4AP 0x03840f40 /* BME=0,TWT=7,CSN=1,TH=7,RE=1,SOR=0,BEM=1 */ |
493 | #define CONFIG_SYS_EBC_PB4CR (CONFIG_SYS_FPGA_BASE0 | 0x1c000) /* BS=1M,BU=R/W,BW=32bit */ | |
8ba132ca MF |
494 | |
495 | /* Memory Bank 5 (FPGA / 16Bit) initialization */ | |
6d0f6bcf JCPV |
496 | #define CONFIG_SYS_EBC_PB5AP 0x03840f40 /* BME=0,TWT=3,CSN=1,TH=0,RE=1,SOR=0,BEM=1 */ |
497 | #define CONFIG_SYS_EBC_PB5CR (CONFIG_SYS_FPGA_BASE1 | 0x1a000) /* BS=1M,BU=R/W,BW=16bit */ | |
8ba132ca MF |
498 | |
499 | /*----------------------------------------------------------------------- | |
500 | * NAND FLASH | |
501 | *----------------------------------------------------------------------*/ | |
6d0f6bcf | 502 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
6d0f6bcf JCPV |
503 | #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS) |
504 | #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ | |
505 | #define CONFIG_SYS_NAND_QUIET_TEST 1 | |
8ba132ca | 506 | |
be88b169 | 507 | #if defined(CONFIG_CMD_KGDB) |
8ba132ca MF |
508 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
509 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
510 | #endif | |
511 | ||
512 | /* pass open firmware flat tree */ | |
513 | #define CONFIG_OF_LIBFDT 1 | |
514 | #define CONFIG_OF_BOARD_SETUP 1 | |
515 | ||
76b565b6 MF |
516 | #define CONFIG_API 1 |
517 | ||
8ba132ca | 518 | #endif /* __CONFIG_H */ |