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ee52b188 YS |
1 | /* |
2 | * Copyright 2011-2012 Freescale Semiconductor, Inc. | |
3 | * | |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
ee52b188 YS |
5 | */ |
6 | ||
7 | /* | |
8 | * T4240 QDS board configuration file | |
9 | */ | |
1cb19fbb YS |
10 | #ifndef __CONFIG_H |
11 | #define __CONFIG_H | |
12 | ||
ee52b188 YS |
13 | #define CONFIG_T4240QDS |
14 | #define CONFIG_PHYS_64BIT | |
677f970b | 15 | #define CONFIG_FSL_CLK |
ee52b188 YS |
16 | |
17 | #define CONFIG_FSL_SATA_V2 | |
18 | #define CONFIG_PCIE4 | |
737537ef | 19 | #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ |
ee52b188 YS |
20 | |
21 | #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ | |
22 | ||
1cb19fbb | 23 | #ifdef CONFIG_RAMBOOT_PBL |
e4536f8e MY |
24 | #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg |
25 | #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_rcw.cfg | |
b6036993 SX |
26 | #if !defined(CONFIG_NAND) && !defined(CONFIG_SDCARD) |
27 | #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE | |
28 | #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc | |
29 | #else | |
b6036993 SX |
30 | #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT |
31 | #define CONFIG_SPL_ENV_SUPPORT | |
32 | #define CONFIG_SPL_SERIAL_SUPPORT | |
33 | #define CONFIG_SPL_FLUSH_IMAGE | |
34 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
35 | #define CONFIG_SPL_LIBGENERIC_SUPPORT | |
36 | #define CONFIG_SPL_LIBCOMMON_SUPPORT | |
37 | #define CONFIG_SPL_I2C_SUPPORT | |
38 | #define CONFIG_SPL_DRIVERS_MISC_SUPPORT | |
39 | #define CONFIG_FSL_LAW /* Use common FSL init code */ | |
40 | #define CONFIG_SYS_TEXT_BASE 0x00201000 | |
41 | #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 | |
42 | #define CONFIG_SPL_PAD_TO 0x40000 | |
43 | #define CONFIG_SPL_MAX_SIZE 0x28000 | |
44 | #define RESET_VECTOR_OFFSET 0x27FFC | |
45 | #define BOOT_PAGE_OFFSET 0x27000 | |
46 | ||
47 | #ifdef CONFIG_NAND | |
48 | #define CONFIG_SPL_NAND_SUPPORT | |
49 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) | |
50 | #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 | |
51 | #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 | |
52 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) | |
53 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" | |
54 | #define CONFIG_SPL_NAND_BOOT | |
55 | #endif | |
56 | ||
57 | #ifdef CONFIG_SDCARD | |
58 | #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC | |
59 | #define CONFIG_SPL_MMC_SUPPORT | |
60 | #define CONFIG_SPL_MMC_MINIMAL | |
61 | #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) | |
62 | #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 | |
63 | #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 | |
64 | #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) | |
65 | #ifndef CONFIG_SPL_BUILD | |
66 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC | |
67 | #endif | |
68 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" | |
69 | #define CONFIG_SPL_MMC_BOOT | |
70 | #endif | |
71 | ||
72 | #ifdef CONFIG_SPL_BUILD | |
73 | #define CONFIG_SPL_SKIP_RELOCATE | |
74 | #define CONFIG_SPL_COMMON_INIT_DDR | |
75 | #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE | |
76 | #define CONFIG_SYS_NO_FLASH | |
77 | #endif | |
78 | ||
1cb19fbb | 79 | #endif |
b6036993 | 80 | #endif /* CONFIG_RAMBOOT_PBL */ |
1cb19fbb YS |
81 | |
82 | #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE | |
83 | /* Set 1M boot space */ | |
84 | #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) | |
85 | #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ | |
86 | (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) | |
87 | #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc | |
88 | #define CONFIG_SYS_NO_FLASH | |
89 | #endif | |
90 | ||
91 | #define CONFIG_SRIO_PCIE_BOOT_MASTER | |
92 | #define CONFIG_DDR_ECC | |
93 | ||
ee52b188 | 94 | #include "t4qds.h" |
1cb19fbb YS |
95 | |
96 | #ifdef CONFIG_SYS_NO_FLASH | |
97 | #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) | |
98 | #define CONFIG_ENV_IS_NOWHERE | |
99 | #endif | |
100 | #else | |
101 | #define CONFIG_FLASH_CFI_DRIVER | |
102 | #define CONFIG_SYS_FLASH_CFI | |
103 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
104 | #endif | |
105 | ||
106 | #if defined(CONFIG_SPIFLASH) | |
107 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
108 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
109 | #define CONFIG_ENV_SPI_BUS 0 | |
110 | #define CONFIG_ENV_SPI_CS 0 | |
111 | #define CONFIG_ENV_SPI_MAX_HZ 10000000 | |
112 | #define CONFIG_ENV_SPI_MODE 0 | |
113 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ | |
114 | #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ | |
115 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
116 | #elif defined(CONFIG_SDCARD) | |
117 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
118 | #define CONFIG_ENV_IS_IN_MMC | |
119 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
120 | #define CONFIG_ENV_SIZE 0x2000 | |
b6036993 | 121 | #define CONFIG_ENV_OFFSET (512 * 0x800) |
1cb19fbb YS |
122 | #elif defined(CONFIG_NAND) |
123 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
124 | #define CONFIG_ENV_IS_IN_NAND | |
b6036993 SX |
125 | #define CONFIG_ENV_SIZE 0x2000 |
126 | #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) | |
1cb19fbb YS |
127 | #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) |
128 | #define CONFIG_ENV_IS_IN_REMOTE | |
129 | #define CONFIG_ENV_ADDR 0xffe20000 | |
130 | #define CONFIG_ENV_SIZE 0x2000 | |
131 | #elif defined(CONFIG_ENV_IS_NOWHERE) | |
132 | #define CONFIG_ENV_SIZE 0x2000 | |
133 | #else | |
134 | #define CONFIG_ENV_IS_IN_FLASH | |
135 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) | |
136 | #define CONFIG_ENV_SIZE 0x2000 | |
137 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
138 | #endif | |
139 | ||
140 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() | |
141 | #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() | |
142 | ||
143 | #ifndef __ASSEMBLY__ | |
144 | unsigned long get_board_sys_clk(void); | |
145 | unsigned long get_board_ddr_clk(void); | |
146 | #endif | |
147 | ||
148 | /* EEPROM */ | |
149 | #define CONFIG_ID_EEPROM | |
150 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
151 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 | |
152 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
153 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
154 | ||
155 | /* | |
156 | * DDR Setup | |
157 | */ | |
158 | #define CONFIG_SYS_SPD_BUS_NUM 0 | |
159 | #define SPD_EEPROM_ADDRESS1 0x51 | |
160 | #define SPD_EEPROM_ADDRESS2 0x52 | |
161 | #define SPD_EEPROM_ADDRESS3 0x53 | |
162 | #define SPD_EEPROM_ADDRESS4 0x54 | |
163 | #define SPD_EEPROM_ADDRESS5 0x55 | |
164 | #define SPD_EEPROM_ADDRESS6 0x56 | |
165 | #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ | |
166 | #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ | |
167 | ||
168 | /* | |
169 | * IFC Definitions | |
170 | */ | |
171 | #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) | |
172 | #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ | |
173 | + 0x8000000) | \ | |
174 | CSPR_PORT_SIZE_16 | \ | |
175 | CSPR_MSEL_NOR | \ | |
176 | CSPR_V) | |
177 | #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) | |
178 | #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ | |
179 | CSPR_PORT_SIZE_16 | \ | |
180 | CSPR_MSEL_NOR | \ | |
181 | CSPR_V) | |
182 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) | |
183 | /* NOR Flash Timing Params */ | |
184 | #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 | |
185 | ||
186 | #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ | |
187 | FTIM0_NOR_TEADC(0x5) | \ | |
188 | FTIM0_NOR_TEAHC(0x5)) | |
189 | #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ | |
190 | FTIM1_NOR_TRAD_NOR(0x1A) |\ | |
191 | FTIM1_NOR_TSEQRAD_NOR(0x13)) | |
192 | #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ | |
193 | FTIM2_NOR_TCH(0x4) | \ | |
194 | FTIM2_NOR_TWPH(0x0E) | \ | |
195 | FTIM2_NOR_TWP(0x1c)) | |
196 | #define CONFIG_SYS_NOR_FTIM3 0x0 | |
197 | ||
198 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
199 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
200 | ||
201 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ | |
202 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
203 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
204 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
205 | ||
206 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
207 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ | |
208 | + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} | |
209 | ||
210 | #define CONFIG_FSL_QIXIS /* use common QIXIS code */ | |
211 | #define QIXIS_BASE 0xffdf0000 | |
212 | #define QIXIS_LBMAP_SWITCH 6 | |
213 | #define QIXIS_LBMAP_MASK 0x0f | |
214 | #define QIXIS_LBMAP_SHIFT 0 | |
215 | #define QIXIS_LBMAP_DFLTBANK 0x00 | |
216 | #define QIXIS_LBMAP_ALTBANK 0x04 | |
217 | #define QIXIS_RST_CTL_RESET 0x83 | |
c63e1370 | 218 | #define QIXIS_RST_FORCE_MEM 0x1 |
1cb19fbb YS |
219 | #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 |
220 | #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 | |
221 | #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 | |
f7e27cc5 HZ |
222 | #define QIXIS_BRDCFG5 0x55 |
223 | #define QIXIS_MUX_SDHC 2 | |
d47e3d27 | 224 | #define QIXIS_MUX_SDHC_WIDTH8 1 |
1cb19fbb YS |
225 | #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) |
226 | ||
227 | #define CONFIG_SYS_CSPR3_EXT (0xf) | |
228 | #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ | |
229 | | CSPR_PORT_SIZE_8 \ | |
230 | | CSPR_MSEL_GPCM \ | |
231 | | CSPR_V) | |
232 | #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) | |
233 | #define CONFIG_SYS_CSOR3 0x0 | |
234 | /* QIXIS Timing parameters for IFC CS3 */ | |
235 | #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ | |
236 | FTIM0_GPCM_TEADC(0x0e) | \ | |
237 | FTIM0_GPCM_TEAHC(0x0e)) | |
238 | #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ | |
239 | FTIM1_GPCM_TRAD(0x3f)) | |
240 | #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ | |
de519163 | 241 | FTIM2_GPCM_TCH(0x8) | \ |
1cb19fbb YS |
242 | FTIM2_GPCM_TWP(0x1f)) |
243 | #define CONFIG_SYS_CS3_FTIM3 0x0 | |
244 | ||
245 | /* NAND Flash on IFC */ | |
246 | #define CONFIG_NAND_FSL_IFC | |
247 | #define CONFIG_SYS_NAND_BASE 0xff800000 | |
248 | #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) | |
249 | ||
250 | #define CONFIG_SYS_NAND_CSPR_EXT (0xf) | |
251 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
252 | | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ | |
253 | | CSPR_MSEL_NAND /* MSEL = NAND */ \ | |
254 | | CSPR_V) | |
255 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) | |
256 | ||
257 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | |
258 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | |
259 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | |
260 | | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ | |
261 | | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ | |
262 | | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ | |
263 | | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ | |
264 | ||
265 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
266 | ||
267 | /* ONFI NAND Flash mode0 Timing Params */ | |
268 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ | |
269 | FTIM0_NAND_TWP(0x18) | \ | |
270 | FTIM0_NAND_TWCHT(0x07) | \ | |
271 | FTIM0_NAND_TWH(0x0a)) | |
272 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ | |
273 | FTIM1_NAND_TWBE(0x39) | \ | |
274 | FTIM1_NAND_TRR(0x0e) | \ | |
275 | FTIM1_NAND_TRP(0x18)) | |
276 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ | |
277 | FTIM2_NAND_TREH(0x0a) | \ | |
278 | FTIM2_NAND_TWHRE(0x1e)) | |
279 | #define CONFIG_SYS_NAND_FTIM3 0x0 | |
280 | ||
281 | #define CONFIG_SYS_NAND_DDR_LAW 11 | |
282 | ||
283 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } | |
284 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
1cb19fbb YS |
285 | #define CONFIG_CMD_NAND |
286 | ||
287 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
68ec9c85 PK |
288 | #define CONFIG_SYS_NAND_MAX_OOBFREE 2 |
289 | #define CONFIG_SYS_NAND_MAX_ECCPOS 256 | |
1cb19fbb YS |
290 | |
291 | #if defined(CONFIG_NAND) | |
292 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT | |
293 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR | |
294 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK | |
295 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR | |
296 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
297 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
298 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
299 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
b6036993 SX |
300 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT |
301 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR | |
302 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK | |
303 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR | |
304 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
305 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
306 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
307 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
308 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT | |
309 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR | |
1cb19fbb YS |
310 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK |
311 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR | |
312 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
313 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
314 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
315 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
316 | #else | |
317 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT | |
318 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR | |
319 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK | |
320 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR | |
321 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
322 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
323 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
324 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
b6036993 SX |
325 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT |
326 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR | |
327 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK | |
328 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR | |
329 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
330 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
331 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
332 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
1cb19fbb YS |
333 | #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT |
334 | #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR | |
335 | #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK | |
336 | #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR | |
337 | #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
338 | #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
339 | #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
340 | #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
341 | #endif | |
1cb19fbb YS |
342 | |
343 | #if defined(CONFIG_RAMBOOT_PBL) | |
344 | #define CONFIG_SYS_RAMBOOT | |
345 | #endif | |
346 | ||
347 | ||
348 | /* I2C */ | |
349 | #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ | |
350 | #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ | |
351 | #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ | |
352 | #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ | |
353 | ||
354 | #define I2C_MUX_CH_DEFAULT 0x8 | |
355 | #define I2C_MUX_CH_VOL_MONITOR 0xa | |
356 | #define I2C_MUX_CH_VSC3316_FS 0xc | |
357 | #define I2C_MUX_CH_VSC3316_BS 0xd | |
358 | ||
359 | /* Voltage monitor on channel 2*/ | |
360 | #define I2C_VOL_MONITOR_ADDR 0x40 | |
361 | #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 | |
362 | #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 | |
363 | #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 | |
364 | ||
365 | /* VSC Crossbar switches */ | |
366 | #define CONFIG_VSC_CROSSBAR | |
367 | #define VSC3316_FSM_TX_ADDR 0x70 | |
368 | #define VSC3316_FSM_RX_ADDR 0x71 | |
369 | ||
370 | /* | |
371 | * RapidIO | |
372 | */ | |
373 | ||
374 | /* | |
375 | * for slave u-boot IMAGE instored in master memory space, | |
376 | * PHYS must be aligned based on the SIZE | |
377 | */ | |
e4911815 LG |
378 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull |
379 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull | |
380 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ | |
381 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull | |
1cb19fbb YS |
382 | /* |
383 | * for slave UCODE and ENV instored in master memory space, | |
384 | * PHYS must be aligned based on the SIZE | |
385 | */ | |
e4911815 | 386 | #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull |
1cb19fbb YS |
387 | #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull |
388 | #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ | |
389 | ||
390 | /* slave core release by master*/ | |
391 | #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 | |
392 | #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ | |
393 | ||
394 | /* | |
395 | * SRIO_PCIE_BOOT - SLAVE | |
396 | */ | |
397 | #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE | |
398 | #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 | |
399 | #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ | |
400 | (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) | |
401 | #endif | |
402 | /* | |
403 | * eSPI - Enhanced SPI | |
404 | */ | |
405 | #define CONFIG_FSL_ESPI | |
1cb19fbb YS |
406 | #define CONFIG_SPI_FLASH_SST |
407 | #define CONFIG_CMD_SF | |
408 | #define CONFIG_SF_DEFAULT_SPEED 10000000 | |
409 | #define CONFIG_SF_DEFAULT_MODE 0 | |
410 | ||
411 | ||
412 | /* Qman/Bman */ | |
413 | #ifndef CONFIG_NOBQFMAN | |
414 | #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ | |
415 | #define CONFIG_SYS_BMAN_NUM_PORTALS 50 | |
416 | #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 | |
417 | #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull | |
418 | #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 | |
3fa66db4 JL |
419 | #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 |
420 | #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 | |
421 | #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE | |
422 | #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) | |
423 | #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ | |
424 | CONFIG_SYS_BMAN_CENA_SIZE) | |
425 | #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) | |
426 | #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 | |
1cb19fbb YS |
427 | #define CONFIG_SYS_QMAN_NUM_PORTALS 50 |
428 | #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 | |
429 | #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull | |
430 | #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 | |
3fa66db4 JL |
431 | #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 |
432 | #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 | |
433 | #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE | |
434 | #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) | |
435 | #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ | |
436 | CONFIG_SYS_QMAN_CENA_SIZE) | |
437 | #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) | |
438 | #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 | |
1cb19fbb YS |
439 | |
440 | #define CONFIG_SYS_DPAA_FMAN | |
441 | #define CONFIG_SYS_DPAA_PME | |
442 | #define CONFIG_SYS_PMAN | |
443 | #define CONFIG_SYS_DPAA_DCE | |
0795eff3 | 444 | #define CONFIG_SYS_DPAA_RMAN |
1cb19fbb YS |
445 | #define CONFIG_SYS_INTERLAKEN |
446 | ||
447 | /* Default address of microcode for the Linux Fman driver */ | |
448 | #if defined(CONFIG_SPIFLASH) | |
449 | /* | |
450 | * env is stored at 0x100000, sector size is 0x10000, ucode is stored after | |
451 | * env, so we got 0x110000. | |
452 | */ | |
453 | #define CONFIG_SYS_QE_FW_IN_SPIFLASH | |
dcf1d774 | 454 | #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 |
1cb19fbb YS |
455 | #elif defined(CONFIG_SDCARD) |
456 | /* | |
457 | * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is | |
b6036993 SX |
458 | * about 1MB (2048 blocks), Env is stored after the image, and the env size is |
459 | * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. | |
1cb19fbb YS |
460 | */ |
461 | #define CONFIG_SYS_QE_FMAN_FW_IN_MMC | |
b6036993 | 462 | #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) |
1cb19fbb YS |
463 | #elif defined(CONFIG_NAND) |
464 | #define CONFIG_SYS_QE_FMAN_FW_IN_NAND | |
b6036993 | 465 | #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) |
1cb19fbb YS |
466 | #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) |
467 | /* | |
468 | * Slave has no ucode locally, it can fetch this from remote. When implementing | |
469 | * in two corenet boards, slave's ucode could be stored in master's memory | |
470 | * space, the address can be mapped from slave TLB->slave LAW-> | |
471 | * slave SRIO or PCIE outbound window->master inbound window-> | |
472 | * master LAW->the ucode address in master's memory space. | |
473 | */ | |
474 | #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE | |
dcf1d774 | 475 | #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 |
1cb19fbb YS |
476 | #else |
477 | #define CONFIG_SYS_QE_FMAN_FW_IN_NOR | |
dcf1d774 | 478 | #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 |
1cb19fbb YS |
479 | #endif |
480 | #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 | |
481 | #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) | |
482 | #endif /* CONFIG_NOBQFMAN */ | |
483 | ||
484 | #ifdef CONFIG_SYS_DPAA_FMAN | |
485 | #define CONFIG_FMAN_ENET | |
486 | #define CONFIG_PHYLIB_10G | |
487 | #define CONFIG_PHY_VITESSE | |
488 | #define CONFIG_PHY_TERANETICS | |
489 | #define SGMII_CARD_PORT1_PHY_ADDR 0x1C | |
490 | #define SGMII_CARD_PORT2_PHY_ADDR 0x1D | |
491 | #define SGMII_CARD_PORT3_PHY_ADDR 0x1E | |
492 | #define SGMII_CARD_PORT4_PHY_ADDR 0x1F | |
493 | #define FM1_10GEC1_PHY_ADDR 0x0 | |
494 | #define FM1_10GEC2_PHY_ADDR 0x1 | |
495 | #define FM2_10GEC1_PHY_ADDR 0x2 | |
496 | #define FM2_10GEC2_PHY_ADDR 0x3 | |
497 | #endif | |
498 | ||
499 | ||
500 | /* SATA */ | |
501 | #ifdef CONFIG_FSL_SATA_V2 | |
502 | #define CONFIG_LIBATA | |
503 | #define CONFIG_FSL_SATA | |
504 | ||
505 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 | |
506 | #define CONFIG_SATA1 | |
507 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR | |
508 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
509 | #define CONFIG_SATA2 | |
510 | #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR | |
511 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
512 | ||
513 | #define CONFIG_LBA48 | |
514 | #define CONFIG_CMD_SATA | |
515 | #define CONFIG_DOS_PARTITION | |
516 | #define CONFIG_CMD_EXT2 | |
517 | #endif | |
518 | ||
519 | #ifdef CONFIG_FMAN_ENET | |
520 | #define CONFIG_MII /* MII PHY management */ | |
521 | #define CONFIG_ETHPRIME "FM1@DTSEC1" | |
522 | #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ | |
523 | #endif | |
524 | ||
737537ef RG |
525 | /* Hash command with SHA acceleration supported in hardware */ |
526 | #ifdef CONFIG_FSL_CAAM | |
527 | #define CONFIG_CMD_HASH | |
528 | #define CONFIG_SHA_HW_ACCEL | |
529 | #endif | |
530 | ||
1cb19fbb YS |
531 | /* |
532 | * USB | |
533 | */ | |
534 | #define CONFIG_CMD_USB | |
535 | #define CONFIG_USB_STORAGE | |
536 | #define CONFIG_USB_EHCI | |
537 | #define CONFIG_USB_EHCI_FSL | |
538 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
539 | #define CONFIG_CMD_EXT2 | |
540 | #define CONFIG_HAS_FSL_DR_USB | |
541 | ||
542 | #define CONFIG_MMC | |
543 | ||
544 | #ifdef CONFIG_MMC | |
545 | #define CONFIG_FSL_ESDHC | |
546 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR | |
547 | #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT | |
548 | #define CONFIG_CMD_MMC | |
549 | #define CONFIG_GENERIC_MMC | |
550 | #define CONFIG_CMD_EXT2 | |
551 | #define CONFIG_CMD_FAT | |
552 | #define CONFIG_DOS_PARTITION | |
ef38f3ff | 553 | #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 |
f7e27cc5 HZ |
554 | #define CONFIG_ESDHC_DETECT_QUIRK \ |
555 | (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \ | |
556 | IS_SVR_REV(get_svr(), 1, 0)) | |
d47e3d27 HZ |
557 | #define CONFIG_ESDHC_DETECT_8_BIT_QUIRK \ |
558 | (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8)) | |
1cb19fbb YS |
559 | #endif |
560 | ||
561 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
562 | ||
563 | #define __USB_PHY_TYPE utmi | |
564 | ||
565 | /* | |
566 | * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be | |
567 | * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way | |
568 | * interleaving. It can be cacheline, page, bank, superbank. | |
569 | * See doc/README.fsl-ddr for details. | |
570 | */ | |
571 | #ifdef CONFIG_PPC_T4240 | |
572 | #define CTRL_INTLV_PREFERED 3way_4KB | |
573 | #else | |
574 | #define CTRL_INTLV_PREFERED cacheline | |
575 | #endif | |
576 | ||
577 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
578 | "hwconfig=fsl_ddr:" \ | |
579 | "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ | |
580 | "bank_intlv=auto;" \ | |
581 | "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ | |
582 | "netdev=eth0\0" \ | |
583 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ | |
584 | "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ | |
585 | "tftpflash=tftpboot $loadaddr $uboot && " \ | |
586 | "protect off $ubootaddr +$filesize && " \ | |
587 | "erase $ubootaddr +$filesize && " \ | |
588 | "cp.b $loadaddr $ubootaddr $filesize && " \ | |
589 | "protect on $ubootaddr +$filesize && " \ | |
590 | "cmp.b $loadaddr $ubootaddr $filesize\0" \ | |
591 | "consoledev=ttyS0\0" \ | |
592 | "ramdiskaddr=2000000\0" \ | |
593 | "ramdiskfile=t4240qds/ramdisk.uboot\0" \ | |
594 | "fdtaddr=c00000\0" \ | |
595 | "fdtfile=t4240qds/t4240qds.dtb\0" \ | |
3246584d | 596 | "bdev=sda3\0" |
1cb19fbb YS |
597 | |
598 | #define CONFIG_HVBOOT \ | |
599 | "setenv bootargs config-addr=0x60000000; " \ | |
600 | "bootm 0x01000000 - 0x00f00000" | |
601 | ||
602 | #define CONFIG_ALU \ | |
603 | "setenv bootargs root=/dev/$bdev rw " \ | |
604 | "console=$consoledev,$baudrate $othbootargs;" \ | |
605 | "cpu 1 release 0x01000000 - - -;" \ | |
606 | "cpu 2 release 0x01000000 - - -;" \ | |
607 | "cpu 3 release 0x01000000 - - -;" \ | |
608 | "cpu 4 release 0x01000000 - - -;" \ | |
609 | "cpu 5 release 0x01000000 - - -;" \ | |
610 | "cpu 6 release 0x01000000 - - -;" \ | |
611 | "cpu 7 release 0x01000000 - - -;" \ | |
612 | "go 0x01000000" | |
613 | ||
614 | #define CONFIG_LINUX \ | |
615 | "setenv bootargs root=/dev/ram rw " \ | |
616 | "console=$consoledev,$baudrate $othbootargs;" \ | |
617 | "setenv ramdiskaddr 0x02000000;" \ | |
618 | "setenv fdtaddr 0x00c00000;" \ | |
619 | "setenv loadaddr 0x1000000;" \ | |
620 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
621 | ||
622 | #define CONFIG_HDBOOT \ | |
623 | "setenv bootargs root=/dev/$bdev rw " \ | |
624 | "console=$consoledev,$baudrate $othbootargs;" \ | |
625 | "tftp $loadaddr $bootfile;" \ | |
626 | "tftp $fdtaddr $fdtfile;" \ | |
627 | "bootm $loadaddr - $fdtaddr" | |
628 | ||
629 | #define CONFIG_NFSBOOTCOMMAND \ | |
630 | "setenv bootargs root=/dev/nfs rw " \ | |
631 | "nfsroot=$serverip:$rootpath " \ | |
632 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
633 | "console=$consoledev,$baudrate $othbootargs;" \ | |
634 | "tftp $loadaddr $bootfile;" \ | |
635 | "tftp $fdtaddr $fdtfile;" \ | |
636 | "bootm $loadaddr - $fdtaddr" | |
637 | ||
638 | #define CONFIG_RAMBOOTCOMMAND \ | |
639 | "setenv bootargs root=/dev/ram rw " \ | |
640 | "console=$consoledev,$baudrate $othbootargs;" \ | |
641 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
642 | "tftp $loadaddr $bootfile;" \ | |
643 | "tftp $fdtaddr $fdtfile;" \ | |
644 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
645 | ||
646 | #define CONFIG_BOOTCOMMAND CONFIG_LINUX | |
647 | ||
1cb19fbb | 648 | #include <asm/fsl_secure_boot.h> |
1cb19fbb | 649 | |
789490b6 RG |
650 | #ifdef CONFIG_SECURE_BOOT |
651 | #define CONFIG_CMD_BLOB | |
652 | #endif | |
653 | ||
1cb19fbb | 654 | #endif /* __CONFIG_H */ |