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d126bfbd | 1 | /* |
29f8f58f | 2 | * (C) Copyright 2000-2008 |
d126bfbd WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * board/config.h - configuration options, board specific | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
31 | /* | |
32 | * High Level Configuration Options | |
33 | * (easy to change) | |
34 | */ | |
35 | ||
36 | #define CONFIG_MPC860 1 | |
37 | #define CONFIG_MPC860T 1 | |
38 | #define CONFIG_MPC862 1 | |
39 | ||
40 | #define CONFIG_TQM862L 1 /* ...on a TQM8xxL module */ | |
41 | ||
2ae18241 WD |
42 | #define CONFIG_SYS_TEXT_BASE 0x40000000 |
43 | ||
d126bfbd | 44 | #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
3cb7a480 WD |
45 | #define CONFIG_SYS_SMC_RXBUFLEN 128 |
46 | #define CONFIG_SYS_MAXIDLE 10 | |
d126bfbd WD |
47 | #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ |
48 | ||
ae3af05e | 49 | #define CONFIG_BOOTCOUNT_LIMIT |
d126bfbd | 50 | |
ae3af05e | 51 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
d126bfbd WD |
52 | |
53 | #define CONFIG_BOARD_TYPES 1 /* support board types */ | |
54 | ||
55 | #define CONFIG_PREBOOT "echo;" \ | |
32bf3d14 | 56 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
d126bfbd WD |
57 | "echo" |
58 | ||
59 | #undef CONFIG_BOOTARGS | |
60 | ||
61 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
ae3af05e | 62 | "netdev=eth0\0" \ |
d126bfbd | 63 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
fe126d8b | 64 | "nfsroot=${serverip}:${rootpath}\0" \ |
d126bfbd | 65 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
fe126d8b WD |
66 | "addip=setenv bootargs ${bootargs} " \ |
67 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
68 | ":${hostname}:${netdev}:off panic=1\0" \ | |
d126bfbd | 69 | "flash_nfs=run nfsargs addip;" \ |
fe126d8b | 70 | "bootm ${kernel_addr}\0" \ |
d126bfbd | 71 | "flash_self=run ramargs addip;" \ |
fe126d8b WD |
72 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
73 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ | |
d126bfbd | 74 | "rootpath=/opt/eldk/ppc_8xx\0" \ |
29f8f58f WD |
75 | "hostname=TQM862L\0" \ |
76 | "bootfile=TQM862L/uImage\0" \ | |
eb6da805 WD |
77 | "fdt_addr=40040000\0" \ |
78 | "kernel_addr=40060000\0" \ | |
79 | "ramdisk_addr=40200000\0" \ | |
29f8f58f WD |
80 | "u-boot=TQM862L/u-image.bin\0" \ |
81 | "load=tftp 200000 ${u-boot}\0" \ | |
82 | "update=prot off 40000000 +${filesize};" \ | |
83 | "era 40000000 +${filesize};" \ | |
84 | "cp.b 200000 40000000 ${filesize};" \ | |
85 | "sete filesize;save\0" \ | |
d126bfbd WD |
86 | "" |
87 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
88 | ||
89 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 90 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
d126bfbd WD |
91 | |
92 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
93 | ||
94 | #define CONFIG_STATUS_LED 1 /* Status LED enabled */ | |
95 | ||
96 | #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ | |
97 | ||
37d4bb70 JL |
98 | /* |
99 | * BOOTP options | |
100 | */ | |
101 | #define CONFIG_BOOTP_SUBNETMASK | |
102 | #define CONFIG_BOOTP_GATEWAY | |
103 | #define CONFIG_BOOTP_HOSTNAME | |
104 | #define CONFIG_BOOTP_BOOTPATH | |
105 | #define CONFIG_BOOTP_BOOTFILESIZE | |
106 | ||
d126bfbd WD |
107 | |
108 | #define CONFIG_MAC_PARTITION | |
109 | #define CONFIG_DOS_PARTITION | |
110 | ||
111 | #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ | |
112 | ||
d126bfbd | 113 | |
2694690e JL |
114 | /* |
115 | * Command line configuration. | |
116 | */ | |
117 | #include <config_cmd_default.h> | |
118 | ||
119 | #define CONFIG_CMD_ASKENV | |
120 | #define CONFIG_CMD_DATE | |
121 | #define CONFIG_CMD_DHCP | |
29f8f58f | 122 | #define CONFIG_CMD_ELF |
9a63b7f4 | 123 | #define CONFIG_CMD_EXT2 |
2694690e | 124 | #define CONFIG_CMD_IDE |
29f8f58f | 125 | #define CONFIG_CMD_JFFS2 |
2694690e JL |
126 | #define CONFIG_CMD_NFS |
127 | #define CONFIG_CMD_SNTP | |
128 | ||
d126bfbd | 129 | |
29f8f58f WD |
130 | #define CONFIG_NETCONSOLE |
131 | ||
132 | ||
d126bfbd WD |
133 | /* |
134 | * Miscellaneous configurable options | |
135 | */ | |
6d0f6bcf JCPV |
136 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
137 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
d126bfbd | 138 | |
2751a95a | 139 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
6d0f6bcf | 140 | #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ |
d126bfbd | 141 | |
2694690e | 142 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 143 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
d126bfbd | 144 | #else |
6d0f6bcf | 145 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
d126bfbd | 146 | #endif |
6d0f6bcf JCPV |
147 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
148 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
149 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
d126bfbd | 150 | |
6d0f6bcf JCPV |
151 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
152 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
d126bfbd | 153 | |
6d0f6bcf | 154 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
d126bfbd | 155 | |
6d0f6bcf | 156 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
d126bfbd | 157 | |
d126bfbd WD |
158 | /* |
159 | * Low Level Configuration Settings | |
160 | * (address mappings, register initial values, etc.) | |
161 | * You should know what you are doing if you make changes here. | |
162 | */ | |
163 | /*----------------------------------------------------------------------- | |
164 | * Internal Memory Mapped Register | |
165 | */ | |
6d0f6bcf | 166 | #define CONFIG_SYS_IMMR 0xFFF00000 |
d126bfbd WD |
167 | |
168 | /*----------------------------------------------------------------------- | |
169 | * Definitions for initial stack pointer and data area (in DPRAM) | |
170 | */ | |
6d0f6bcf | 171 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
553f0982 | 172 | #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ |
25ddd1fb | 173 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 174 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
d126bfbd WD |
175 | |
176 | /*----------------------------------------------------------------------- | |
177 | * Start addresses for the final memory configuration | |
178 | * (Set up by the startup code) | |
6d0f6bcf | 179 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
d126bfbd | 180 | */ |
6d0f6bcf JCPV |
181 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
182 | #define CONFIG_SYS_FLASH_BASE 0x40000000 | |
183 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
184 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
185 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
d126bfbd WD |
186 | |
187 | /* | |
188 | * For booting Linux, the board info and command line data | |
189 | * have to be in the first 8 MB of memory, since this is | |
190 | * the maximum mapped by the Linux kernel during initialization. | |
191 | */ | |
6d0f6bcf | 192 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
d126bfbd WD |
193 | |
194 | /*----------------------------------------------------------------------- | |
195 | * FLASH organization | |
196 | */ | |
d126bfbd | 197 | |
e318d9e9 | 198 | /* use CFI flash driver */ |
6d0f6bcf | 199 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
00b1883a | 200 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ |
6d0f6bcf JCPV |
201 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size } |
202 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
203 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 | |
204 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ | |
205 | #define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ | |
d126bfbd | 206 | |
5a1aceb0 | 207 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
208 | #define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ |
209 | #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ | |
d126bfbd WD |
210 | |
211 | /* Address and size of Redundant Environment Sector */ | |
0e8d1586 JCPV |
212 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) |
213 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
d126bfbd | 214 | |
6d0f6bcf | 215 | #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ |
67c31036 | 216 | |
7c803be2 WD |
217 | #define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ |
218 | ||
29f8f58f WD |
219 | /*----------------------------------------------------------------------- |
220 | * Dynamic MTD partition support | |
221 | */ | |
68d7d651 | 222 | #define CONFIG_CMD_MTDPARTS |
942556a9 SR |
223 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
224 | #define CONFIG_FLASH_CFI_MTD | |
29f8f58f WD |
225 | #define MTDIDS_DEFAULT "nor0=TQM8xxL-0" |
226 | ||
227 | #define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ | |
228 | "128k(dtb)," \ | |
229 | "1664k(kernel)," \ | |
230 | "2m(rootfs)," \ | |
cd82919e | 231 | "4m(data)" |
29f8f58f | 232 | |
d126bfbd WD |
233 | /*----------------------------------------------------------------------- |
234 | * Hardware Information Block | |
235 | */ | |
6d0f6bcf JCPV |
236 | #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ |
237 | #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ | |
238 | #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ | |
d126bfbd WD |
239 | |
240 | /*----------------------------------------------------------------------- | |
241 | * Cache Configuration | |
242 | */ | |
6d0f6bcf | 243 | #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
2694690e | 244 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 245 | #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
d126bfbd WD |
246 | #endif |
247 | ||
248 | /*----------------------------------------------------------------------- | |
249 | * SYPCR - System Protection Control 11-9 | |
250 | * SYPCR can only be written once after reset! | |
251 | *----------------------------------------------------------------------- | |
252 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
253 | */ | |
254 | #if defined(CONFIG_WATCHDOG) | |
6d0f6bcf | 255 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
d126bfbd WD |
256 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
257 | #else | |
6d0f6bcf | 258 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
d126bfbd WD |
259 | #endif |
260 | ||
261 | /*----------------------------------------------------------------------- | |
262 | * SIUMCR - SIU Module Configuration 11-6 | |
263 | *----------------------------------------------------------------------- | |
264 | * PCMCIA config., multi-function pin tri-state | |
265 | */ | |
266 | #ifndef CONFIG_CAN_DRIVER | |
6d0f6bcf | 267 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
d126bfbd | 268 | #else /* we must activate GPL5 in the SIUMCR for CAN */ |
6d0f6bcf | 269 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
d126bfbd WD |
270 | #endif /* CONFIG_CAN_DRIVER */ |
271 | ||
272 | /*----------------------------------------------------------------------- | |
273 | * TBSCR - Time Base Status and Control 11-26 | |
274 | *----------------------------------------------------------------------- | |
275 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
276 | */ | |
6d0f6bcf | 277 | #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
d126bfbd WD |
278 | |
279 | /*----------------------------------------------------------------------- | |
280 | * RTCSC - Real-Time Clock Status and Control Register 11-27 | |
281 | *----------------------------------------------------------------------- | |
282 | */ | |
6d0f6bcf | 283 | #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
d126bfbd WD |
284 | |
285 | /*----------------------------------------------------------------------- | |
286 | * PISCR - Periodic Interrupt Status and Control 11-31 | |
287 | *----------------------------------------------------------------------- | |
288 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
289 | */ | |
6d0f6bcf | 290 | #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
d126bfbd WD |
291 | |
292 | /*----------------------------------------------------------------------- | |
293 | * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 | |
294 | *----------------------------------------------------------------------- | |
295 | * Reset PLL lock status sticky bit, timer expired status bit and timer | |
296 | * interrupt status bit | |
d126bfbd | 297 | */ |
6d0f6bcf | 298 | #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) |
d126bfbd WD |
299 | |
300 | /*----------------------------------------------------------------------- | |
301 | * SCCR - System Clock and reset Control Register 15-27 | |
302 | *----------------------------------------------------------------------- | |
303 | * Set clock output, timebase and RTC source and divider, | |
304 | * power management and some other internal clocks | |
305 | */ | |
306 | #define SCCR_MASK SCCR_EBDF11 | |
6d0f6bcf | 307 | #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ |
d126bfbd WD |
308 | SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ |
309 | SCCR_DFALCD00) | |
d126bfbd WD |
310 | |
311 | /*----------------------------------------------------------------------- | |
312 | * PCMCIA stuff | |
313 | *----------------------------------------------------------------------- | |
314 | * | |
315 | */ | |
6d0f6bcf JCPV |
316 | #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) |
317 | #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) | |
318 | #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) | |
319 | #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) | |
320 | #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) | |
321 | #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) | |
322 | #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) | |
323 | #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) | |
d126bfbd WD |
324 | |
325 | /*----------------------------------------------------------------------- | |
326 | * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) | |
327 | *----------------------------------------------------------------------- | |
328 | */ | |
329 | ||
8d1165e1 | 330 | #define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ |
d126bfbd WD |
331 | #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ |
332 | ||
333 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
334 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
335 | #undef CONFIG_IDE_RESET /* reset for ide not supported */ | |
336 | ||
6d0f6bcf JCPV |
337 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
338 | #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ | |
d126bfbd | 339 | |
6d0f6bcf | 340 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
d126bfbd | 341 | |
6d0f6bcf | 342 | #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR |
d126bfbd WD |
343 | |
344 | /* Offset for data I/O */ | |
6d0f6bcf | 345 | #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
d126bfbd WD |
346 | |
347 | /* Offset for normal register accesses */ | |
6d0f6bcf | 348 | #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
d126bfbd WD |
349 | |
350 | /* Offset for alternate registers */ | |
6d0f6bcf | 351 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 |
d126bfbd WD |
352 | |
353 | /*----------------------------------------------------------------------- | |
354 | * | |
355 | *----------------------------------------------------------------------- | |
356 | * | |
357 | */ | |
6d0f6bcf | 358 | #define CONFIG_SYS_DER 0 |
d126bfbd WD |
359 | |
360 | /* | |
361 | * Init Memory Controller: | |
362 | * | |
363 | * BR0/1 and OR0/1 (FLASH) | |
364 | */ | |
365 | ||
366 | #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ | |
71f95118 | 367 | #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */ |
d126bfbd WD |
368 | |
369 | /* used to re-map FLASH both when starting from SRAM or FLASH: | |
370 | * restrict access enough to keep SRAM working (if any) | |
371 | * but not too much to meddle with FLASH accesses | |
372 | */ | |
6d0f6bcf JCPV |
373 | #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
374 | #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ | |
d126bfbd WD |
375 | |
376 | /* | |
377 | * FLASH timing: | |
378 | */ | |
6d0f6bcf | 379 | #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ |
d126bfbd | 380 | OR_SCY_3_CLK | OR_EHTR | OR_BI) |
d126bfbd | 381 | |
6d0f6bcf JCPV |
382 | #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
383 | #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) | |
384 | #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) | |
d126bfbd | 385 | |
6d0f6bcf JCPV |
386 | #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP |
387 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM | |
388 | #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) | |
d126bfbd WD |
389 | |
390 | /* | |
391 | * BR2/3 and OR2/3 (SDRAM) | |
392 | * | |
393 | */ | |
394 | #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ | |
395 | #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ | |
396 | #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ | |
397 | ||
398 | /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ | |
6d0f6bcf | 399 | #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 |
d126bfbd | 400 | |
6d0f6bcf JCPV |
401 | #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) |
402 | #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
d126bfbd WD |
403 | |
404 | #ifndef CONFIG_CAN_DRIVER | |
6d0f6bcf JCPV |
405 | #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM |
406 | #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
d126bfbd | 407 | #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ |
6d0f6bcf JCPV |
408 | #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ |
409 | #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ | |
410 | #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) | |
411 | #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ | |
d126bfbd WD |
412 | BR_PS_8 | BR_MS_UPMB | BR_V ) |
413 | #endif /* CONFIG_CAN_DRIVER */ | |
414 | ||
415 | /* | |
416 | * Memory Periodic Timer Prescaler | |
417 | * | |
418 | * The Divider for PTA (refresh timer) configuration is based on an | |
419 | * example SDRAM configuration (64 MBit, one bank). The adjustment to | |
420 | * the number of chip selects (NCS) and the actually needed refresh | |
421 | * rate is done by setting MPTPR. | |
422 | * | |
423 | * PTA is calculated from | |
424 | * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) | |
425 | * | |
426 | * gclk CPU clock (not bus clock!) | |
427 | * Trefresh Refresh cycle * 4 (four word bursts used) | |
428 | * | |
429 | * 4096 Rows from SDRAM example configuration | |
430 | * 1000 factor s -> ms | |
431 | * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration | |
432 | * 4 Number of refresh cycles per period | |
433 | * 64 Refresh cycle in ms per number of rows | |
434 | * -------------------------------------------- | |
435 | * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 | |
436 | * | |
73a8b27c WD |
437 | * 50 MHz => 50.000.000 / Divider = 98 |
438 | * 66 Mhz => 66.000.000 / Divider = 129 | |
439 | * 80 Mhz => 80.000.000 / Divider = 156 | |
440 | * 100 Mhz => 100.000.000 / Divider = 195 | |
d126bfbd | 441 | */ |
e9132ea9 | 442 | |
6d0f6bcf JCPV |
443 | #define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) |
444 | #define CONFIG_SYS_MAMR_PTA 98 | |
d126bfbd WD |
445 | |
446 | /* | |
447 | * For 16 MBit, refresh rates could be 31.3 us | |
448 | * (= 64 ms / 2K = 125 / quad bursts). | |
449 | * For a simpler initialization, 15.6 us is used instead. | |
450 | * | |
6d0f6bcf JCPV |
451 | * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks |
452 | * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank | |
d126bfbd | 453 | */ |
6d0f6bcf JCPV |
454 | #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ |
455 | #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ | |
d126bfbd WD |
456 | |
457 | /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ | |
6d0f6bcf JCPV |
458 | #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ |
459 | #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ | |
d126bfbd WD |
460 | |
461 | /* | |
462 | * MAMR settings for SDRAM | |
463 | */ | |
464 | ||
465 | /* 8 column SDRAM */ | |
6d0f6bcf | 466 | #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
d126bfbd WD |
467 | MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ |
468 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
469 | /* 9 column SDRAM */ | |
6d0f6bcf | 470 | #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
d126bfbd WD |
471 | MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ |
472 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
473 | ||
d126bfbd WD |
474 | #define CONFIG_SCC1_ENET |
475 | #define CONFIG_FEC_ENET | |
48690d80 | 476 | #define CONFIG_ETHPRIME "SCC" |
d126bfbd | 477 | |
7026ead0 HS |
478 | /* pass open firmware flat tree */ |
479 | #define CONFIG_OF_LIBFDT 1 | |
480 | #define CONFIG_OF_BOARD_SETUP 1 | |
481 | #define CONFIG_HWCONFIG 1 | |
482 | ||
d126bfbd | 483 | #endif /* __CONFIG_H */ |