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aebf00fc MS |
1 | /* |
2 | * (C) Copyright 2007 | |
3 | * Michael Schwingen, michael@schwingen.org | |
4 | * | |
5 | * Configuration settings for the AcTux-2 board. | |
6 | * | |
7 | * See file CREDITS for list of people who contributed to this | |
8 | * project. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of | |
13 | * the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | * MA 02111-1307 USA | |
24 | */ | |
25 | ||
26 | #ifndef __CONFIG_H | |
27 | #define __CONFIG_H | |
28 | ||
29 | #define CONFIG_IXP425 1 | |
30 | #define CONFIG_ACTUX2 1 | |
31 | ||
32 | #define CONFIG_DISPLAY_CPUINFO 1 | |
33 | #define CONFIG_DISPLAY_BOARDINFO 1 | |
34 | ||
930590f3 | 35 | #define CONFIG_IXP_SERIAL |
6d0f6bcf | 36 | #define CONFIG_SYS_IXP425_CONSOLE IXP425_UART2 |
aebf00fc MS |
37 | #define CONFIG_BAUDRATE 115200 |
38 | #define CONFIG_BOOTDELAY 5 | |
39 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ | |
40 | ||
41 | /*************************************************************** | |
42 | * U-boot generic defines start here. | |
43 | ***************************************************************/ | |
44 | #undef CONFIG_USE_IRQ | |
45 | ||
46 | /* Size of malloc() pool */ | |
6d0f6bcf | 47 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) |
aebf00fc | 48 | /* size in bytes reserved for initial data */ |
6d0f6bcf | 49 | #define CONFIG_SYS_GBL_DATA_SIZE 128 |
aebf00fc MS |
50 | |
51 | /* allow to overwrite serial and ethaddr */ | |
52 | #define CONFIG_ENV_OVERWRITE | |
53 | ||
54 | /* Command line configuration. */ | |
55 | #include <config_cmd_default.h> | |
56 | ||
57 | #define CONFIG_CMD_ELF | |
58 | #undef CONFIG_CMD_PCI | |
59 | #undef CONFIG_PCI | |
60 | ||
61 | #define CONFIG_BOOTCOMMAND "run boot_flash" | |
62 | /* enable passing of ATAGs */ | |
63 | #define CONFIG_CMDLINE_TAG 1 | |
64 | #define CONFIG_SETUP_MEMORY_TAGS 1 | |
65 | #define CONFIG_INITRD_TAG 1 | |
66 | #define CONFIG_REVISION_TAG 1 | |
67 | ||
68 | #if defined(CONFIG_CMD_KGDB) | |
69 | # define CONFIG_KGDB_BAUDRATE 230400 | |
70 | /* which serial port to use */ | |
71 | # define CONFIG_KGDB_SER_INDEX 1 | |
72 | #endif | |
73 | ||
74 | /* Miscellaneous configurable options */ | |
6d0f6bcf JCPV |
75 | #define CONFIG_SYS_LONGHELP |
76 | #define CONFIG_SYS_PROMPT "=> " | |
aebf00fc | 77 | /* Console I/O Buffer Size */ |
6d0f6bcf | 78 | #define CONFIG_SYS_CBSIZE 256 |
aebf00fc | 79 | /* Print Buffer Size */ |
6d0f6bcf | 80 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
aebf00fc | 81 | /* max number of command args */ |
6d0f6bcf | 82 | #define CONFIG_SYS_MAXARGS 16 |
aebf00fc | 83 | /* Boot Argument Buffer Size */ |
6d0f6bcf | 84 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
aebf00fc | 85 | |
6d0f6bcf JCPV |
86 | #define CONFIG_SYS_MEMTEST_START 0x00400000 |
87 | #define CONFIG_SYS_MEMTEST_END 0x00800000 | |
aebf00fc | 88 | |
aebf00fc | 89 | /* spec says 66.666 MHz, but it appears to be 33 */ |
6d0f6bcf | 90 | #define CONFIG_SYS_HZ 3333333 |
aebf00fc MS |
91 | |
92 | /* default load address */ | |
6d0f6bcf | 93 | #define CONFIG_SYS_LOAD_ADDR 0x00010000 |
aebf00fc MS |
94 | |
95 | /* valid baudrates */ | |
6d0f6bcf | 96 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ |
aebf00fc MS |
97 | 115200, 230400 } |
98 | #define CONFIG_SERIAL_RTS_ACTIVE 1 | |
99 | ||
100 | /* | |
101 | * Stack sizes | |
102 | * The stack sizes are set up in start.S using the settings below | |
103 | */ | |
104 | #define CONFIG_STACKSIZE (128*1024) /* regular stack */ | |
105 | #ifdef CONFIG_USE_IRQ | |
106 | # define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ | |
107 | # define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ | |
108 | #endif | |
109 | ||
110 | /* Expansion bus settings */ | |
6d0f6bcf | 111 | #define CONFIG_SYS_EXP_CS0 0xbd113042 |
aebf00fc MS |
112 | |
113 | /* SDRAM settings */ | |
114 | #define CONFIG_NR_DRAM_BANKS 1 | |
115 | #define PHYS_SDRAM_1 0x00000000 | |
6d0f6bcf | 116 | #define CONFIG_SYS_DRAM_BASE 0x00000000 |
aebf00fc MS |
117 | |
118 | /* 16MB SDRAM */ | |
6d0f6bcf | 119 | #define CONFIG_SYS_SDR_CONFIG 0x3A |
aebf00fc | 120 | #define PHYS_SDRAM_1_SIZE 0x01000000 |
6d0f6bcf JCPV |
121 | #define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a |
122 | #define CONFIG_SYS_SDR_MODE_CONFIG 0x1 | |
123 | #define CONFIG_SYS_DRAM_SIZE 0x01000000 | |
aebf00fc MS |
124 | |
125 | /* FLASH organization */ | |
6d0f6bcf | 126 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
aebf00fc | 127 | /* max number of sectors on one chip */ |
6d0f6bcf | 128 | #define CONFIG_SYS_MAX_FLASH_SECT 140 |
aebf00fc | 129 | #define PHYS_FLASH_1 0x50000000 |
6d0f6bcf | 130 | #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1 } |
aebf00fc | 131 | |
6d0f6bcf JCPV |
132 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
133 | #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 | |
134 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) | |
aebf00fc MS |
135 | |
136 | /* Use common CFI driver */ | |
6d0f6bcf | 137 | #define CONFIG_SYS_FLASH_CFI |
00b1883a | 138 | #define CONFIG_FLASH_CFI_DRIVER |
aebf00fc | 139 | /* no byte writes on IXP4xx */ |
6d0f6bcf | 140 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
aebf00fc MS |
141 | |
142 | /* print 'E' for empty sector on flinfo */ | |
6d0f6bcf | 143 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
aebf00fc MS |
144 | |
145 | /* Ethernet */ | |
146 | ||
147 | /* include IXP4xx NPE support */ | |
148 | #define CONFIG_IXP4XX_NPE 1 | |
aebf00fc MS |
149 | #define CONFIG_NET_MULTI 1 |
150 | /* NPE0 PHY address */ | |
151 | #define CONFIG_PHY_ADDR 0x00 | |
152 | /* MII PHY management */ | |
153 | #define CONFIG_MII 1 | |
154 | /* Number of ethernet rx buffers & descriptors */ | |
6d0f6bcf | 155 | #define CONFIG_SYS_RX_ETH_BUFFER 16 |
aebf00fc MS |
156 | #define CONFIG_RESET_PHY_R 1 |
157 | /* ethernet switch connected to MII port */ | |
158 | #define CONFIG_MII_ETHSWITCH 1 | |
159 | ||
160 | #define CONFIG_CMD_DHCP | |
161 | #define CONFIG_CMD_NET | |
162 | #define CONFIG_CMD_MII | |
163 | #define CONFIG_CMD_PING | |
164 | #undef CONFIG_CMD_NFS | |
165 | ||
166 | /* BOOTP options */ | |
167 | #define CONFIG_BOOTP_BOOTFILESIZE | |
168 | #define CONFIG_BOOTP_BOOTPATH | |
169 | #define CONFIG_BOOTP_GATEWAY | |
170 | #define CONFIG_BOOTP_HOSTNAME | |
171 | ||
172 | /* Cache Configuration */ | |
6d0f6bcf | 173 | #define CONFIG_SYS_CACHELINE_SIZE 32 |
aebf00fc MS |
174 | |
175 | /* | |
176 | * environment organization: | |
177 | * one flash sector, embedded in uboot area (bottom bootblock flash) | |
178 | */ | |
5a1aceb0 | 179 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
180 | #define CONFIG_ENV_SIZE 0x2000 |
181 | #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x4000) | |
6d0f6bcf | 182 | #define CONFIG_SYS_USE_PPCENV 1 |
aebf00fc MS |
183 | |
184 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
b4e2f89d | 185 | "npe_ucode=50040000\0" \ |
aebf00fc MS |
186 | "mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \ |
187 | "kerneladdr=50050000\0" \ | |
188 | "rootaddr=50170000\0" \ | |
189 | "loadaddr=10000\0" \ | |
190 | "updateboot_ser=mw.b 10000 ff 40000;" \ | |
191 | " loady ${loadaddr};" \ | |
192 | " run eraseboot writeboot\0" \ | |
193 | "updateboot_net=mw.b 10000 ff 40000;" \ | |
194 | " tftp ${loadaddr} u-boot.bin;" \ | |
195 | " run eraseboot writeboot\0" \ | |
196 | "eraseboot=protect off 50000000 50003fff;" \ | |
197 | " protect off 50006000 5003ffff;" \ | |
198 | " erase 50000000 50003fff;" \ | |
199 | " erase 50006000 5003ffff\0" \ | |
200 | "writeboot=cp.b 10000 50000000 4000;" \ | |
201 | " cp.b 16000 50006000 3a000\0" \ | |
202 | "eraseenv=protect off 50004000 50005fff;" \ | |
203 | " erase 50004000 50005fff\0" \ | |
204 | "updateroot=tftp ${loadaddr} ${rootfile};" \ | |
205 | " era ${rootaddr} +${filesize};" \ | |
206 | " cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \ | |
207 | "updatekern=tftp ${loadaddr} ${kernelfile};" \ | |
208 | " era ${kerneladdr} +${filesize};" \ | |
209 | " cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \ | |
210 | "flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \ | |
211 | " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ | |
212 | "netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \ | |
213 | " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ | |
214 | "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ | |
215 | "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ | |
216 | "boot_flash=run flashargs addtty addeth;" \ | |
217 | " bootm ${kerneladdr}\0" \ | |
218 | "boot_net=run netargs addtty addeth;" \ | |
219 | " tftpboot ${loadaddr} ${kernelfile};" \ | |
220 | " bootm\0" | |
221 | ||
222 | #endif /* __CONFIG_H */ |