]>
Commit | Line | Data |
---|---|---|
8f79e4c2 | 1 | /* |
5078cce8 | 2 | * (C) Copyright 2003-2006 |
8f79e4c2 WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
5 | * (C) Copyright 2004-2005 | |
6 | * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de | |
7 | * | |
3765b3e7 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
8f79e4c2 WD |
9 | */ |
10 | ||
11 | #ifndef __CONFIG_H | |
12 | #define __CONFIG_H | |
13 | ||
14 | /* | |
15 | * High Level Configuration Options | |
16 | * (easy to change) | |
17 | */ | |
18 | ||
b2a6dfe4 | 19 | #define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ |
8f79e4c2 WD |
20 | #define CONFIG_TQM5200 1 /* ... on TQM5200 module */ |
21 | #undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */ | |
22 | #define CONFIG_STK52XX 1 /* ... on a STK52XX base board */ | |
23 | #define CONFIG_STK52XX_REV100 1 /* define for revision 100 baseboards */ | |
24 | #define CONFIG_AEVFIFO 1 | |
6d0f6bcf | 25 | #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ |
8f79e4c2 | 26 | |
2ae18241 WD |
27 | /* |
28 | * Valid values for CONFIG_SYS_TEXT_BASE are: | |
29 | * 0xFC000000 boot low (standard configuration with room for | |
30 | * max 64 MByte Flash ROM) | |
31 | * 0xFFF00000 boot high (for a backup copy of U-Boot) | |
32 | * 0x00100000 boot from RAM (for testing only) | |
33 | */ | |
34 | #ifndef CONFIG_SYS_TEXT_BASE | |
35 | #define CONFIG_SYS_TEXT_BASE 0xFC000000 | |
36 | #endif | |
37 | ||
31d82672 BB |
38 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
39 | ||
8f79e4c2 WD |
40 | /* |
41 | * Serial console configuration | |
42 | */ | |
43 | #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ | |
44 | #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ | |
6d0f6bcf | 45 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
8f79e4c2 WD |
46 | |
47 | /* | |
48 | * PCI Mapping: | |
49 | * 0x40000000 - 0x4fffffff - PCI Memory | |
50 | * 0x50000000 - 0x50ffffff - PCI IO Space | |
51 | */ | |
52 | #ifdef CONFIG_AEVFIFO | |
53 | #define CONFIG_PCI 1 | |
54 | #define CONFIG_PCI_PNP 1 | |
55 | /* #define CONFIG_PCI_SCAN_SHOW 1 */ | |
f33fca22 | 56 | #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 |
8f79e4c2 WD |
57 | |
58 | #define CONFIG_PCI_MEM_BUS 0x40000000 | |
59 | #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS | |
60 | #define CONFIG_PCI_MEM_SIZE 0x10000000 | |
61 | ||
62 | #define CONFIG_PCI_IO_BUS 0x50000000 | |
63 | #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS | |
64 | #define CONFIG_PCI_IO_SIZE 0x01000000 | |
65 | ||
8f79e4c2 | 66 | #define CONFIG_EEPRO100 1 |
6d0f6bcf | 67 | #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ |
8f79e4c2 WD |
68 | #define CONFIG_NS8382X 1 |
69 | #endif /* CONFIG_AEVFIFO */ | |
70 | ||
71 | /* Partitions */ | |
72 | #define CONFIG_MAC_PARTITION | |
73 | #define CONFIG_DOS_PARTITION | |
74 | #define CONFIG_ISO_PARTITION | |
75 | ||
76 | /* POST support */ | |
6d0f6bcf JCPV |
77 | #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ |
78 | CONFIG_SYS_POST_CPU | \ | |
79 | CONFIG_SYS_POST_I2C) | |
8f79e4c2 WD |
80 | |
81 | #ifdef CONFIG_POST | |
8f79e4c2 WD |
82 | /* preserve space for the post_word at end of on-chip SRAM */ |
83 | #define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4 | |
8f79e4c2 WD |
84 | #endif |
85 | ||
0b361c91 | 86 | |
80ff4f99 JL |
87 | /* |
88 | * BOOTP options | |
89 | */ | |
90 | #define CONFIG_BOOTP_BOOTFILESIZE | |
91 | #define CONFIG_BOOTP_BOOTPATH | |
92 | #define CONFIG_BOOTP_GATEWAY | |
93 | #define CONFIG_BOOTP_HOSTNAME | |
94 | ||
95 | ||
8f79e4c2 | 96 | /* |
0b361c91 | 97 | * Command line configuration. |
8f79e4c2 | 98 | */ |
0b361c91 JL |
99 | #include <config_cmd_default.h> |
100 | ||
101 | #define CONFIG_CMD_ASKENV | |
102 | #define CONFIG_CMD_DATE | |
103 | #define CONFIG_CMD_DHCP | |
104 | #define CONFIG_CMD_ECHO | |
105 | #define CONFIG_CMD_EEPROM | |
106 | #define CONFIG_CMD_I2C | |
107 | #define CONFIG_CMD_MII | |
108 | #define CONFIG_CMD_NFS | |
109 | #define CONFIG_CMD_PCI | |
110 | #define CONFIG_CMD_PING | |
0b361c91 JL |
111 | #define CONFIG_CMD_REGINFO |
112 | #define CONFIG_CMD_SNTP | |
113 | ||
af075ee9 JL |
114 | #ifdef CONFIG_POST |
115 | #define CONFIG_CMD_DIAG | |
116 | #endif | |
117 | ||
8f79e4c2 WD |
118 | |
119 | #define CONFIG_TIMESTAMP /* display image timestamps */ | |
120 | ||
14d0a02a | 121 | #if (CONFIG_SYS_TEXT_BASE == 0xFC000000) /* Boot low */ |
6d0f6bcf | 122 | # define CONFIG_SYS_LOWBOOT 1 |
8f79e4c2 WD |
123 | #endif |
124 | ||
125 | /* | |
126 | * Autobooting | |
127 | */ | |
128 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
129 | ||
130 | #define CONFIG_PREBOOT "echo;" \ | |
32bf3d14 | 131 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
8f79e4c2 WD |
132 | "echo" |
133 | ||
134 | #undef CONFIG_BOOTARGS | |
135 | ||
136 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
137 | "netdev=eth0\0" \ | |
138 | "rootpath=/opt/eldk/ppc_6xx\0" \ | |
139 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
140 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
fe126d8b WD |
141 | "nfsroot=${serverip}:${rootpath} " \ |
142 | "console=ttyS0,${baudrate}\0" \ | |
143 | "addip=setenv bootargs ${bootargs} " \ | |
144 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
145 | ":${hostname}:${netdev}:off panic=1\0" \ | |
8f79e4c2 | 146 | "flash_self=run ramargs addip;" \ |
fe126d8b | 147 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
8f79e4c2 | 148 | "flash_nfs=run nfsargs addip;" \ |
fe126d8b WD |
149 | "bootm ${kernel_addr}\0" \ |
150 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ | |
8f79e4c2 | 151 | "bootfile=/tftpboot/tqm5200/uImage\0" \ |
fe126d8b | 152 | "load=tftp 200000 ${u-boot}\0" \ |
8f79e4c2 WD |
153 | "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \ |
154 | "update=protect off FC000000 FC05FFFF;" \ | |
155 | "erase FC000000 FC05FFFF;" \ | |
fe126d8b | 156 | "cp.b 200000 FC000000 ${filesize};" \ |
8f79e4c2 WD |
157 | "protect on FC000000 FC05FFFF\0" \ |
158 | "" | |
159 | ||
160 | #define CONFIG_BOOTCOMMAND "run net_nfs" | |
161 | ||
162 | /* | |
163 | * IPB Bus clocking configuration. | |
164 | */ | |
6d0f6bcf | 165 | #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ |
8f79e4c2 | 166 | |
6d0f6bcf | 167 | #if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) |
8f79e4c2 WD |
168 | /* |
169 | * PCI Bus clocking configuration | |
170 | * | |
171 | * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if | |
6d0f6bcf | 172 | * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock |
c99512d6 | 173 | * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz. |
8f79e4c2 | 174 | */ |
6d0f6bcf | 175 | #define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */ |
8f79e4c2 WD |
176 | #endif |
177 | ||
178 | /* | |
179 | * I2C configuration | |
180 | */ | |
181 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
182 | #ifdef CONFIG_TQM5200_REV100 | |
6d0f6bcf | 183 | #define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */ |
8f79e4c2 | 184 | #else |
6d0f6bcf | 185 | #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 for all other revs */ |
8f79e4c2 WD |
186 | #endif |
187 | ||
188 | /* | |
189 | * I2C clock frequency | |
190 | * | |
191 | * Please notice, that the resulting clock frequency could differ from the | |
192 | * configured value. This is because the I2C clock is derived from system | |
193 | * clock over a frequency divider with only a few divider values. U-boot | |
6d0f6bcf | 194 | * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated |
8f79e4c2 WD |
195 | * approximation allways lies below the configured value, never above. |
196 | */ | |
6d0f6bcf JCPV |
197 | #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ |
198 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
8f79e4c2 WD |
199 | |
200 | /* | |
201 | * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work | |
202 | * also). For other EEPROMs configuration should be verified. On Mini-FAP the | |
203 | * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the | |
204 | * same configuration could be used. | |
205 | */ | |
6d0f6bcf JCPV |
206 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ |
207 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
208 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ | |
209 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 | |
8f79e4c2 WD |
210 | |
211 | /* | |
212 | * Flash configuration | |
213 | */ | |
14d0a02a | 214 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE /* 0xFC000000 */ |
8f79e4c2 WD |
215 | |
216 | /* use CFI flash driver if no module variant is spezified */ | |
6d0f6bcf | 217 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
00b1883a | 218 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ |
6d0f6bcf JCPV |
219 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START } |
220 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
221 | #define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */ | |
222 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ | |
223 | #undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */ | |
224 | ||
225 | #if !defined(CONFIG_SYS_LOWBOOT) | |
226 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000) | |
227 | #else /* CONFIG_SYS_LOWBOOT */ | |
228 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000) | |
229 | #endif /* CONFIG_SYS_LOWBOOT */ | |
230 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks | |
8f79e4c2 | 231 | (= chip selects) */ |
6d0f6bcf JCPV |
232 | #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ |
233 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ | |
8f79e4c2 WD |
234 | |
235 | ||
236 | /* | |
237 | * Environment settings | |
238 | */ | |
5a1aceb0 | 239 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
240 | #define CONFIG_ENV_SIZE 0x10000 |
241 | #define CONFIG_ENV_SECT_SIZE 0x20000 | |
242 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) | |
243 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
8f79e4c2 WD |
244 | |
245 | /* | |
246 | * Memory map | |
247 | */ | |
6d0f6bcf JCPV |
248 | #define CONFIG_SYS_MBAR 0xF0000000 |
249 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
250 | #define CONFIG_SYS_DEFAULT_MBAR 0x80000000 | |
8f79e4c2 WD |
251 | |
252 | /* Use ON-Chip SRAM until RAM will be available */ | |
6d0f6bcf | 253 | #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM |
8f79e4c2 WD |
254 | #ifdef CONFIG_POST |
255 | /* preserve space for the post_word at end of on-chip SRAM */ | |
553f0982 | 256 | #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE |
8f79e4c2 | 257 | #else |
553f0982 | 258 | #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE |
8f79e4c2 WD |
259 | #endif |
260 | ||
261 | ||
25ddd1fb | 262 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 263 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
8f79e4c2 | 264 | |
14d0a02a | 265 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf JCPV |
266 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
267 | # define CONFIG_SYS_RAMBOOT 1 | |
8f79e4c2 WD |
268 | #endif |
269 | ||
6d0f6bcf JCPV |
270 | #define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ |
271 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
272 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
8f79e4c2 WD |
273 | |
274 | /* | |
275 | * Ethernet configuration | |
276 | */ | |
277 | #define CONFIG_MPC5xxx_FEC 1 | |
90964353 | 278 | #define CONFIG_MPC5xxx_FEC_MII100 |
8f79e4c2 | 279 | /* |
90964353 | 280 | * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb |
8f79e4c2 | 281 | */ |
90964353 | 282 | /* #define CONFIG_MPC5xxx_FEC_MII10 */ |
8f79e4c2 WD |
283 | #define CONFIG_PHY_ADDR 0x00 |
284 | ||
285 | /* | |
286 | * GPIO configuration | |
287 | * | |
288 | * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1): | |
289 | * Bit 0 (mask: 0x80000000): 1 | |
290 | * use ALT CAN position: Bits 2-3 (mask: 0x30000000): | |
291 | * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting. | |
292 | * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1. | |
293 | * Use for REV200 STK52XX boards. Do not use with REV100 modules | |
294 | * (because, there I2C1 is used as I2C bus) | |
295 | * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100 | |
296 | * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030) | |
297 | * 000 -> All PSC2 pins are GIOPs | |
298 | * 001 -> CAN1/2 on PSC2 pins | |
299 | * Use for REV100 STK52xx boards | |
300 | * use PSC6: | |
301 | * on STK52xx: | |
302 | * use as UART. Pins PSC6_0 to PSC6_3 are used. | |
303 | * Bits 9:11 (mask: 0x00700000): | |
304 | * 101 -> PSC6 : Extended POST test is not available | |
305 | * on MINI-FAP and TQM5200_IB: | |
306 | * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000): | |
307 | * 000 -> PSC6 could not be used as UART, CODEC or IrDA | |
308 | * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST | |
309 | * tests. | |
310 | */ | |
6d0f6bcf | 311 | #define CONFIG_SYS_GPS_PORT_CONFIG 0x81500014 |
8f79e4c2 WD |
312 | |
313 | /* | |
314 | * RTC configuration | |
315 | */ | |
316 | #define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ | |
317 | ||
318 | /* | |
319 | * Miscellaneous configurable options | |
320 | */ | |
6d0f6bcf | 321 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
0b361c91 | 322 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 323 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
8f79e4c2 | 324 | #else |
6d0f6bcf | 325 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
8f79e4c2 | 326 | #endif |
6d0f6bcf JCPV |
327 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
328 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
329 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
8f79e4c2 WD |
330 | |
331 | /* Enable an alternate, more extensive memory test */ | |
6d0f6bcf | 332 | #define CONFIG_SYS_ALT_MEMTEST |
8f79e4c2 | 333 | |
6d0f6bcf JCPV |
334 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
335 | #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ | |
8f79e4c2 | 336 | |
6d0f6bcf | 337 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
8f79e4c2 | 338 | |
6d0f6bcf | 339 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
0b361c91 | 340 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 341 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
0b361c91 JL |
342 | #endif |
343 | ||
8f79e4c2 | 344 | /* |
80ff4f99 | 345 | * Enable loopw command. |
8f79e4c2 WD |
346 | */ |
347 | #define CONFIG_LOOPW | |
348 | ||
349 | /* | |
350 | * Various low-level settings | |
351 | */ | |
6d0f6bcf JCPV |
352 | #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI |
353 | #define CONFIG_SYS_HID0_FINAL HID0_ICE | |
8f79e4c2 | 354 | |
6d0f6bcf JCPV |
355 | #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE |
356 | #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE | |
357 | #ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 | |
358 | #define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */ | |
8f79e4c2 | 359 | #else |
6d0f6bcf | 360 | #define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */ |
8f79e4c2 | 361 | #endif |
6d0f6bcf JCPV |
362 | #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE |
363 | #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE | |
8f79e4c2 | 364 | |
8f79e4c2 | 365 | #define CONFIG_LAST_STAGE_INIT |
8f79e4c2 WD |
366 | |
367 | /* | |
368 | * SRAM - Do not map below 2 GB in address space, because this area is used | |
369 | * for SDRAM autosizing. | |
370 | */ | |
6d0f6bcf JCPV |
371 | #define CONFIG_SYS_CS2_START 0xE5000000 |
372 | #define CONFIG_SYS_CS2_SIZE 0x80000 /* 512 kByte */ | |
373 | #define CONFIG_SYS_CS2_CFG 0x0004D930 | |
8f79e4c2 WD |
374 | |
375 | /* | |
376 | * Grafic controller - Do not map below 2 GB in address space, because this | |
377 | * area is used for SDRAM autosizing. | |
378 | */ | |
379 | #define SM501_FB_BASE 0xE0000000 | |
6d0f6bcf JCPV |
380 | #define CONFIG_SYS_CS1_START (SM501_FB_BASE) |
381 | #define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */ | |
382 | #define CONFIG_SYS_CS1_CFG 0x8F48FF70 | |
383 | #define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000 | |
8f79e4c2 | 384 | |
6d0f6bcf JCPV |
385 | #define CONFIG_SYS_CS_BURST 0x00000000 |
386 | #define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */ | |
8f79e4c2 | 387 | |
6d0f6bcf | 388 | #define CONFIG_SYS_RESET_ADDRESS 0xff000000 |
8f79e4c2 WD |
389 | |
390 | #endif /* __CONFIG_H */ |