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899620c2 | 1 | /* |
9462732a | 2 | * (C) Copyright 2006-2008 |
899620c2 SR |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #ifndef __CONFIG_H | |
25 | #define __CONFIG_H | |
26 | ||
27 | /*----------------------------------------------------------------------- | |
28 | * High Level Configuration Options | |
29 | *----------------------------------------------------------------------*/ | |
30 | #define CONFIG_ALPR 1 /* Board is ebony */ | |
31 | #define CONFIG_440GX 1 /* Specifc GX support */ | |
efa35cf1 | 32 | #define CONFIG_440 1 /* ... PPC440 family */ |
899620c2 SR |
33 | #define CONFIG_4xx 1 /* ... PPC4xx family */ |
34 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ | |
1c2ce226 | 35 | #define CONFIG_LAST_STAGE_INIT 1 /* call last_stage_init() */ |
1c2ce226 | 36 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ |
511e4f9e | 37 | #define CONFIG_4xx_DCACHE /* Enable i- and d-cache */ |
899620c2 SR |
38 | |
39 | /*----------------------------------------------------------------------- | |
40 | * Base addresses -- Note these are effective addresses where the | |
41 | * actual resources get mapped (not physical addresses) | |
42 | *----------------------------------------------------------------------*/ | |
1c2ce226 SR |
43 | #define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ |
44 | #define CFG_FLASH_BASE 0xffe00000 /* start of FLASH */ | |
45 | #define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */ | |
46 | #define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ | |
47 | #define CFG_PCI_MEMSIZE 0x40000000 /* size of mapped pci memory */ | |
48 | #define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ | |
49 | #define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */ | |
50 | #define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ | |
51 | #define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 | |
52 | #define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 | |
53 | #define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 | |
899620c2 SR |
54 | |
55 | ||
56 | #define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08300000) | |
57 | #define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000) | |
58 | ||
59 | /*----------------------------------------------------------------------- | |
60 | * Initial RAM & stack pointer (placed in internal SRAM) | |
61 | *----------------------------------------------------------------------*/ | |
62 | #define CFG_TEMP_STACK_OCM 1 | |
63 | #define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE | |
64 | #define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */ | |
65 | #define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ | |
66 | #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ | |
67 | ||
68 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
69 | #define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) | |
70 | #define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR | |
71 | ||
72 | #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ | |
73 | #define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ | |
74 | ||
75 | /*----------------------------------------------------------------------- | |
76 | * Serial Port | |
77 | *----------------------------------------------------------------------*/ | |
78 | #undef CFG_EXT_SERIAL_CLOCK | |
79 | #define CONFIG_BAUDRATE 115200 | |
80 | #define CONFIG_UART1_CONSOLE /* define for uart1 as console */ | |
81 | ||
82 | #define CFG_BAUDRATE_TABLE \ | |
83 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
84 | ||
899620c2 SR |
85 | /*----------------------------------------------------------------------- |
86 | * FLASH related | |
87 | *----------------------------------------------------------------------*/ | |
1c2ce226 | 88 | #define CFG_FLASH_CFI 1 /* The flash is CFI compatible */ |
00b1883a | 89 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use common CFI driver */ |
899620c2 | 90 | #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
1c2ce226 SR |
91 | #define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ |
92 | #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ | |
899620c2 | 93 | #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
1c2ce226 | 94 | #define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ |
899620c2 SR |
95 | |
96 | #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ | |
97 | ||
1636d1c8 | 98 | #define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ |
899620c2 SR |
99 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) |
100 | #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ | |
101 | ||
102 | /* Address and size of Redundant Environment Sector */ | |
103 | #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) | |
104 | #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) | |
105 | ||
106 | /*----------------------------------------------------------------------- | |
107 | * DDR SDRAM | |
108 | *----------------------------------------------------------------------*/ | |
109 | #undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */ | |
110 | #define CONFIG_SDRAM_BANK0 1 /* init onboard DDR SDRAM bank 0 */ | |
111 | #undef CONFIG_SDRAM_ECC /* enable ECC support */ | |
112 | #define CFG_SDRAM_TABLE { \ | |
113 | {(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \ | |
114 | {(64 << 20), 12, 0x00082001}} /* 64MB mode 2, 12x9(4) */ | |
115 | ||
116 | /*----------------------------------------------------------------------- | |
117 | * I2C | |
118 | *----------------------------------------------------------------------*/ | |
119 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
120 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
121 | #define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ | |
122 | #define CFG_I2C_SLAVE 0x7F | |
123 | #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ | |
124 | ||
125 | /*----------------------------------------------------------------------- | |
126 | * I2C EEPROM (PCF8594C) | |
127 | *----------------------------------------------------------------------*/ | |
128 | #define CFG_I2C_EEPROM_ADDR 0x54 /* EEPROM PCF8594C */ | |
129 | #define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ | |
130 | /* mask of address bits that overflow into the "EEPROM chip address" */ | |
131 | #define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 | |
132 | #define CFG_EEPROM_PAGE_WRITE_BITS 3 /* The Philips PCF8594C has */ | |
133 | /* 8 byte page write mode using */ | |
134 | /* last 3 bits of the address */ | |
135 | #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 40 /* and takes up to 40 msec */ | |
136 | #define CFG_EEPROM_PAGE_WRITE_ENABLE | |
137 | ||
138 | #define CONFIG_PREBOOT "echo;" \ | |
6304430e | 139 | "echo Type \"run kernelx\" to boot the system;" \ |
899620c2 SR |
140 | "echo" |
141 | ||
142 | #undef CONFIG_BOOTARGS | |
143 | ||
144 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
1c2ce226 | 145 | "netdev=eth3\0" \ |
899620c2 | 146 | "hostname=alpr\0" \ |
9462732a SR |
147 | "fdt_file=alpr/alpr.dtb\0" \ |
148 | "fdt_addr=400000\0" \ | |
899620c2 | 149 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
6304430e | 150 | "nfsroot=${serverip}:${rootpath} ${init}\0" \ |
899620c2 SR |
151 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
152 | "addip=setenv bootargs ${bootargs} " \ | |
153 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
154 | ":${hostname}:${netdev}:off panic=1\0" \ | |
1c2ce226 SR |
155 | "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate} " \ |
156 | "mem=193M\0" \ | |
899620c2 SR |
157 | "flash_nfs=run nfsargs addip addtty;" \ |
158 | "bootm ${kernel_addr}\0" \ | |
159 | "flash_self=run ramargs addip addtty;" \ | |
160 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ | |
161 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ | |
162 | "bootm\0" \ | |
9462732a SR |
163 | "net_nfs_fdt=tftp 200000 ${bootfile};" \ |
164 | "tftp ${fdt_addr} ${fdt_file};" \ | |
165 | "run nfsargs addip addtty;" \ | |
166 | "bootm 200000 - ${fdt_addr}\0" \ | |
1c2ce226 SR |
167 | "rootpath=/opt/projects/alpr/nfs_root\0" \ |
168 | "bootfile=/alpr/uImage\0" \ | |
899620c2 SR |
169 | "kernel_addr=fff00000\0" \ |
170 | "ramdisk_addr=fff10000\0" \ | |
1c2ce226 | 171 | "load=tftp 100000 /alpr/u-boot/u-boot.bin\0" \ |
899620c2 SR |
172 | "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ |
173 | "cp.b 100000 fffc0000 40000;" \ | |
174 | "setenv filesize;saveenv\0" \ | |
d8ab58b2 | 175 | "upd=run load update\0" \ |
f16c1da9 SR |
176 | "ethprime=ppc_4xx_eth3\0" \ |
177 | "ethact=ppc_4xx_eth3\0" \ | |
178 | "autoload=no\0" \ | |
179 | "ipconfig=dhcp;setenv serverip 11.0.0.152\0" \ | |
f16c1da9 SR |
180 | "load_fpga=fpga load 0 ffe00000 10dd9a\0" \ |
181 | "mtdargs=setenv bootargs root=/dev/mtdblock6 rw " \ | |
182 | "rootfstype=jffs2 init=/sbin/init\0" \ | |
183 | "kernel1_mtd=nand read 200000 0 200000;run mtdargs addip addtty"\ | |
184 | ";bootm 200000\0" \ | |
185 | "kernel2_mtd=nand read 200000 200000 200000;run mtdargs addip " \ | |
186 | "addtty;bootm 200000\0" \ | |
6304430e SR |
187 | "kernel1=setenv actkernel 'kernel1';run load_fpga " \ |
188 | "kernel1_mtd\0" \ | |
189 | "kernel2=setenv actkernel 'kernel2';run load_fpga " \ | |
190 | "kernel2_mtd\0" \ | |
899620c2 | 191 | "" |
f16c1da9 SR |
192 | |
193 | #define CONFIG_BOOTCOMMAND "run kernel2" | |
899620c2 | 194 | |
1c2ce226 | 195 | #define CONFIG_BOOTDELAY 2 /* autoboot after 5 seconds */ |
899620c2 SR |
196 | |
197 | #define CONFIG_BAUDRATE 115200 | |
198 | ||
199 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
200 | #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
201 | ||
202 | #define CONFIG_MII 1 /* MII PHY management */ | |
203 | #define CONFIG_NET_MULTI 1 | |
204 | #define CONFIG_PHY_ADDR 0x02 /* dummy setting, no EMAC0 used */ | |
205 | #define CONFIG_PHY1_ADDR 0x03 /* dummy setting, no EMAC1 used */ | |
1c2ce226 SR |
206 | #define CONFIG_PHY2_ADDR 0x01 /* PHY address for EMAC2 */ |
207 | #define CONFIG_PHY3_ADDR 0x02 /* PHY address for EMAC3 */ | |
899620c2 SR |
208 | #define CONFIG_HAS_ETH0 |
209 | #define CONFIG_HAS_ETH1 | |
210 | #define CONFIG_HAS_ETH2 | |
211 | #define CONFIG_HAS_ETH3 | |
212 | #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ | |
ec0c2ec7 | 213 | #define CONFIG_M88E1111_PHY 1 /* needed for PHY specific setup*/ |
899620c2 | 214 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ |
5bc528fa SR |
215 | #define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ |
216 | ||
217 | #define CONFIG_NETCONSOLE /* include NetConsole support */ | |
899620c2 | 218 | |
0b361c91 | 219 | |
80ff4f99 JL |
220 | /* |
221 | * BOOTP options | |
222 | */ | |
223 | #define CONFIG_BOOTP_BOOTFILESIZE | |
224 | #define CONFIG_BOOTP_BOOTPATH | |
225 | #define CONFIG_BOOTP_GATEWAY | |
226 | #define CONFIG_BOOTP_HOSTNAME | |
227 | ||
228 | ||
0b361c91 JL |
229 | /* |
230 | * Command line configuration. | |
231 | */ | |
232 | #include <config_cmd_default.h> | |
233 | ||
234 | #define CONFIG_CMD_ASKENV | |
235 | #define CONFIG_CMD_DHCP | |
236 | #define CONFIG_CMD_DIAG | |
237 | #define CONFIG_CMD_EEPROM | |
238 | #define CONFIG_CMD_ELF | |
239 | #define CONFIG_CMD_FPGA | |
240 | #define CONFIG_CMD_I2C | |
241 | #define CONFIG_CMD_IRQ | |
242 | #define CONFIG_CMD_MII | |
243 | #define CONFIG_CMD_NAND | |
244 | #define CONFIG_CMD_NET | |
245 | #define CONFIG_CMD_NFS | |
246 | #define CONFIG_CMD_PCI | |
247 | #define CONFIG_CMD_PING | |
248 | #define CONFIG_CMD_REGINFO | |
249 | ||
899620c2 SR |
250 | |
251 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
252 | ||
253 | /* | |
254 | * Miscellaneous configurable options | |
255 | */ | |
256 | #define CFG_LONGHELP /* undef to save memory */ | |
257 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
0b361c91 | 258 | #if defined(CONFIG_CMD_KGDB) |
899620c2 SR |
259 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
260 | #else | |
261 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
262 | #endif | |
263 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
264 | #define CFG_MAXARGS 16 /* max number of command args */ | |
265 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
266 | ||
6304430e | 267 | #define CFG_ALT_MEMTEST 1 /* Enable more extensive memtest*/ |
899620c2 SR |
268 | #define CFG_MEMTEST_START 0x0400000 /* memtest works on */ |
269 | #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
270 | ||
271 | #define CFG_LOAD_ADDR 0x100000 /* default load address */ | |
272 | #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
273 | ||
274 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
275 | ||
5bc528fa | 276 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
899620c2 | 277 | #define CONFIG_LOOPW 1 /* enable loopw command */ |
1636d1c8 | 278 | #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ |
899620c2 | 279 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ |
1c2ce226 SR |
280 | #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ |
281 | ||
282 | #define CFG_4xx_RESET_TYPE 0x2 /* use chip reset on this board */ | |
899620c2 | 283 | |
899620c2 SR |
284 | /*----------------------------------------------------------------------- |
285 | * PCI stuff | |
286 | *----------------------------------------------------------------------- | |
287 | */ | |
288 | /* General PCI */ | |
289 | #define CONFIG_PCI /* include pci support */ | |
290 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
291 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
292 | #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ | |
1c2ce226 | 293 | #define CONFIG_PCI_BOOTDELAY 1 /* enable pci bootdelay variable*/ |
899620c2 SR |
294 | |
295 | /* Board-specific PCI */ | |
899620c2 SR |
296 | #define CFG_PCI_TARGET_INIT /* let board init pci target */ |
297 | #define CFG_PCI_MASTER_INIT | |
298 | ||
299 | #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ | |
300 | #define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ | |
301 | ||
302 | /*----------------------------------------------------------------------- | |
303 | * FPGA stuff | |
1c2ce226 | 304 | *-----------------------------------------------------------------------*/ |
0133502e MF |
305 | #define CONFIG_FPGA |
306 | #define CONFIG_FPGA_ALTERA | |
307 | #define CONFIG_FPGA_CYCLON2 | |
1c2ce226 SR |
308 | #define CFG_FPGA_CHECK_CTRLC |
309 | #define CFG_FPGA_PROG_FEEDBACK | |
899620c2 SR |
310 | #define CONFIG_FPGA_COUNT 1 /* Ich habe 2 ... aber in |
311 | Reihe geschaltet -> sollte gehen, | |
312 | aufpassen mit Datasize ist jetzt | |
313 | halt doppelt so gross ... Seite 306 | |
314 | ist das mit den multiple Device in PS | |
315 | Mode erklaert ...*/ | |
316 | ||
899620c2 SR |
317 | /* FPGA program pin configuration */ |
318 | #define CFG_GPIO_CLK 18 /* FPGA clk pin (cpu output) */ | |
319 | #define CFG_GPIO_DATA 19 /* FPGA data pin (cpu output) */ | |
320 | #define CFG_GPIO_STATUS 20 /* FPGA status pin (cpu input) */ | |
321 | #define CFG_GPIO_CONFIG 21 /* FPGA CONFIG pin (cpu output) */ | |
322 | #define CFG_GPIO_CON_DON 22 /* FPGA CONFIG_DONE pin (cpu input) */ | |
323 | ||
324 | #define CFG_GPIO_SEL_DPR 14 /* cpu output */ | |
325 | #define CFG_GPIO_SEL_AVR 15 /* cpu output */ | |
326 | #define CFG_GPIO_PROG_EN 23 /* cpu output */ | |
327 | ||
1c2ce226 SR |
328 | /*----------------------------------------------------------------------- |
329 | * Definitions for GPIO setup | |
330 | *-----------------------------------------------------------------------*/ | |
f16c1da9 SR |
331 | #define CFG_GPIO_SHUTDOWN (0x80000000 >> 6) |
332 | #define CFG_GPIO_SSD_EMPTY (0x80000000 >> 9) | |
1c2ce226 SR |
333 | #define CFG_GPIO_EREADY (0x80000000 >> 26) |
334 | #define CFG_GPIO_REV0 (0x80000000 >> 14) | |
335 | #define CFG_GPIO_REV1 (0x80000000 >> 15) | |
336 | ||
337 | /*----------------------------------------------------------------------- | |
899620c2 | 338 | * NAND-FLASH stuff |
1c2ce226 | 339 | *-----------------------------------------------------------------------*/ |
5bc528fa SR |
340 | #define CFG_MAX_NAND_DEVICE 4 |
341 | #define NAND_MAX_CHIPS CFG_MAX_NAND_DEVICE | |
342 | #define CFG_NAND_BASE 0xF0000000 /* NAND FLASH Base Address */ | |
343 | #define CFG_NAND_BASE_LIST { CFG_NAND_BASE + 0, CFG_NAND_BASE + 2, \ | |
344 | CFG_NAND_BASE + 4, CFG_NAND_BASE + 6 } | |
345 | #define CFG_NAND_QUIET_TEST 1 /* don't warn upon unknown NAND flash */ | |
899620c2 SR |
346 | |
347 | /*----------------------------------------------------------------------- | |
348 | * External Bus Controller (EBC) Setup | |
349 | *----------------------------------------------------------------------*/ | |
350 | #define CFG_FLASH CFG_FLASH_BASE | |
351 | ||
352 | /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ | |
353 | #define CFG_EBC_PB0AP 0x92015480 | |
354 | #define CFG_EBC_PB0CR (CFG_FLASH | 0x3A000) /* BS=2MB,BU=R/W,BW=16bit */ | |
5bc528fa SR |
355 | |
356 | /* Memory Bank 1 (NAND-FLASH) initialization */ | |
357 | #define CFG_EBC_PB1AP 0x01840380 /* TWT=3 */ | |
1c2ce226 | 358 | #define CFG_EBC_PB1CR (CFG_NAND_BASE | 0x18000) /* BS=1MB,BU=R/W,BW=8bit */ |
899620c2 SR |
359 | |
360 | /* | |
361 | * For booting Linux, the board info and command line data | |
362 | * have to be in the first 8 MB of memory, since this is | |
363 | * the maximum mapped by the Linux kernel during initialization. | |
364 | */ | |
365 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
899620c2 SR |
366 | |
367 | /* | |
368 | * Internal Definitions | |
369 | * | |
370 | * Boot Flags | |
371 | */ | |
372 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
373 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
374 | ||
0b361c91 | 375 | #if defined(CONFIG_CMD_KGDB) |
899620c2 SR |
376 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
377 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
378 | #endif | |
9462732a SR |
379 | |
380 | /* pass open firmware flat tree */ | |
381 | #define CONFIG_OF_LIBFDT 1 | |
382 | #define CONFIG_OF_BOARD_SETUP 1 | |
383 | ||
899620c2 | 384 | #endif /* __CONFIG_H */ |