[people/ms/u-boot.git] / include / configs / alpr.h

/*
 * (C) Copyright 2006
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*-----------------------------------------------------------------------
 * High Level Configuration Options
 *----------------------------------------------------------------------*/
#define CONFIG_ALPR		1	    /* Board is ebony		*/
#define CONFIG_440GX		1	    /* Specifc GX support	*/
#define CONFIG_4xx		1	    /* ... PPC4xx family	*/
#define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_pre_init	*/
#undef	CFG_DRAM_TEST			    /* Disable-takes long time! */
#define CONFIG_SYS_CLK_FREQ	33333333    /* external freq to pll	*/

/*-----------------------------------------------------------------------
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 *----------------------------------------------------------------------*/
#define CFG_SDRAM_BASE	    0x00000000	    /* _must_ be 0		*/
#define CFG_FLASH_BASE	    0xffe00000	    /* start of FLASH		*/
#define CFG_MONITOR_BASE    0xfffc0000	    /* start of monitor		*/
#define CFG_PCI_MEMBASE	    0x80000000	    /* mapped pci memory	*/
#define	CFG_PCI_MEMSIZE	    0x40000000	    /* size of mapped pci memory */
#define CFG_PERIPHERAL_BASE 0xe0000000	    /* internal peripherals	*/
#define CFG_ISRAM_BASE	    0xc0000000	    /* internal SRAM		*/
#define CFG_PCI_BASE	    0xd0000000	    /* internal PCI regs	*/
#define CFG_PCI_MEMBASE1        CFG_PCI_MEMBASE  + 0x10000000
#define CFG_PCI_MEMBASE2        CFG_PCI_MEMBASE1 + 0x10000000
#define CFG_PCI_MEMBASE3        CFG_PCI_MEMBASE2 + 0x10000000


#define CFG_FPGA_BASE	    (CFG_PERIPHERAL_BASE + 0x08300000)
#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)

/*-----------------------------------------------------------------------
 * Initial RAM & stack pointer (placed in internal SRAM)
 *----------------------------------------------------------------------*/
#define CFG_TEMP_STACK_OCM  1
#define CFG_OCM_DATA_ADDR   CFG_ISRAM_BASE
#define CFG_INIT_RAM_ADDR   CFG_ISRAM_BASE  /* Initial RAM address	*/
#define CFG_INIT_RAM_END    0x2000	    /* End of used area in RAM	*/
#define CFG_GBL_DATA_SIZE   128		    /* num bytes initial data	*/

#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_POST_WORD_ADDR	(CFG_GBL_DATA_OFFSET - 0x4)
#define CFG_INIT_SP_OFFSET	CFG_POST_WORD_ADDR

#define CFG_MONITOR_LEN	    (256 * 1024)    /* Reserve 256 kB for Mon	*/
#define CFG_MALLOC_LEN	    (128 * 1024)    /* Reserve 128 kB for malloc*/

/*-----------------------------------------------------------------------
 * Serial Port
 *----------------------------------------------------------------------*/
#undef	CFG_EXT_SERIAL_CLOCK
#define CONFIG_BAUDRATE		115200
#define	CONFIG_UART1_CONSOLE		/* define for uart1 as console	*/

#define CFG_BAUDRATE_TABLE  \
    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

/*-----------------------------------------------------------------------
 * Environment
 *----------------------------------------------------------------------*/
#define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/

#if 0 /* test-only */
/*-----------------------------------------------------------------------
 * NVRAM/RTC
 *
 * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
 * The DS1743 code assumes this condition (i.e. -- it assumes the base
 * address for the RTC registers is:
 *
 *	CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
 *
 *----------------------------------------------------------------------*/
#define CFG_NVRAM_SIZE	    (0x2000 - 8)    /* NVRAM size(8k)- RTC regs */
#define CONFIG_RTC_DS174x	1		    /* DS1743 RTC		*/
#endif

/*-----------------------------------------------------------------------
 * FLASH related
 *----------------------------------------------------------------------*/
#define CFG_FLASH_CFI				/* The flash is CFI compatible	*/
#define CFG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/

#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }

#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
#define CFG_FLASH_PROTECTION	1	/* use hardware flash protection	*/

#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
#define CFG_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash	*/

#define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/

#define CFG_ENV_SECT_SIZE	0x10000 	/* size of one complete sector	*/
#define CFG_ENV_ADDR		(CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/

/* Address and size of Redundant Environment Sector	*/
#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)

/*-----------------------------------------------------------------------
 * DDR SDRAM
 *----------------------------------------------------------------------*/
#undef CONFIG_SPD_EEPROM		/* Don't use SPD EEPROM for setup	*/
#define CONFIG_SDRAM_BANK0	1	/* init onboard DDR SDRAM bank 0	*/
#undef CONFIG_SDRAM_ECC			/* enable ECC support			*/
#define CFG_SDRAM_TABLE	{ \
		{(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \
		{(64 << 20),  12, 0x00082001}} /* 64MB mode 2, 12x9(4)	*/

/*-----------------------------------------------------------------------
 * I2C
 *----------------------------------------------------------------------*/
#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
#undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
#define CFG_I2C_SPEED		100000	/* I2C speed and slave address	*/
#define CFG_I2C_SLAVE		0x7F
#define CFG_I2C_NOPROBES	{0x69}	/* Don't probe these addrs	*/

/*-----------------------------------------------------------------------
 * I2C EEPROM (PCF8594C)
 *----------------------------------------------------------------------*/
#define CFG_I2C_EEPROM_ADDR	0x54	/* EEPROM PCF8594C		*/
#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
/* mask of address bits that overflow into the "EEPROM chip address"	*/
#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
#define CFG_EEPROM_PAGE_WRITE_BITS 3	/* The Philips PCF8594C has	*/
					/* 8 byte page write mode using */
					/* last 3 bits of the address	*/
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	40   /* and takes up to 40 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"hostname=alpr\0"						\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
	"flash_nfs=run nfsargs addip addtty;"				\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip addtty;"				\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
	        "bootm\0"						\
	"rootpath=/opt/eldk/ppc_4xx\0"					\
	"bootfile=/tftpboot/alpr/uImage\0"				\
	"kernel_addr=fff00000\0"					\
	"ramdisk_addr=fff10000\0"					\
	"load=tftp 100000 /tftpboot/alpr/u-boot.bin\0"			\
	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"	\
		"cp.b 100000 fffc0000 40000;"			        \
		"setenv filesize;saveenv\0"				\
	"upd=run load;run update\0"					\
	""
#define CONFIG_BOOTCOMMAND	"run flash_self"

#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/

#define CONFIG_BAUDRATE		115200

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_NET_MULTI	1
#define CONFIG_PHY_ADDR		0x02	/* dummy setting, no EMAC0 used	*/
#define CONFIG_PHY1_ADDR	0x03	/* dummy setting, no EMAC1 used	*/
#define CONFIG_PHY2_ADDR	0x00	/* test-only: will be changed	*/
#define CONFIG_PHY3_ADDR	0x01	/* PHY address for EMAC3	*/
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
#define CONFIG_HAS_ETH3
#define CONFIG_PHY_RESET	1	/* reset phy upon startup	*/
#define CONFIG_88E1111_CLK_DELAY 1	/* set CLK delay on ALPR	*/
#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */

#if 0 /* test-only */
#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
				CFG_CMD_ASKENV	| \
				CFG_CMD_DATE	| \
				CFG_CMD_DHCP	| \
				CFG_CMD_DIAG	| \
				CFG_CMD_ELF	| \
				CFG_CMD_I2C	| \
				CFG_CMD_IRQ	| \
				CFG_CMD_MII	| \
				CFG_CMD_NET	| \
				CFG_CMD_NFS	| \
				CFG_CMD_PCI	| \
				CFG_CMD_PING	| \
				CFG_CMD_REGINFO	| \
				CFG_CMD_SNTP	)
#else
#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
				CFG_CMD_ASKENV	| \
				CFG_CMD_DHCP	| \
				CFG_CMD_DIAG	| \
				CFG_CMD_EEPROM	| \
				CFG_CMD_ELF	| \
				CFG_CMD_I2C	| \
				CFG_CMD_IRQ	| \
				CFG_CMD_MII	| \
				CFG_CMD_NET	| \
				CFG_CMD_NFS	| \
				CFG_CMD_PCI	| \
				CFG_CMD_PING	| \
				CFG_CMD_FPGA	| \
				CFG_CMD_NAND	| \
				CFG_CMD_REGINFO)
#endif

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

#undef CONFIG_WATCHDOG			/* watchdog disabled		*/

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define CFG_LOAD_ADDR		0x100000	/* default load address */
#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */

#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */

#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
#define CONFIG_LOOPW            1       /* enable loopw command         */
#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */

#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */

#define CONFIG_NETCONSOLE		/* include NetConsole support	*/

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
/* General PCI */
#define CONFIG_PCI			/* include pci support		*/
#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
#define CFG_PCI_TARGBASE    0x80000000	/* PCIaddr mapped to CFG_PCI_MEMBASE */
#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/

/* Board-specific PCI */
#define CFG_PCI_PRE_INIT		/* enable board pci_pre_init()	*/
#define CFG_PCI_TARGET_INIT		/* let board init pci target    */
#define CFG_PCI_MASTER_INIT

#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
#define CFG_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */

/*-----------------------------------------------------------------------
 * FPGA stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_FPGA             CFG_ALTERA_CYCLON2
#undef CFG_FPGA_CHECK_CTRLC
#undef CFG_FPGA_PROG_FEEDBACK
#define CONFIG_FPGA_COUNT       1		/* Ich habe 2 ... aber in
					Reihe geschaltet -> sollte gehen,
					aufpassen mit Datasize ist jetzt
					halt doppelt so gross ... Seite 306
					ist das mit den multiple Device in PS
					Mode erklaert ...*/


/* FPGA program pin configuration */
#define CFG_GPIO_CLK		18	/* FPGA clk pin (cpu output)		*/
#define CFG_GPIO_DATA		19	/* FPGA data pin (cpu output)		*/
#define CFG_GPIO_STATUS		20	/* FPGA status pin (cpu input)		*/
#define CFG_GPIO_CONFIG		21	/* FPGA CONFIG pin (cpu output)		*/
#define CFG_GPIO_CON_DON	22	/* FPGA CONFIG_DONE pin (cpu input)	*/

#define CFG_GPIO_SEL_DPR	14	/* cpu output */
#define CFG_GPIO_SEL_AVR	15	/* cpu output */
#define CFG_GPIO_PROG_EN	23	/* cpu output */

/*
 * NAND-FLASH stuff
 */
#define CFG_MAX_NAND_DEVICE	2
#define NAND_MAX_CHIPS		2
#define CFG_NAND_BASE		0x50000000	/* NAND FLASH Base Address	*/

#if 0
#define CONFIG_MTD_DEBUG
#define CONFIG_MTD_DEBUG_VERBOSE 4
#endif

/*-----------------------------------------------------------------------
 * External Bus Controller (EBC) Setup
 *----------------------------------------------------------------------*/
#define CFG_FLASH		CFG_FLASH_BASE

/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
#define CFG_EBC_PB0AP		0x92015480
#define CFG_EBC_PB0CR		(CFG_FLASH | 0x3A000) /* BS=2MB,BU=R/W,BW=16bit */
/* Memory Bank 1 (NAND-FLASH) initialization			*/
/*#define CFG_EBC_PB1AP		0x108f4380 */	/* TODO */
/*#define CFG_EBC_PB1AP		0x7f854380 */	/* TODO */
/*#define CFG_EBC_PB1AP		0x108553c0 */
/*#define CFG_EBC_PB1AP		0x108053c0 */
#define CFG_EBC_PB1AP		0x10810180

/*#define CFG_EBC_PB1CR		(CFG_NAND_BASE | 0x18000) *//* BS=1MB,BU=R/W,BW=8bit */
#define CFG_EBC_PB1CR		(CFG_NAND_BASE | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_DCACHE_SIZE		32768	/* For AMCC 440 CPUs			*/
#define CFG_CACHELINE_SIZE	32	/* ...			*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
#endif

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif
#endif	/* __CONFIG_H */
Commit	Line	Data
899620c2 SR	1	/*
	2	* (C) Copyright 2006
	3	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#ifndef __CONFIG_H
	25	#define __CONFIG_H
	26
	27	/*-----------------------------------------------------------------------
	28	* High Level Configuration Options
	29	----------------------------------------------------------------------/
	30	#define CONFIG_ALPR 1 /* Board is ebony */
	31	#define CONFIG_440GX 1 /* Specifc GX support */
	32	#define CONFIG_4xx 1 /* ... PPC4xx family */
	33	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
	34	#undef CFG_DRAM_TEST /* Disable-takes long time! */
	35	#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
	36
	37	/*-----------------------------------------------------------------------
	38	* Base addresses -- Note these are effective addresses where the
	39	* actual resources get mapped (not physical addresses)
	40	----------------------------------------------------------------------/
	41	#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
	42	#define CFG_FLASH_BASE 0xffe00000 /* start of FLASH */
	43	#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */
	44	#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
	45	#define CFG_PCI_MEMSIZE 0x40000000 /* size of mapped pci memory */
	46	#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
	47	#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */
	48	#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
	49	#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
	50	#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
	51	#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
	52
	53
	54	#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08300000)
	55	#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
	56
	57	/*-----------------------------------------------------------------------
	58	* Initial RAM & stack pointer (placed in internal SRAM)
	59	----------------------------------------------------------------------/
	60	#define CFG_TEMP_STACK_OCM 1
	61	#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE
	62	#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
	63	#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
	64	#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
65
66	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
67	#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
68	#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
69
70	#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
71	#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
72
73	/*-----------------------------------------------------------------------
74	* Serial Port
75	----------------------------------------------------------------------/
76	#undef CFG_EXT_SERIAL_CLOCK
77	#define CONFIG_BAUDRATE 115200
78	#define CONFIG_UART1_CONSOLE /* define for uart1 as console */
79
80	#define CFG_BAUDRATE_TABLE \
81	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
82
83	/*-----------------------------------------------------------------------
84	* Environment
85	----------------------------------------------------------------------/
86	#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
87
88	#if 0 /* test-only */
89	/*-----------------------------------------------------------------------
90	* NVRAM/RTC
91	*
92	* NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
93	* The DS1743 code assumes this condition (i.e. -- it assumes the base
94	* address for the RTC registers is:
95	*
96	* CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
97	*
98	----------------------------------------------------------------------/
99	#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */
100	#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
101	#endif
102
103	/*-----------------------------------------------------------------------
104	* FLASH related
105	----------------------------------------------------------------------/
106	#define CFG_FLASH_CFI /* The flash is CFI compatible */
107	#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
108
109	#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
110
111	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
112	#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
113
114	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
115	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
116
117	#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
118	#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */
119
120	#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
121	#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
122
123	#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
124
125	#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
126	#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
127	#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
128
129	/* Address and size of Redundant Environment Sector */
130	#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
131	#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
132
133	/*-----------------------------------------------------------------------
134	* DDR SDRAM
135	----------------------------------------------------------------------/
136	#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */
137	#define CONFIG_SDRAM_BANK0 1 /* init onboard DDR SDRAM bank 0 */
138	#undef CONFIG_SDRAM_ECC /* enable ECC support */
139	#define CFG_SDRAM_TABLE { \
140	{(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \
141	{(64 << 20), 12, 0x00082001}} /* 64MB mode 2, 12x9(4) */
142
143	/*-----------------------------------------------------------------------
144	* I2C
145	----------------------------------------------------------------------/
146	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
147	#undef CONFIG_SOFT_I2C /* I2C bit-banged */
148	#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
149	#define CFG_I2C_SLAVE 0x7F
150	#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
151
152	/*-----------------------------------------------------------------------
153	* I2C EEPROM (PCF8594C)
154	----------------------------------------------------------------------/
155	#define CFG_I2C_EEPROM_ADDR 0x54 /* EEPROM PCF8594C */
156	#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
157	/* mask of address bits that overflow into the "EEPROM chip address" */
158	#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
159	#define CFG_EEPROM_PAGE_WRITE_BITS 3 /* The Philips PCF8594C has */
160	/* 8 byte page write mode using */
161	/* last 3 bits of the address */
162	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 40 /* and takes up to 40 msec */
163	#define CFG_EEPROM_PAGE_WRITE_ENABLE
164
165	#define CONFIG_PREBOOT "echo;" \
166	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
167	"echo"
168
169	#undef CONFIG_BOOTARGS
170
171	#define CONFIG_EXTRA_ENV_SETTINGS \
172	"netdev=eth0\0" \
173	"hostname=alpr\0" \
174	"nfsargs=setenv bootargs root=/dev/nfs rw " \
175	"nfsroot=${serverip}:${rootpath}\0" \
176	"ramargs=setenv bootargs root=/dev/ram rw\0" \
177	"addip=setenv bootargs ${bootargs} " \
178	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
179	":${hostname}:${netdev}:off panic=1\0" \
180	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
181	"flash_nfs=run nfsargs addip addtty;" \
182	"bootm ${kernel_addr}\0" \
183	"flash_self=run ramargs addip addtty;" \
184	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
185	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
186	"bootm\0" \
187	"rootpath=/opt/eldk/ppc_4xx\0" \
188	"bootfile=/tftpboot/alpr/uImage\0" \
189	"kernel_addr=fff00000\0" \
190	"ramdisk_addr=fff10000\0" \
191	"load=tftp 100000 /tftpboot/alpr/u-boot.bin\0" \
192	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
193	"cp.b 100000 fffc0000 40000;" \
194	"setenv filesize;saveenv\0" \
195	"upd=run load;run update\0" \
196	""
197	#define CONFIG_BOOTCOMMAND "run flash_self"
198
199	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
200
201	#define CONFIG_BAUDRATE 115200
202
203	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
204	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
205
206	#define CONFIG_MII 1 /* MII PHY management */
207	#define CONFIG_NET_MULTI 1
208	#define CONFIG_PHY_ADDR 0x02 /* dummy setting, no EMAC0 used */
209	#define CONFIG_PHY1_ADDR 0x03 /* dummy setting, no EMAC1 used */
210	#define CONFIG_PHY2_ADDR 0x00 /* test-only: will be changed */
211	#define CONFIG_PHY3_ADDR 0x01 /* PHY address for EMAC3 */
212	#define CONFIG_HAS_ETH0
213	#define CONFIG_HAS_ETH1
214	#define CONFIG_HAS_ETH2
215	#define CONFIG_HAS_ETH3
216	#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
217	#define CONFIG_88E1111_CLK_DELAY 1 /* set CLK delay on ALPR */
218	#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
219
220	#if 0 /* test-only */
221	#define CONFIG_COMMANDS (CONFIG_CMD_DFL \| \
222	CFG_CMD_ASKENV \| \
223	CFG_CMD_DATE \| \
224	CFG_CMD_DHCP \| \
225	CFG_CMD_DIAG \| \
226	CFG_CMD_ELF \| \
227	CFG_CMD_I2C \| \
228	CFG_CMD_IRQ \| \
229	CFG_CMD_MII \| \
230	CFG_CMD_NET \| \
231	CFG_CMD_NFS \| \
232	CFG_CMD_PCI \| \
233	CFG_CMD_PING \| \
234	CFG_CMD_REGINFO \| \
235	CFG_CMD_SNTP )
236	#else
237	#define CONFIG_COMMANDS (CONFIG_CMD_DFL \| \
238	CFG_CMD_ASKENV \| \
239	CFG_CMD_DHCP \| \
240	CFG_CMD_DIAG \| \
241	CFG_CMD_EEPROM \| \
242	CFG_CMD_ELF \| \
243	CFG_CMD_I2C \| \
244	CFG_CMD_IRQ \| \
245	CFG_CMD_MII \| \
246	CFG_CMD_NET \| \
247	CFG_CMD_NFS \| \
248	CFG_CMD_PCI \| \
249	CFG_CMD_PING \| \
250	CFG_CMD_FPGA \| \
251	CFG_CMD_NAND \| \
252	CFG_CMD_REGINFO)
253	#endif
254
255	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
256	#include <cmd_confdefs.h>
257
258	#undef CONFIG_WATCHDOG /* watchdog disabled */
259
260	/*
261	* Miscellaneous configurable options
262	*/
263	#define CFG_LONGHELP /* undef to save memory */
264	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
265	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
266	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
267	#else
268	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
269	#endif
270	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
271	#define CFG_MAXARGS 16 /* max number of command args */
272	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
273
274	#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
275	#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
276
277	#define CFG_LOAD_ADDR 0x100000 /* default load address */
278	#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
279
280	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
281
282	#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
283	#define CONFIG_LOOPW 1 /* enable loopw command */
284	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
285	#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
286
287	#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
288
289	#define CONFIG_NETCONSOLE /* include NetConsole support */
290
291	/*-----------------------------------------------------------------------
292	* PCI stuff
293	*-----------------------------------------------------------------------
294	*/
295	/* General PCI */
296	#define CONFIG_PCI /* include pci support */
297	#define CONFIG_PCI_PNP /* do pci plug-and-play */
298	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
299	#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
300	#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
301
302	/* Board-specific PCI */
303	#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
304	#define CFG_PCI_TARGET_INIT /* let board init pci target */
305	#define CFG_PCI_MASTER_INIT
306
307	#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
308	#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
309
310	/*-----------------------------------------------------------------------
311	* FPGA stuff
312	*-----------------------------------------------------------------------
313	*/
314	#define CONFIG_FPGA CFG_ALTERA_CYCLON2
315	#undef CFG_FPGA_CHECK_CTRLC
316	#undef CFG_FPGA_PROG_FEEDBACK
317	#define CONFIG_FPGA_COUNT 1 /* Ich habe 2 ... aber in
318	Reihe geschaltet -> sollte gehen,
319	aufpassen mit Datasize ist jetzt
320	halt doppelt so gross ... Seite 306
321	ist das mit den multiple Device in PS
322	Mode erklaert ...*/
323
324
325	/* FPGA program pin configuration */
326	#define CFG_GPIO_CLK 18 /* FPGA clk pin (cpu output) */
327	#define CFG_GPIO_DATA 19 /* FPGA data pin (cpu output) */
328	#define CFG_GPIO_STATUS 20 /* FPGA status pin (cpu input) */
329	#define CFG_GPIO_CONFIG 21 /* FPGA CONFIG pin (cpu output) */
330	#define CFG_GPIO_CON_DON 22 /* FPGA CONFIG_DONE pin (cpu input) */
331
332	#define CFG_GPIO_SEL_DPR 14 /* cpu output */
333	#define CFG_GPIO_SEL_AVR 15 /* cpu output */
334	#define CFG_GPIO_PROG_EN 23 /* cpu output */
335
336	/*
337	* NAND-FLASH stuff
338	*/
339	#define CFG_MAX_NAND_DEVICE 2
340	#define NAND_MAX_CHIPS 2
341	#define CFG_NAND_BASE 0x50000000 /* NAND FLASH Base Address */
342
343	#if 0
344	#define CONFIG_MTD_DEBUG
345	#define CONFIG_MTD_DEBUG_VERBOSE 4
346	#endif
347
348	/*-----------------------------------------------------------------------
349	* External Bus Controller (EBC) Setup
350	----------------------------------------------------------------------/
351	#define CFG_FLASH CFG_FLASH_BASE
352
353	/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
354	#define CFG_EBC_PB0AP 0x92015480
355	#define CFG_EBC_PB0CR (CFG_FLASH \| 0x3A000) /* BS=2MB,BU=R/W,BW=16bit */
356	/* Memory Bank 1 (NAND-FLASH) initialization */
357	/#define CFG_EBC_PB1AP 0x108f4380 / /* TODO */
358	/#define CFG_EBC_PB1AP 0x7f854380 / /* TODO */
359	/#define CFG_EBC_PB1AP 0x108553c0 /
360	/#define CFG_EBC_PB1AP 0x108053c0 /
361	#define CFG_EBC_PB1AP 0x10810180
362
363	/#define CFG_EBC_PB1CR (CFG_NAND_BASE \| 0x18000) //* BS=1MB,BU=R/W,BW=8bit */
364	#define CFG_EBC_PB1CR (CFG_NAND_BASE \| 0x1A000) /* BS=1MB,BU=R/W,BW=16bit */
365
366	/*
367	* For booting Linux, the board info and command line data
368	* have to be in the first 8 MB of memory, since this is
369	* the maximum mapped by the Linux kernel during initialization.
370	*/
371	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
372	/*-----------------------------------------------------------------------
373	* Cache Configuration
374	*/
375	#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */
376	#define CFG_CACHELINE_SIZE 32 /* ... */
377	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
378	#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
379	#endif
380
381	/*
382	* Internal Definitions
383	*
384	* Boot Flags
385	*/
386	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
387	#define BOOTFLAG_WARM 0x02 /* Software reboot */
388
389	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
390	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
391	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
392	#endif
393	#endif /* __CONFIG_H */