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7254d92e HS |
1 | /* |
2 | * (C) Copyright 2015 | |
3 | * (C) Copyright 2014 | |
4 | * Heiko Schocher, DENX Software Engineering, hs@denx.de. | |
5 | * | |
6 | * Based on: | |
7 | * Copyright (C) 2012 Freescale Semiconductor, Inc. | |
8 | * | |
9 | * Configuration settings for the Freescale i.MX6Q SabreSD board. | |
10 | * | |
11 | * SPDX-License-Identifier: GPL-2.0+ | |
12 | */ | |
13 | #ifndef __ARISTAINETOS_COMMON_CONFIG_H | |
14 | #define __ARISTAINETOS_COMMON_CONFIG_H | |
15 | ||
7254d92e | 16 | #include "mx6_common.h" |
7254d92e | 17 | |
7254d92e HS |
18 | #define CONFIG_MACH_TYPE 4501 |
19 | #define CONFIG_MMCROOT "/dev/mmcblk0p1" | |
7254d92e | 20 | |
7254d92e HS |
21 | /* Size of malloc() pool */ |
22 | #define CONFIG_SYS_MALLOC_LEN (64 * SZ_1M) | |
23 | ||
24 | #define CONFIG_BOARD_EARLY_INIT_F | |
7254d92e HS |
25 | |
26 | #define CONFIG_MXC_UART | |
27 | ||
7254d92e | 28 | /* MMC Configs */ |
7254d92e HS |
29 | #define CONFIG_SYS_FSL_ESDHC_ADDR 0 |
30 | ||
7254d92e HS |
31 | #define CONFIG_FEC_MXC |
32 | #define CONFIG_MII | |
33 | #define IMX_FEC_BASE ENET_BASE_ADDR | |
34 | #define CONFIG_ETHPRIME "FEC" | |
35 | #define CONFIG_FEC_MXC_PHYADDR 0 | |
36 | ||
37 | #define CONFIG_PHYLIB | |
38 | #define CONFIG_PHY_MICREL | |
39 | ||
7254d92e | 40 | #define CONFIG_SPI_FLASH_MTD |
7254d92e | 41 | #define CONFIG_MXC_SPI |
7254d92e HS |
42 | #define CONFIG_SF_DEFAULT_SPEED 20000000 |
43 | #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 | |
44 | #define CONFIG_SYS_SPI_ST_ENABLE_WP_PIN | |
45 | ||
7254d92e | 46 | /* Command definition */ |
7254d92e | 47 | #define CONFIG_CMD_BMODE |
7254d92e | 48 | |
7254d92e HS |
49 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
50 | "script=u-boot.scr\0" \ | |
51 | "fit_file=/boot/system.itb\0" \ | |
52 | "loadaddr=0x12000000\0" \ | |
53 | "fit_addr_r=0x14000000\0" \ | |
54 | "uboot=/boot/u-boot.imx\0" \ | |
55 | "uboot_sz=d0000\0" \ | |
56 | "rescue_sys_addr=f0000\0" \ | |
57 | "rescue_sys_length=f10000\0" \ | |
58 | "panel=lb07wv8\0" \ | |
59 | "splashpos=m,m\0" \ | |
12ca05a3 | 60 | "console=" CONSOLE_DEV "\0" \ |
7254d92e HS |
61 | "fdt_high=0xffffffff\0" \ |
62 | "initrd_high=0xffffffff\0" \ | |
63 | "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ | |
64 | "set_fit_default=fdt addr ${fit_addr_r};fdt set /configurations " \ | |
65 | "default ${board_type}\0" \ | |
66 | "get_env=mw ${loadaddr} 0 0x20000;" \ | |
67 | "mmc rescan;" \ | |
68 | "ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} env.txt;" \ | |
69 | "env import -t ${loadaddr}\0" \ | |
70 | "default_env=mw ${loadaddr} 0 0x20000;" \ | |
71 | "env export -t ${loadaddr} serial# ethaddr eth1addr " \ | |
72 | "board_type panel;" \ | |
73 | "env default -a;" \ | |
74 | "env import -t ${loadaddr}\0" \ | |
75 | "loadbootscript=" \ | |
76 | "ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ | |
77 | "bootscript=echo Running bootscript from mmc ...; " \ | |
78 | "source\0" \ | |
79 | "mmcpart=1\0" \ | |
80 | "mmcdev=0\0" \ | |
81 | "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ | |
82 | "mmcargs=setenv bootargs console=${console},${baudrate} " \ | |
83 | "root=${mmcroot}\0" \ | |
84 | "mmcboot=echo Booting from mmc ...; " \ | |
85 | "run mmcargs addmtd addmisc set_fit_default;" \ | |
86 | "bootm ${fit_addr_r}\0" \ | |
87 | "mmc_load_fit=ext2load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \ | |
88 | "${fit_file}\0" \ | |
89 | "mmc_load_uboot=ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ | |
90 | "${uboot}\0" \ | |
91 | "mmc_upd_uboot=mw.b ${loadaddr} 0xff ${uboot_sz};" \ | |
92 | "setexpr cmp_buf ${loadaddr} + ${uboot_sz};" \ | |
93 | "setexpr uboot_maxsize ${uboot_sz} - 400;" \ | |
94 | "mw.b ${cmp_buf} 0x00 ${uboot_sz};" \ | |
95 | "run mmc_load_uboot;sf probe;sf erase 0 ${uboot_sz};" \ | |
96 | "sf write ${loadaddr} 400 ${filesize};" \ | |
97 | "sf read ${cmp_buf} 400 ${uboot_sz};" \ | |
98 | "cmp.b ${loadaddr} ${cmp_buf} ${uboot_maxsize}\0" \ | |
99 | "ubiboot=echo Booting from ubi ...; " \ | |
100 | "run ubiargs addmtd addmisc set_fit_default;" \ | |
101 | "bootm ${fit_addr_r}\0" \ | |
7254d92e HS |
102 | "rescueargs=setenv bootargs console=${console},${baudrate} " \ |
103 | "root=/dev/ram rw\0 " \ | |
104 | "rescueboot=echo Booting rescue system from NOR ...; " \ | |
105 | "run rescueargs addmtd addmisc set_fit_default;" \ | |
106 | "bootm ${fit_addr_r}\0" \ | |
107 | "rescue_load_fit=sf probe;sf read ${fit_addr_r} ${rescue_sys_addr} " \ | |
108 | "${rescue_sys_length}; imi ${fit_addr_r}\0" \ | |
109 | CONFIG_EXTRA_ENV_BOARD_SETTINGS | |
110 | ||
111 | #define CONFIG_BOOTCOMMAND \ | |
112 | "mmc dev ${mmcdev};" \ | |
113 | "if mmc rescan; then " \ | |
114 | "if run loadbootscript; then " \ | |
115 | "run bootscript; " \ | |
116 | "else " \ | |
117 | "if run mmc_load_fit; then " \ | |
118 | "run mmcboot; " \ | |
119 | "else " \ | |
120 | "if run ubifs_load_fit; then " \ | |
121 | "run ubiboot; " \ | |
122 | "else " \ | |
123 | "if run rescue_load_fit; then " \ | |
124 | "run rescueboot; " \ | |
125 | "else " \ | |
126 | "echo RESCUE SYSTEM BOOT " \ | |
127 | "FAILURE;" \ | |
128 | "fi; " \ | |
129 | "fi; " \ | |
130 | "fi; " \ | |
131 | "fi; " \ | |
132 | "else " \ | |
133 | "if run ubifs_load_fit; then " \ | |
134 | "run ubiboot; " \ | |
135 | "else " \ | |
136 | "if run rescue_load_fit; then " \ | |
137 | "run rescueboot; " \ | |
138 | "else " \ | |
139 | "echo RESCUE SYSTEM BOOT FAILURE;" \ | |
140 | "fi; " \ | |
141 | "fi; " \ | |
142 | "fi" | |
143 | ||
144 | #define CONFIG_ARP_TIMEOUT 200UL | |
145 | ||
7254d92e HS |
146 | /* Print Buffer Size */ |
147 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
7254d92e HS |
148 | |
149 | #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM | |
150 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000) | |
151 | #define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 | |
152 | ||
7254d92e HS |
153 | #define CONFIG_STACKSIZE (128 * 1024) |
154 | ||
155 | /* Physical Memory Map */ | |
156 | #define CONFIG_NR_DRAM_BANKS 1 | |
157 | #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR | |
158 | ||
159 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM | |
160 | #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR | |
161 | #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE | |
162 | ||
163 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
164 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
165 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
166 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
167 | ||
056845c2 | 168 | /* Environment organization */ |
7254d92e HS |
169 | #define CONFIG_ENV_SIZE (12 * 1024) |
170 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
171 | #define CONFIG_SYS_REDUNDAND_ENVIRONMENT | |
172 | #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS | |
173 | #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS | |
174 | #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED | |
175 | #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE | |
176 | #define CONFIG_ENV_SECT_SIZE (0x010000) | |
177 | #define CONFIG_ENV_OFFSET (0x0d0000) | |
178 | #define CONFIG_ENV_OFFSET_REDUND (0x0e0000) | |
179 | ||
7254d92e HS |
180 | #define CONFIG_SYS_FSL_USDHC_NUM 2 |
181 | ||
182 | /* I2C */ | |
7254d92e HS |
183 | #define CONFIG_SYS_I2C |
184 | #define CONFIG_SYS_I2C_MXC | |
03544c66 AA |
185 | #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ |
186 | #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ | |
7254d92e HS |
187 | #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ |
188 | #define CONFIG_SYS_I2C_SPEED 100000 | |
189 | #define CONFIG_SYS_I2C_SLAVE 0x7f | |
190 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x00} } | |
191 | ||
7254d92e HS |
192 | /* NAND stuff */ |
193 | #define CONFIG_CMD_NAND | |
194 | #define CONFIG_CMD_NAND_TRIMFFS | |
195 | #define CONFIG_NAND_MXS | |
196 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
197 | #define CONFIG_SYS_NAND_BASE 0x40000000 | |
198 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE | |
199 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
200 | ||
201 | /* DMA stuff, needed for GPMI/MXS NAND support */ | |
202 | #define CONFIG_APBH_DMA | |
203 | #define CONFIG_APBH_DMA_BURST | |
204 | #define CONFIG_APBH_DMA_BURST8 | |
205 | ||
206 | /* RTC */ | |
207 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
208 | #define CONFIG_SYS_RTC_BUS_NUM 2 | |
209 | #define CONFIG_RTC_M41T11 | |
210 | #define CONFIG_CMD_DATE | |
211 | ||
212 | /* USB Configs */ | |
7254d92e HS |
213 | #define CONFIG_USB_EHCI |
214 | #define CONFIG_USB_EHCI_MX6 | |
7254d92e HS |
215 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
216 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ | |
217 | #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) | |
218 | #define CONFIG_MXC_USB_FLAGS 0 | |
219 | ||
220 | /* UBI support */ | |
a380ce6e | 221 | #define CONFIG_LZO |
7254d92e HS |
222 | #define CONFIG_CMD_MTDPARTS |
223 | #define CONFIG_MTD_PARTITIONS | |
224 | #define CONFIG_MTD_DEVICE | |
225 | #define CONFIG_RBTREE | |
7254d92e HS |
226 | #define CONFIG_CMD_UBIFS |
227 | ||
7254d92e HS |
228 | #define CONFIG_HW_WATCHDOG |
229 | #define CONFIG_IMX_WATCHDOG | |
230 | ||
7254d92e | 231 | /* Framebuffer */ |
7254d92e HS |
232 | #define CONFIG_VIDEO_IPUV3 |
233 | /* check this console not needed, after test remove it */ | |
7254d92e HS |
234 | #define CONFIG_VIDEO_BMP_RLE8 |
235 | #define CONFIG_SPLASH_SCREEN | |
236 | #define CONFIG_SPLASH_SCREEN_ALIGN | |
237 | #define CONFIG_BMP_16BPP | |
238 | #define CONFIG_VIDEO_LOGO | |
239 | #define CONFIG_VIDEO_BMP_LOGO | |
240 | #define CONFIG_IPUV3_CLK 198000000 | |
241 | #define CONFIG_IMX_VIDEO_SKIP | |
242 | ||
243 | #define CONFIG_CMD_BMP | |
244 | ||
245 | #define CONFIG_PWM_IMX | |
246 | #define CONFIG_IMX6_PWM_PER_CLK 66000000 | |
247 | ||
248 | #endif /* __ARISTAINETOS_COMMON_CONFIG_H */ |