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8e429b3e SP |
1 | /* |
2 | * (C) Copyright 2007-2008 | |
3 | * Stelian Pop <stelian.pop@leadtechdesign.com> | |
4 | * Lead Tech Design <www.leadtechdesign.com> | |
5 | * | |
6 | * Configuation settings for the AT91SAM9263EK board. | |
7 | * | |
8 | * See file CREDITS for list of people who contributed to this | |
9 | * project. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of | |
14 | * the License, or (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
24 | * MA 02111-1307 USA | |
25 | */ | |
26 | ||
27 | #ifndef __CONFIG_H | |
28 | #define __CONFIG_H | |
29 | ||
425de62d JS |
30 | #define CONFIG_AT91_LEGACY |
31 | ||
8e429b3e | 32 | /* ARM asynchronous clock */ |
ad229a44 | 33 | #define AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ |
6ebff365 | 34 | #define CONFIG_SYS_HZ 1000 |
8e429b3e | 35 | |
8e429b3e SP |
36 | #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ |
37 | #define CONFIG_AT91SAM9263 1 /* It's an Atmel AT91SAM9263 SoC*/ | |
38 | #define CONFIG_AT91SAM9263EK 1 /* on an AT91SAM9263EK Board */ | |
dc39ae95 | 39 | #define CONFIG_ARCH_CPU_INIT |
8e429b3e SP |
40 | #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ |
41 | ||
42 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ | |
43 | #define CONFIG_SETUP_MEMORY_TAGS 1 | |
44 | #define CONFIG_INITRD_TAG 1 | |
45 | ||
1b3b7c64 | 46 | #ifndef CONFIG_SYS_USE_BOOT_NORFLASH |
8e429b3e SP |
47 | #define CONFIG_SKIP_LOWLEVEL_INIT |
48 | #define CONFIG_SKIP_RELOCATE_UBOOT | |
1b3b7c64 | 49 | #endif |
8e429b3e SP |
50 | |
51 | /* | |
52 | * Hardware drivers | |
53 | */ | |
ea8fbba7 | 54 | #define CONFIG_AT91_GPIO 1 |
8e429b3e SP |
55 | #define CONFIG_ATMEL_USART 1 |
56 | #undef CONFIG_USART0 | |
57 | #undef CONFIG_USART1 | |
58 | #undef CONFIG_USART2 | |
59 | #define CONFIG_USART3 1 /* USART 3 is DBGU */ | |
60 | ||
56a2479c SP |
61 | /* LCD */ |
62 | #define CONFIG_LCD 1 | |
63 | #define LCD_BPP LCD_COLOR8 | |
64 | #define CONFIG_LCD_LOGO 1 | |
65 | #undef LCD_TEST_PATTERN | |
66 | #define CONFIG_LCD_INFO 1 | |
67 | #define CONFIG_LCD_INFO_BELOW_LOGO 1 | |
6d0f6bcf | 68 | #define CONFIG_SYS_WHITE_ON_BLACK 1 |
56a2479c SP |
69 | #define CONFIG_ATMEL_LCD 1 |
70 | #define CONFIG_ATMEL_LCD_BGR555 1 | |
6d0f6bcf | 71 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 |
56a2479c | 72 | |
a484b00b JCPV |
73 | /* LED */ |
74 | #define CONFIG_AT91_LED | |
75 | #define CONFIG_RED_LED AT91_PIN_PB7 /* this is the power led */ | |
76 | #define CONFIG_GREEN_LED AT91_PIN_PB8 /* this is the user1 led */ | |
77 | #define CONFIG_YELLOW_LED AT91_PIN_PC29 /* this is the user2 led */ | |
78 | ||
8e429b3e SP |
79 | #define CONFIG_BOOTDELAY 3 |
80 | ||
8e429b3e SP |
81 | /* |
82 | * BOOTP options | |
83 | */ | |
84 | #define CONFIG_BOOTP_BOOTFILESIZE 1 | |
85 | #define CONFIG_BOOTP_BOOTPATH 1 | |
86 | #define CONFIG_BOOTP_GATEWAY 1 | |
87 | #define CONFIG_BOOTP_HOSTNAME 1 | |
88 | ||
89 | /* | |
90 | * Command line configuration. | |
91 | */ | |
92 | #include <config_cmd_default.h> | |
93 | #undef CONFIG_CMD_BDI | |
8e429b3e | 94 | #undef CONFIG_CMD_FPGA |
74de7aef | 95 | #undef CONFIG_CMD_IMI |
8e429b3e | 96 | #undef CONFIG_CMD_IMLS |
74de7aef WD |
97 | #undef CONFIG_CMD_LOADS |
98 | #undef CONFIG_CMD_SOURCE | |
8e429b3e SP |
99 | |
100 | #define CONFIG_CMD_PING 1 | |
101 | #define CONFIG_CMD_DHCP 1 | |
102 | #define CONFIG_CMD_NAND 1 | |
103 | #define CONFIG_CMD_USB 1 | |
104 | ||
105 | /* SDRAM */ | |
106 | #define CONFIG_NR_DRAM_BANKS 1 | |
107 | #define PHYS_SDRAM 0x20000000 | |
108 | #define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ | |
109 | ||
110 | /* DataFlash */ | |
4758ebdd | 111 | #define CONFIG_ATMEL_DATAFLASH_SPI |
8e429b3e | 112 | #define CONFIG_HAS_DATAFLASH 1 |
6d0f6bcf JCPV |
113 | #define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) |
114 | #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 | |
115 | #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ | |
8e429b3e SP |
116 | #define AT91_SPI_CLK 15000000 |
117 | #define DATAFLASH_TCSS (0x1a << 16) | |
118 | #define DATAFLASH_TCHS (0x1 << 24) | |
119 | ||
120 | /* NOR flash, if populated */ | |
1b3b7c64 | 121 | #ifdef CONFIG_SYS_USE_NORFLASH |
6d0f6bcf | 122 | #define CONFIG_SYS_FLASH_CFI 1 |
1b3b7c64 JCPV |
123 | #define CONFIG_FLASH_CFI_DRIVER 1 |
124 | #define PHYS_FLASH_1 0x10000000 | |
6d0f6bcf JCPV |
125 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
126 | #define CONFIG_SYS_MAX_FLASH_SECT 256 | |
127 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
1b3b7c64 JCPV |
128 | |
129 | #define CONFIG_SYS_MONITOR_SEC 1:0-3 | |
130 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
131 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) | |
132 | #define CONFIG_ENV_IS_IN_FLASH 1 | |
133 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x007FE000) | |
134 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SIZE) | |
135 | ||
136 | /* Address and size of Primary Environment Sector */ | |
137 | #define CONFIG_ENV_SIZE 0x2000 | |
138 | ||
139 | #define xstr(s) str(s) | |
140 | #define str(s) #s | |
141 | ||
142 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
143 | "monitor_base=" xstr(CONFIG_SYS_MONITOR_BASE) "\0" \ | |
144 | "update=" \ | |
145 | "protect off ${monitor_base} +${filesize};" \ | |
146 | "erase ${monitor_base} +${filesize};" \ | |
147 | "cp.b ${load_addr} ${monitor_base} ${filesize};" \ | |
148 | "protect on ${monitor_base} +${filesize}\0" | |
149 | ||
150 | #ifndef CONFIG_SKIP_LOWLEVEL_INIT | |
151 | #define MASTER_PLL_MUL 171 | |
152 | #define MASTER_PLL_DIV 14 | |
153 | ||
154 | /* clocks */ | |
155 | #define CONFIG_SYS_MOR_VAL \ | |
156 | (AT91_PMC_MOSCEN | \ | |
157 | (255 << 8)) /* Main Oscillator Start-up Time */ | |
158 | #define CONFIG_SYS_PLLAR_VAL \ | |
159 | (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \ | |
160 | AT91_PMC_OUT | \ | |
161 | AT91_PMC_PLLCOUNT | /* PLL Counter */ \ | |
162 | (2 << 28) | /* PLL Clock Frequency Range */ \ | |
163 | ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) | |
164 | ||
165 | /* PCK/2 = MCK Master Clock from PLLA */ | |
166 | #define CONFIG_SYS_MCKR1_VAL \ | |
167 | (AT91_PMC_CSS_SLOW | \ | |
168 | AT91_PMC_PRES_1 | \ | |
169 | AT91SAM9_PMC_MDIV_2 | \ | |
170 | AT91_PMC_PDIV_1) | |
171 | /* PCK/2 = MCK Master Clock from PLLA */ | |
172 | #define CONFIG_SYS_MCKR2_VAL \ | |
173 | (AT91_PMC_CSS_PLLA | \ | |
174 | AT91_PMC_PRES_1 | \ | |
175 | AT91SAM9_PMC_MDIV_2 | \ | |
176 | AT91_PMC_PDIV_1) | |
177 | ||
178 | /* define PDC[31:16] as DATA[31:16] */ | |
179 | #define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 | |
180 | /* no pull-up for D[31:16] */ | |
181 | #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 | |
182 | /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ | |
183 | #define CONFIG_SYS_MATRIX_EBI0CSA_VAL \ | |
184 | (AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V | \ | |
185 | AT91_MATRIX_EBI0_CS1A_SDRAMC) | |
186 | ||
187 | /* SDRAM */ | |
188 | /* SDRAMC_MR Mode register */ | |
189 | #define CONFIG_SYS_SDRC_MR_VAL1 0 | |
190 | /* SDRAMC_TR - Refresh Timer register */ | |
191 | #define CONFIG_SYS_SDRC_TR_VAL1 0x13C | |
192 | /* SDRAMC_CR - Configuration register*/ | |
193 | #define CONFIG_SYS_SDRC_CR_VAL \ | |
194 | (AT91_SDRAMC_NC_9 | \ | |
195 | AT91_SDRAMC_NR_13 | \ | |
196 | AT91_SDRAMC_NB_4 | \ | |
197 | AT91_SDRAMC_CAS_3 | \ | |
198 | AT91_SDRAMC_DBW_32 | \ | |
199 | (1 << 8) | /* Write Recovery Delay */ \ | |
200 | (7 << 12) | /* Row Cycle Delay */ \ | |
201 | (2 << 16) | /* Row Precharge Delay */ \ | |
202 | (2 << 20) | /* Row to Column Delay */ \ | |
203 | (5 << 24) | /* Active to Precharge Delay */ \ | |
204 | (1 << 28)) /* Exit Self Refresh to Active Delay */ | |
205 | ||
206 | /* Memory Device Register -> SDRAM */ | |
207 | #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM | |
208 | #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE | |
209 | #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ | |
210 | #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH | |
211 | #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ | |
212 | #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ | |
213 | #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ | |
214 | #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ | |
215 | #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ | |
216 | #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ | |
217 | #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ | |
218 | #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ | |
219 | #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR | |
220 | #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ | |
221 | #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL | |
222 | #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ | |
223 | #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ | |
224 | #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ | |
225 | ||
226 | /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ | |
227 | #define CONFIG_SYS_SMC0_SETUP0_VAL \ | |
228 | (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \ | |
229 | AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10)) | |
230 | #define CONFIG_SYS_SMC0_PULSE0_VAL \ | |
231 | (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \ | |
232 | AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11)) | |
233 | #define CONFIG_SYS_SMC0_CYCLE0_VAL \ | |
234 | (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22)) | |
235 | #define CONFIG_SYS_SMC0_MODE0_VAL \ | |
236 | (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \ | |
237 | AT91_SMC_DBW_16 | \ | |
238 | AT91_SMC_TDFMODE | \ | |
239 | AT91_SMC_TDF_(6)) | |
240 | ||
241 | /* user reset enable */ | |
242 | #define CONFIG_SYS_RSTC_RMR_VAL \ | |
243 | (AT91_RSTC_KEY | \ | |
244 | AT91_RSTC_PROCRST | \ | |
245 | AT91_RSTC_RSTTYP_WAKEUP | \ | |
246 | AT91_RSTC_RSTTYP_WATCHDOG) | |
247 | ||
248 | /* Disable Watchdog */ | |
249 | #define CONFIG_SYS_WDTC_WDMR_VAL \ | |
250 | (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \ | |
251 | AT91_WDT_WDV | \ | |
252 | AT91_WDT_WDDIS | \ | |
253 | AT91_WDT_WDD) | |
254 | #endif | |
255 | ||
256 | #else | |
257 | #define CONFIG_SYS_NO_FLASH 1 | |
8e429b3e SP |
258 | #endif |
259 | ||
260 | /* NAND flash */ | |
74c076d6 JCPV |
261 | #ifdef CONFIG_CMD_NAND |
262 | #define CONFIG_NAND_ATMEL | |
6d0f6bcf JCPV |
263 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
264 | #define CONFIG_SYS_NAND_BASE 0x40000000 | |
265 | #define CONFIG_SYS_NAND_DBW_8 1 | |
74c076d6 JCPV |
266 | /* our ALE is AD21 */ |
267 | #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) | |
268 | /* our CLE is AD22 */ | |
269 | #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) | |
270 | #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15 | |
271 | #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22 | |
2eb99ca8 | 272 | |
74c076d6 | 273 | #endif |
8e429b3e SP |
274 | |
275 | /* Ethernet */ | |
276 | #define CONFIG_MACB 1 | |
277 | #define CONFIG_RMII 1 | |
278 | #define CONFIG_NET_MULTI 1 | |
279 | #define CONFIG_NET_RETRY_COUNT 20 | |
280 | #define CONFIG_RESET_PHY_R 1 | |
281 | ||
282 | /* USB */ | |
2b7178af | 283 | #define CONFIG_USB_ATMEL |
8e429b3e | 284 | #define CONFIG_USB_OHCI_NEW 1 |
8e429b3e | 285 | #define CONFIG_DOS_PARTITION 1 |
6d0f6bcf JCPV |
286 | #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 |
287 | #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ | |
288 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" | |
289 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 | |
8e429b3e | 290 | #define CONFIG_USB_STORAGE 1 |
3e0cda07 | 291 | #define CONFIG_CMD_FAT 1 |
8e429b3e | 292 | |
6d0f6bcf | 293 | #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ |
8e429b3e | 294 | |
6d0f6bcf JCPV |
295 | #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM |
296 | #define CONFIG_SYS_MEMTEST_END 0x23e00000 | |
8e429b3e | 297 | |
6d0f6bcf | 298 | #ifdef CONFIG_SYS_USE_DATAFLASH |
8e429b3e SP |
299 | |
300 | /* bootstrap + u-boot + env + linux in dataflash on CS0 */ | |
057c849c | 301 | #define CONFIG_ENV_IS_IN_DATAFLASH 1 |
6d0f6bcf | 302 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400) |
0e8d1586 | 303 | #define CONFIG_ENV_OFFSET 0x4200 |
6d0f6bcf | 304 | #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) |
0e8d1586 | 305 | #define CONFIG_ENV_SIZE 0x4200 |
8e429b3e SP |
306 | #define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm" |
307 | #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ | |
308 | "root=/dev/mtdblock0 " \ | |
918319c7 | 309 | "mtdparts=atmel_nand:-(root) "\ |
8e429b3e SP |
310 | "rw rootfstype=jffs2" |
311 | ||
1b3b7c64 | 312 | #elif CONFIG_SYS_USE_NANDFLASH |
8e429b3e SP |
313 | |
314 | /* bootstrap + u-boot + env + linux in nandflash */ | |
51bfee19 | 315 | #define CONFIG_ENV_IS_IN_NAND 1 |
0e8d1586 JCPV |
316 | #define CONFIG_ENV_OFFSET 0x60000 |
317 | #define CONFIG_ENV_OFFSET_REDUND 0x80000 | |
318 | #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ | |
8e429b3e SP |
319 | #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm" |
320 | #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ | |
321 | "root=/dev/mtdblock5 " \ | |
918319c7 | 322 | "mtdparts=atmel_nand:128k(bootstrap)ro,256k(uboot)ro,128k(env1)ro,128k(env2)ro,2M(linux),-(root) " \ |
8e429b3e SP |
323 | "rw rootfstype=jffs2" |
324 | ||
325 | #endif | |
326 | ||
327 | #define CONFIG_BAUDRATE 115200 | |
6d0f6bcf | 328 | #define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } |
8e429b3e | 329 | |
6d0f6bcf JCPV |
330 | #define CONFIG_SYS_PROMPT "U-Boot> " |
331 | #define CONFIG_SYS_CBSIZE 256 | |
332 | #define CONFIG_SYS_MAXARGS 16 | |
333 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
334 | #define CONFIG_SYS_LONGHELP 1 | |
8e429b3e | 335 | #define CONFIG_CMDLINE_EDITING 1 |
03bab009 JCPV |
336 | #define CONFIG_AUTO_COMPLETE |
337 | #define CONFIG_SYS_HUSH_PARSER | |
338 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
8e429b3e | 339 | |
8e429b3e SP |
340 | /* |
341 | * Size of malloc() pool | |
342 | */ | |
6d0f6bcf JCPV |
343 | #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) |
344 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ | |
8e429b3e SP |
345 | |
346 | #define CONFIG_STACKSIZE (32*1024) /* regular stack */ | |
347 | ||
348 | #ifdef CONFIG_USE_IRQ | |
349 | #error CONFIG_USE_IRQ not supported | |
350 | #endif | |
351 | ||
352 | #endif |