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6ccec449 WD |
1 | /* |
2 | * Copyright (C) 2005-2006 Atmel Corporation | |
3 | * | |
4 | * Configuration settings for the ATSTK1002 CPU daughterboard | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | #ifndef __CONFIG_H | |
25 | #define __CONFIG_H | |
26 | ||
27 | #define CONFIG_AVR32 1 | |
28 | #define CONFIG_AT32AP 1 | |
29 | #define CONFIG_AT32AP7000 1 | |
30 | #define CONFIG_ATSTK1002 1 | |
31 | #define CONFIG_ATSTK1000 1 | |
32 | ||
33 | #define CONFIG_ATSTK1000_EXT_FLASH 1 | |
34 | ||
35 | /* | |
36 | * Timer clock frequency. We're using the CPU-internal COUNT register | |
37 | * for this, so this is equivalent to the CPU core clock frequency | |
38 | */ | |
39 | #define CFG_HZ 1000 | |
40 | ||
41 | /* | |
42 | * Set up the PLL to run at 199.5 MHz, the CPU to run at 1/2 the PLL | |
43 | * frequency and the peripherals to run at 1/4 the PLL frequency. | |
44 | */ | |
45 | #define CONFIG_PLL 1 | |
46 | #define CFG_POWER_MANAGER 1 | |
47 | #define CFG_OSC0_HZ 20000000 | |
48 | #define CFG_PLL0_DIV 1 | |
49 | #define CFG_PLL0_MUL 7 | |
50 | #define CFG_PLL0_SUPPRESS_CYCLES 16 | |
51 | #define CFG_CLKDIV_CPU 0 | |
52 | #define CFG_CLKDIV_HSB 1 | |
53 | #define CFG_CLKDIV_PBA 2 | |
54 | #define CFG_CLKDIV_PBB 1 | |
55 | ||
56 | /* | |
57 | * The PLLOPT register controls the PLL like this: | |
58 | * icp = PLLOPT<2> | |
59 | * ivco = PLLOPT<1:0> | |
60 | * | |
61 | * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). | |
62 | */ | |
63 | #define CFG_PLL0_OPT 0x04 | |
64 | ||
df548d3c HS |
65 | #undef CONFIG_USART0 |
66 | #define CONFIG_USART1 1 | |
67 | #undef CONFIG_USART2 | |
68 | #undef CONFIG_USART3 | |
6ccec449 WD |
69 | |
70 | /* User serviceable stuff */ | |
71 | #define CONFIG_CMDLINE_TAG 1 | |
72 | #define CONFIG_SETUP_MEMORY_TAGS 1 | |
73 | #define CONFIG_INITRD_TAG 1 | |
74 | ||
75 | #define CONFIG_STACKSIZE (2048) | |
76 | ||
77 | #define CONFIG_BAUDRATE 115200 | |
78 | #define CONFIG_BOOTARGS \ | |
1b804b22 HS |
79 | "console=ttyS0 root=/dev/mtdblock1 rootfstype=jffs2 fbmem=600k" |
80 | ||
81 | #define CONFIG_BOOTCOMMAND \ | |
82 | "fsload; bootm $(fileaddr)" | |
83 | ||
84 | /* | |
85 | * Only interrupt autoboot if <space> is pressed. Otherwise, garbage | |
86 | * data on the serial line may interrupt the boot sequence. | |
87 | */ | |
88 | #define CONFIG_BOOTDELAY 2 | |
89 | #define CONFIG_AUTOBOOT 1 | |
90 | #define CONFIG_AUTOBOOT_KEYED 1 | |
91 | #define CONFIG_AUTOBOOT_PROMPT \ | |
92 | "Press SPACE to abort autoboot in %d seconds\n" | |
93 | #define CONFIG_AUTOBOOT_DELAY_STR "d" | |
94 | #define CONFIG_AUTOBOOT_STOP_STR " " | |
6ccec449 | 95 | |
9a24f477 HS |
96 | /* |
97 | * These are "locally administered ethernet addresses" generated by | |
98 | * ./tools/gen_eth_addr | |
99 | * | |
100 | * After booting the board for the first time, new addresses should be | |
101 | * generated and assigned to the environment variables "ethaddr" and | |
102 | * "eth1addr". | |
103 | */ | |
104 | #define CONFIG_ETHADDR "6a:87:71:14:cd:cb" | |
105 | #define CONFIG_ETH1ADDR "ca:f8:15:e6:3e:e6" | |
106 | #define CONFIG_OVERWRITE_ETHADDR_ONCE 1 | |
107 | #define CONFIG_NET_MULTI 1 | |
108 | ||
109 | #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_SUBNETMASK \ | |
110 | | CONFIG_BOOTP_GATEWAY) | |
111 | ||
6ccec449 WD |
112 | #define CONFIG_COMMANDS (CFG_CMD_BDI \ |
113 | | CFG_CMD_LOADS \ | |
114 | | CFG_CMD_LOADB \ | |
1b804b22 | 115 | | CFG_CMD_IMI \ |
6ccec449 WD |
116 | /* | CFG_CMD_CACHE */ \ |
117 | | CFG_CMD_FLASH \ | |
118 | | CFG_CMD_MEMORY \ | |
9a24f477 | 119 | | CFG_CMD_NET \ |
6ccec449 WD |
120 | | CFG_CMD_ENV \ |
121 | /* | CFG_CMD_IRQ */ \ | |
122 | | CFG_CMD_BOOTD \ | |
123 | | CFG_CMD_CONSOLE \ | |
124 | /* | CFG_CMD_EEPROM */ \ | |
125 | | CFG_CMD_ASKENV \ | |
126 | | CFG_CMD_RUN \ | |
127 | | CFG_CMD_ECHO \ | |
128 | /* | CFG_CMD_I2C */ \ | |
129 | | CFG_CMD_REGINFO \ | |
130 | /* | CFG_CMD_DATE */ \ | |
9a24f477 | 131 | | CFG_CMD_DHCP \ |
6ccec449 WD |
132 | /* | CFG_CMD_AUTOSCRIPT */ \ |
133 | /* | CFG_CMD_MII */ \ | |
134 | | CFG_CMD_MISC \ | |
135 | /* | CFG_CMD_SDRAM */ \ | |
136 | /* | CFG_CMD_DIAG */ \ | |
137 | /* | CFG_CMD_HWFLOW */ \ | |
138 | /* | CFG_CMD_SAVES */ \ | |
139 | /* | CFG_CMD_SPI */ \ | |
140 | /* | CFG_CMD_PING */ \ | |
141 | /* | CFG_CMD_MMC */ \ | |
142 | /* | CFG_CMD_FAT */ \ | |
1b804b22 | 143 | | CFG_CMD_IMLS \ |
6ccec449 WD |
144 | /* | CFG_CMD_ITEST */ \ |
145 | /* | CFG_CMD_EXT2 */ \ | |
1b804b22 | 146 | | CFG_CMD_JFFS2 \ |
6ccec449 WD |
147 | ) |
148 | ||
149 | #include <cmd_confdefs.h> | |
150 | ||
151 | #define CONFIG_ATMEL_USART 1 | |
9a24f477 | 152 | #define CONFIG_MACB 1 |
6ccec449 WD |
153 | #define CONFIG_PIO2 1 |
154 | #define CFG_NR_PIOS 5 | |
155 | #define CFG_HSDRAMC 1 | |
156 | ||
157 | #define CFG_DCACHE_LINESZ 32 | |
158 | #define CFG_ICACHE_LINESZ 32 | |
159 | ||
160 | #define CONFIG_NR_DRAM_BANKS 1 | |
161 | ||
162 | /* External flash on STK1000 */ | |
163 | #if 0 | |
164 | #define CFG_FLASH_CFI 1 | |
165 | #define CFG_FLASH_CFI_DRIVER 1 | |
166 | #endif | |
167 | ||
168 | #define CFG_FLASH_BASE 0x00000000 | |
169 | #define CFG_FLASH_SIZE 0x800000 | |
170 | #define CFG_MAX_FLASH_BANKS 1 | |
171 | #define CFG_MAX_FLASH_SECT 135 | |
172 | ||
173 | #define CFG_MONITOR_BASE CFG_FLASH_BASE | |
174 | ||
175 | #define CFG_INTRAM_BASE 0x24000000 | |
176 | #define CFG_INTRAM_SIZE 0x8000 | |
177 | ||
178 | #define CFG_SDRAM_BASE 0x10000000 | |
179 | ||
180 | #define CFG_ENV_IS_IN_FLASH 1 | |
181 | #define CFG_ENV_SIZE 65536 | |
182 | #define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE) | |
183 | ||
184 | #define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE) | |
185 | ||
186 | #define CFG_MALLOC_LEN (256*1024) | |
6ccec449 | 187 | #define CFG_DMA_ALLOC_LEN (16384) |
1f4f2121 | 188 | |
6ccec449 WD |
189 | /* Allow 2MB for the kernel run-time image */ |
190 | #define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00200000) | |
191 | #define CFG_BOOTPARAMS_LEN (16 * 1024) | |
192 | ||
193 | /* Other configuration settings that shouldn't have to change all that often */ | |
194 | #define CFG_PROMPT "Uboot> " | |
195 | #define CFG_CBSIZE 256 | |
196 | #define CFG_MAXARGS 8 | |
197 | #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) | |
198 | #define CFG_LONGHELP 1 | |
199 | ||
200 | #define CFG_MEMTEST_START \ | |
201 | ({ DECLARE_GLOBAL_DATA_PTR; gd->bd->bi_dram[0].start; }) | |
202 | #define CFG_MEMTEST_END \ | |
203 | ({ \ | |
204 | DECLARE_GLOBAL_DATA_PTR; \ | |
205 | gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; \ | |
206 | }) | |
207 | #define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } | |
208 | ||
209 | #endif /* __CONFIG_H */ |