[people/ms/u-boot.git] / include / configs / bamboo.h

/*
 * (C) Copyright 2005-2007
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/************************************************************************
 * bamboo.h - configuration for BAMBOO board
 ***********************************************************************/
#ifndef __CONFIG_H
#define __CONFIG_H

/*-----------------------------------------------------------------------
 * High Level Configuration Options
 *----------------------------------------------------------------------*/
#define CONFIG_BAMBOO		1	/* Board is BAMBOO              */
#define CONFIG_440EP		1	/* Specific PPC440EP support    */
#define CONFIG_440		1	/* ... PPC440 family	        */
#define CONFIG_4xx		1	/* ... PPC4xx family	        */
#define CONFIG_SYS_CLK_FREQ	33333333    /* external freq to pll	*/

#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE	0xFFFA0000
#endif

/*
 * Include common defines/options for all AMCC eval boards
 */
#define CONFIG_HOSTNAME		bamboo
#include "amcc-common.h"

#define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f	*/

/*
 * Please note that, if NAND support is enabled, the 2nd ethernet port
 * can't be used because of pin multiplexing. So, if you want to use the
 * 2nd ethernet port you have to "undef" the following define.
 */
#define CONFIG_BAMBOO_NAND      1       /* enable nand flash support    */

/*-----------------------------------------------------------------------
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_FLASH_BASE	        0xfff00000	    /* start of FLASH	*/
#define CONFIG_SYS_PCI_MEMBASE	        0xa0000000	    /* mapped pci memory*/
#define CONFIG_SYS_PCI_MEMBASE1        CONFIG_SYS_PCI_MEMBASE  + 0x10000000
#define CONFIG_SYS_PCI_MEMBASE2        CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
#define CONFIG_SYS_PCI_MEMBASE3        CONFIG_SYS_PCI_MEMBASE2 + 0x10000000

/*Don't change either of these*/
#define CONFIG_SYS_PCI_BASE		0xe0000000	    /* internal PCI regs*/
/*Don't change either of these*/

#define CONFIG_SYS_USB_DEVICE          0x50000000
#define CONFIG_SYS_NVRAM_BASE_ADDR     0x80000000
#define CONFIG_SYS_BOOT_BASE_ADDR      0xf0000000
#define CONFIG_SYS_NAND_ADDR           0x90000000
#define CONFIG_SYS_NAND2_ADDR          0x94000000

/*-----------------------------------------------------------------------
 * Initial RAM & stack pointer (placed in SDRAM)
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_INIT_RAM_DCACHE	1		/* d-cache as init ram	*/
#define CONFIG_SYS_INIT_RAM_ADDR	0x70000000	/* DCache       */
#define CONFIG_SYS_INIT_RAM_SIZE	(4 << 10)
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Serial Port
 *----------------------------------------------------------------------*/
#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
#define CONFIG_SYS_EXT_SERIAL_CLOCK	11059200 /* use external 11.059MHz clk	*/

/*-----------------------------------------------------------------------
 * NVRAM/RTC
 *
 * NOTE: The RTC registers are located at 0x7FFF0 - 0x7FFFF
 * The DS1558 code assumes this condition
 *
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_NVRAM_SIZE	        (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs     */
#define CONFIG_RTC_DS1556	1		         /* DS1556 RTC		*/

/*-----------------------------------------------------------------------
 * Environment
 *----------------------------------------------------------------------*/
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
#else
#define CONFIG_ENV_IS_IN_NAND	1	/* use NAND for environment vars	*/
#define CONFIG_ENV_IS_EMBEDDED	1	/* use embedded environment */
#endif

/*-----------------------------------------------------------------------
 * FLASH related
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_MAX_FLASH_BANKS	3	/* number of banks			*/
#define CONFIG_SYS_MAX_FLASH_SECT	256	/* sectors per device			*/

#undef	CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CONFIG_SYS_FLASH_ADDR0         0x555
#define CONFIG_SYS_FLASH_ADDR1         0x2aa
#define CONFIG_SYS_FLASH_WORD_SIZE     unsigned char

#define CONFIG_SYS_FLASH_2ND_16BIT_DEV 1	/* bamboo has 8 and 16bit device	*/
#define CONFIG_SYS_FLASH_2ND_ADDR      0x87800000  /* bamboo has 8 and 16bit device	*/

#ifdef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE	0x10000	/* size of one complete sector		*/
#define CONFIG_ENV_ADDR		((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
#endif /* CONFIG_ENV_IS_IN_FLASH */

/*
 * IPL (Initial Program Loader, integrated inside CPU)
 * Will load first 4k from NAND (SPL) into cache and execute it from there.
 *
 * SPL (Secondary Program Loader)
 * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
 * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
 * controller and the NAND controller so that the special U-Boot image can be
 * loaded from NAND to SDRAM.
 *
 * NUB (NAND U-Boot)
 * This NAND U-Boot (NUB) is a special U-Boot version which can be started
 * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
 *
 * On 440EPx the SPL is copied to SDRAM before the NAND controller is
 * set up. While still running from cache, I experienced problems accessing
 * the NAND controller.	sr - 2006-08-25
 */
#define CONFIG_SYS_NAND_BOOT_SPL_SRC	0xfffff000	/* SPL location			*/
#define CONFIG_SYS_NAND_BOOT_SPL_SIZE	(4 << 10)	/* SPL size			*/
#define CONFIG_SYS_NAND_BOOT_SPL_DST	0x00800000	/* Copy SPL here		*/
#define CONFIG_SYS_NAND_U_BOOT_DST	0x01000000	/* Load NUB to this addr	*/
#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr	*/
#define CONFIG_SYS_NAND_BOOT_SPL_DELTA	(CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)

/*
 * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
 */
#define CONFIG_SYS_NAND_U_BOOT_OFFS	(16 << 10)	/* Offset to RAM U-Boot image	*/
#define CONFIG_SYS_NAND_U_BOOT_SIZE	(384 << 10)	/* Size of RAM U-Boot image	*/

/*
 * Now the NAND chip has to be defined (no autodetection used!)
 */
#define CONFIG_SYS_NAND_PAGE_SIZE	512		/* NAND chip page size		*/
#define CONFIG_SYS_NAND_BLOCK_SIZE	(16 << 10)	/* NAND chip block size		*/
#define CONFIG_SYS_NAND_PAGE_COUNT	32		/* NAND chip page count		*/
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	5		/* Location of bad block marker	*/
#define CONFIG_SYS_NAND_4_ADDR_CYCLE	1		/* Fourth addr used (>32MB)	*/

#define CONFIG_SYS_NAND_ECCSIZE	256
#define CONFIG_SYS_NAND_ECCBYTES	3
#define CONFIG_SYS_NAND_ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
#define CONFIG_SYS_NAND_OOBSIZE	16
#define CONFIG_SYS_NAND_ECCTOTAL	(CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS)
#define CONFIG_SYS_NAND_ECCPOS		{0, 1, 2, 3, 6, 7}

#ifdef CONFIG_ENV_IS_IN_NAND
/*
 * For NAND booting the environment is embedded in the U-Boot image. Please take
 * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
 */
#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
#define CONFIG_ENV_OFFSET		(CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
#endif

/*-----------------------------------------------------------------------
 * NAND FLASH
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_MAX_NAND_DEVICE	2
#define CONFIG_SYS_NAND_BASE		(CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_ADDR + 2 }
#define CONFIG_SYS_NAND_SELECT_DEVICE  1	/* nand driver supports mutipl. chips	*/

#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_SYS_NAND_CS		1
#else
#define CONFIG_SYS_NAND_CS		0		/* NAND chip connected to CSx	*/
/* Memory Bank 0 (NAND-FLASH) initialization					*/
#define CONFIG_SYS_EBC_PB0AP		0x018003c0
#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_NAND_ADDR | 0x1c000)
#endif

/*-----------------------------------------------------------------------
 * DDR SDRAM
 *----------------------------------------------------------------------------- */
#define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for setup             */
#undef CONFIG_DDR_ECC			/* don't use ECC			*/
#define CONFIG_SYS_SIMULATE_SPD_EEPROM	0xff	/* simulate spd eeprom on this address	*/
#define SPD_EEPROM_ADDRESS	{CONFIG_SYS_SIMULATE_SPD_EEPROM, 0x50, 0x51}
#define CONFIG_SYS_MBYTES_SDRAM	(64)	/* 64MB fixed size for early-sdram-init */
#define CONFIG_PROG_SDRAM_TLB

/*-----------------------------------------------------------------------
 * I2C
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/

#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR	(0xa8>>1)
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10

#ifdef CONFIG_ENV_IS_IN_EEPROM
#define CONFIG_ENV_SIZE		0x200	    /* Size of Environment vars */
#define CONFIG_ENV_OFFSET		0x0
#endif /* CONFIG_ENV_IS_IN_EEPROM */

/*
 * Default environment variables
 */
#define	CONFIG_EXTRA_ENV_SETTINGS					\
	CONFIG_AMCC_DEF_ENV						\
	CONFIG_AMCC_DEF_ENV_POWERPC					\
	CONFIG_AMCC_DEF_ENV_PPC_OLD					\
	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
	CONFIG_AMCC_DEF_ENV_NAND_UPD					\
	"kernel_addr=fff00000\0"					\
	"ramdisk_addr=fff10000\0"					\
	""

#define CONFIG_HAS_ETH0
#define CONFIG_PHY_ADDR		0	/* PHY address, See schematics	*/
#define CONFIG_PHY1_ADDR        1

#ifndef CONFIG_BAMBOO_NAND
#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
#endif /* CONFIG_BAMBOO_NAND */

#ifdef CONFIG_440EP
/* USB */
#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE

/*Comment this out to enable USB 1.1 device*/
#define USB_2_0_DEVICE
#endif /*CONFIG_440EP*/

/*
 * Commands additional to the ones defined in amcc-common.h
 */
#define CONFIG_CMD_DATE
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_PCI
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_SNTP
#define CONFIG_CMD_USB

#ifdef CONFIG_BAMBOO_NAND
#define CONFIG_CMD_NAND
#endif

#define CONFIG_SUPPORT_VFAT

/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
/* General PCI */
#define CONFIG_PCI			/* include pci support	        */
#undef  CONFIG_PCI_PNP			/* do (not) pci plug-and-play   */
#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
#define CONFIG_SYS_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/

/* Board-specific PCI */
#define CONFIG_SYS_PCI_TARGET_INIT
#define CONFIG_SYS_PCI_MASTER_INIT

#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
#define CONFIG_SYS_PCI_SUBSYS_ID       0xcafe	/* Whatever */

#endif	/* __CONFIG_H */
Commit	Line	Data
8a316c9b	1	/*
8b39501d	2	* (C) Copyright 2005-2007
8a316c9b SR	3	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/************************************************************************
	25	* bamboo.h - configuration for BAMBOO board
	26	***********************************************************************/
	27	#ifndef __CONFIG_H
	28	#define __CONFIG_H
	29
	30	/*-----------------------------------------------------------------------
	31	* High Level Configuration Options
	32	----------------------------------------------------------------------/
17f50f22	33	#define CONFIG_BAMBOO 1 /* Board is BAMBOO */
846b0dd2	34	#define CONFIG_440EP 1 /* Specific PPC440EP support */
efa35cf1	35	#define CONFIG_440 1 /* ... PPC440 family */
17f50f22	36	#define CONFIG_4xx 1 /* ... PPC4xx family */
8a316c9b SR	37	#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
8a316c9b SR	38
2ae18241 WD	39	#ifndef CONFIG_SYS_TEXT_BASE
	40	#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
	41	#endif
	42
490f2040 SR	43	/*
	44	* Include common defines/options for all AMCC eval boards
	45	*/
	46	#define CONFIG_HOSTNAME bamboo
	47	#include "amcc-common.h"
	48
c57c7980 SR	49	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
	50
	51	/*
	52	* Please note that, if NAND support is enabled, the 2nd ethernet port
	53	* can't be used because of pin multiplexing. So, if you want to use the
	54	* 2nd ethernet port you have to "undef" the following define.
	55	*/
	56	#define CONFIG_BAMBOO_NAND 1 /* enable nand flash support */
	57
8a316c9b SR	58	/*-----------------------------------------------------------------------
	59	* Base addresses -- Note these are effective addresses where the
	60	* actual resources get mapped (not physical addresses)
	61	----------------------------------------------------------------------/
6d0f6bcf JCPV	62	#define CONFIG_SYS_FLASH_BASE 0xfff00000 /* start of FLASH */
	63	#define CONFIG_SYS_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/
	64	#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
	65	#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
	66	#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
8a316c9b SR	67
8a316c9b SR	68	/Don't change either of these/
550650dd	69	#define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs*/
8a316c9b SR	70	/Don't change either of these/
8a316c9b SR	71
6d0f6bcf JCPV	72	#define CONFIG_SYS_USB_DEVICE 0x50000000
	73	#define CONFIG_SYS_NVRAM_BASE_ADDR 0x80000000
	74	#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
	75	#define CONFIG_SYS_NAND_ADDR 0x90000000
	76	#define CONFIG_SYS_NAND2_ADDR 0x94000000
8a316c9b SR	77
	78	/*-----------------------------------------------------------------------
	79	* Initial RAM & stack pointer (placed in SDRAM)
	80	----------------------------------------------------------------------/
6d0f6bcf JCPV	81	#define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */
6d0f6bcf JCPV	82	#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */
553f0982	83	#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
25ddd1fb	84	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	85	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
8a316c9b	86
8a316c9b SR	87	/*-----------------------------------------------------------------------
	88	* Serial Port
	89	----------------------------------------------------------------------/
550650dd	90	#define CONFIG_CONS_INDEX 1 /* Use UART0 */
6d0f6bcf	91	#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */
8a316c9b	92
8a316c9b SR	93	/*-----------------------------------------------------------------------
	94	* NVRAM/RTC
	95	*
	96	* NOTE: The RTC registers are located at 0x7FFF0 - 0x7FFFF
	97	* The DS1558 code assumes this condition
	98	*
	99	----------------------------------------------------------------------/
6d0f6bcf	100	#define CONFIG_SYS_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */
17f50f22 SR	101	#define CONFIG_RTC_DS1556 1 /* DS1556 RTC */
	102
	103	/*-----------------------------------------------------------------------
	104	* Environment
	105	----------------------------------------------------------------------/
cf959c7d	106	#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
5a1aceb0	107	#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
17f50f22	108	#else
51bfee19	109	#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
0e8d1586	110	#define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */
17f50f22	111	#endif
8a316c9b SR	112
	113	/*-----------------------------------------------------------------------
	114	* FLASH related
	115	----------------------------------------------------------------------/
6d0f6bcf JCPV	116	#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* number of banks */
6d0f6bcf JCPV	117	#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */
8a316c9b	118
6d0f6bcf JCPV	119	#undef CONFIG_SYS_FLASH_CHECKSUM
	120	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	121	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
8a316c9b	122
6d0f6bcf JCPV	123	#define CONFIG_SYS_FLASH_ADDR0 0x555
	124	#define CONFIG_SYS_FLASH_ADDR1 0x2aa
	125	#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char
8a316c9b	126
6d0f6bcf JCPV	127	#define CONFIG_SYS_FLASH_2ND_16BIT_DEV 1 /* bamboo has 8 and 16bit device */
6d0f6bcf JCPV	128	#define CONFIG_SYS_FLASH_2ND_ADDR 0x87800000 /* bamboo has 8 and 16bit device */
8a316c9b	129
5a1aceb0	130	#ifdef CONFIG_ENV_IS_IN_FLASH
0e8d1586	131	#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
6d0f6bcf	132	#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
0e8d1586	133	#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
17f50f22	134
17f50f22	135	/* Address and size of Redundant Environment Sector */
0e8d1586 JCPV	136	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
0e8d1586 JCPV	137	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
5a1aceb0	138	#endif /* CONFIG_ENV_IS_IN_FLASH */
8a316c9b	139
cf959c7d SR	140	/*
	141	* IPL (Initial Program Loader, integrated inside CPU)
	142	* Will load first 4k from NAND (SPL) into cache and execute it from there.
	143	*
	144	* SPL (Secondary Program Loader)
	145	* Will load special U-Boot version (NUB) from NAND and execute it. This SPL
	146	* has to fit into 4kByte. It sets up the CPU and configures the SDRAM
	147	* controller and the NAND controller so that the special U-Boot image can be
	148	* loaded from NAND to SDRAM.
	149	*
	150	* NUB (NAND U-Boot)
	151	* This NAND U-Boot (NUB) is a special U-Boot version which can be started
	152	* from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
	153	*
	154	* On 440EPx the SPL is copied to SDRAM before the NAND controller is
	155	* set up. While still running from cache, I experienced problems accessing
	156	* the NAND controller. sr - 2006-08-25
	157	*/
6d0f6bcf JCPV	158	#define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
	159	#define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
	160	#define CONFIG_SYS_NAND_BOOT_SPL_DST 0x00800000 /* Copy SPL here */
	161	#define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
	162	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr */
	163	#define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
cf959c7d SR	164
	165	/*
	166	* Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
	167	*/
6d0f6bcf JCPV	168	#define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
6d0f6bcf JCPV	169	#define CONFIG_SYS_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
cf959c7d SR	170
	171	/*
	172	* Now the NAND chip has to be defined (no autodetection used!)
	173	*/
6d0f6bcf JCPV	174	#define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */
	175	#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
	176	#define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */
	177	#define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
	178	#define CONFIG_SYS_NAND_4_ADDR_CYCLE 1 /* Fourth addr used (>32MB) */
	179
	180	#define CONFIG_SYS_NAND_ECCSIZE 256
	181	#define CONFIG_SYS_NAND_ECCBYTES 3
	182	#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
	183	#define CONFIG_SYS_NAND_OOBSIZE 16
	184	#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS)
	185	#define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
cf959c7d	186
51bfee19	187	#ifdef CONFIG_ENV_IS_IN_NAND
cf959c7d SR	188	/*
	189	* For NAND booting the environment is embedded in the U-Boot image. Please take
	190	* look at the file board/amcc/sequoia/u-boot-nand.lds for details.
	191	*/
6d0f6bcf JCPV	192	#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
6d0f6bcf JCPV	193	#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
0e8d1586	194	#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
cf959c7d SR	195	#endif
cf959c7d SR	196
c57c7980	197	/*-----------------------------------------------------------------------
8b39501d	198	* NAND FLASH
c57c7980	199	----------------------------------------------------------------------/
6d0f6bcf	200	#define CONFIG_SYS_MAX_NAND_DEVICE 2
6d0f6bcf JCPV	201	#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
	202	#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_ADDR + 2 }
	203	#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
c57c7980	204
cf959c7d	205	#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
6d0f6bcf	206	#define CONFIG_SYS_NAND_CS 1
cf959c7d	207	#else
6d0f6bcf	208	#define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */
cf959c7d	209	/* Memory Bank 0 (NAND-FLASH) initialization */
6d0f6bcf JCPV	210	#define CONFIG_SYS_EBC_PB0AP 0x018003c0
6d0f6bcf JCPV	211	#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR \| 0x1c000)
cf959c7d SR	212	#endif
cf959c7d SR	213
8a316c9b SR	214	/*-----------------------------------------------------------------------
8a316c9b SR	215	* DDR SDRAM
17f50f22 SR	216	----------------------------------------------------------------------------- /
17f50f22 SR	217	#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
fd49bf02	218	#undef CONFIG_DDR_ECC /* don't use ECC */
6d0f6bcf JCPV	219	#define CONFIG_SYS_SIMULATE_SPD_EEPROM 0xff /* simulate spd eeprom on this address */
	220	#define SPD_EEPROM_ADDRESS {CONFIG_SYS_SIMULATE_SPD_EEPROM, 0x50, 0x51}
	221	#define CONFIG_SYS_MBYTES_SDRAM (64) /* 64MB fixed size for early-sdram-init */
d2f68006	222	#define CONFIG_PROG_SDRAM_TLB
8a316c9b SR	223
	224	/*-----------------------------------------------------------------------
	225	* I2C
	226	----------------------------------------------------------------------/
6d0f6bcf	227	#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
8a316c9b	228
6d0f6bcf JCPV	229	#define CONFIG_SYS_I2C_MULTI_EEPROMS
	230	#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
	231	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	232	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	233	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
8a316c9b	234
bb1f8b4f	235	#ifdef CONFIG_ENV_IS_IN_EEPROM
0e8d1586 JCPV	236	#define CONFIG_ENV_SIZE 0x200 /* Size of Environment vars */
0e8d1586 JCPV	237	#define CONFIG_ENV_OFFSET 0x0
bb1f8b4f	238	#endif /* CONFIG_ENV_IS_IN_EEPROM */
17f50f22	239
490f2040 SR	240	/*
	241	* Default environment variables
	242	*/
17f50f22	243	#define CONFIG_EXTRA_ENV_SETTINGS \
490f2040 SR	244	CONFIG_AMCC_DEF_ENV \
	245	CONFIG_AMCC_DEF_ENV_POWERPC \
	246	CONFIG_AMCC_DEF_ENV_PPC_OLD \
	247	CONFIG_AMCC_DEF_ENV_NOR_UPD \
	248	CONFIG_AMCC_DEF_ENV_NAND_UPD \
17f50f22 SR	249	"kernel_addr=fff00000\0" \
17f50f22 SR	250	"ramdisk_addr=fff10000\0" \
17f50f22	251	""
8a316c9b	252
a00eccfe	253	#define CONFIG_HAS_ETH0
17f50f22	254	#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
d6c61aab	255	#define CONFIG_PHY1_ADDR 1
c57c7980 SR	256
c57c7980 SR	257	#ifndef CONFIG_BAMBOO_NAND
8a316c9b	258	#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
c57c7980 SR	259	#endif /* CONFIG_BAMBOO_NAND */
c57c7980 SR	260
846b0dd2	261	#ifdef CONFIG_440EP
8a316c9b SR	262	/* USB */
	263	#define CONFIG_USB_OHCI
	264	#define CONFIG_USB_STORAGE
	265
	266	/Comment this out to enable USB 1.1 device/
	267	#define USB_2_0_DEVICE
846b0dd2	268	#endif /CONFIG_440EP/
8a316c9b	269
80ff4f99	270	/*
490f2040	271	* Commands additional to the ones defined in amcc-common.h
80ff4f99	272	*/
ba2351f9	273	#define CONFIG_CMD_DATE
490f2040 SR	274	#define CONFIG_CMD_EXT2
490f2040 SR	275	#define CONFIG_CMD_FAT
ba2351f9	276	#define CONFIG_CMD_PCI
ba2351f9	277	#define CONFIG_CMD_SDRAM
ba2351f9	278	#define CONFIG_CMD_SNTP
490f2040	279	#define CONFIG_CMD_USB
ba2351f9	280
c57c7980	281	#ifdef CONFIG_BAMBOO_NAND
ba2351f9 JL	282	#define CONFIG_CMD_NAND
ba2351f9 JL	283	#endif
c57c7980	284
3b6748ea SR	285	#define CONFIG_SUPPORT_VFAT
3b6748ea SR	286
490f2040 SR	287	/* Partitions */
	288	#define CONFIG_MAC_PARTITION
	289	#define CONFIG_DOS_PARTITION
	290	#define CONFIG_ISO_PARTITION
193dd958	291
8a316c9b SR	292	/*-----------------------------------------------------------------------
	293	* PCI stuff
	294	*-----------------------------------------------------------------------
	295	*/
	296	/* General PCI */
c57c7980 SR	297	#define CONFIG_PCI /* include pci support */
c57c7980 SR	298	#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
17f50f22	299	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
6d0f6bcf	300	#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
8a316c9b SR	301
8a316c9b SR	302	/* Board-specific PCI */
6d0f6bcf JCPV	303	#define CONFIG_SYS_PCI_TARGET_INIT
6d0f6bcf JCPV	304	#define CONFIG_SYS_PCI_MASTER_INIT
8a316c9b	305
6d0f6bcf JCPV	306	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
6d0f6bcf JCPV	307	#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */
8a316c9b	308
8a316c9b	309	#endif /* __CONFIG_H */