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d1712369 | 1 | /* |
3d7506fa | 2 | * Copyright 2009-2012 Freescale Semiconductor, Inc. |
d1712369 | 3 | * |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
d1712369 KG |
5 | */ |
6 | ||
7 | /* | |
8 | * Corenet DS style board configuration file | |
9 | */ | |
10 | #ifndef __CONFIG_H | |
11 | #define __CONFIG_H | |
12 | ||
15672c6d YS |
13 | #define CONFIG_DISPLAY_BOARDINFO |
14 | ||
d1712369 KG |
15 | #include "../board/freescale/common/ics307_clk.h" |
16 | ||
2a9fab82 | 17 | #ifdef CONFIG_RAMBOOT_PBL |
467a40df AB |
18 | #ifdef CONFIG_SECURE_BOOT |
19 | #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE | |
20 | #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc | |
21 | #ifdef CONFIG_NAND | |
22 | #define CONFIG_RAMBOOT_NAND | |
23 | #endif | |
5050f6f0 | 24 | #define CONFIG_BOOTSCRIPT_COPY_RAM |
467a40df | 25 | #else |
2a9fab82 SX |
26 | #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE |
27 | #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc | |
e4536f8e | 28 | #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg |
5d898a00 | 29 | #if defined(CONFIG_P3041DS) |
e4536f8e | 30 | #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg |
5d898a00 | 31 | #elif defined(CONFIG_P4080DS) |
e4536f8e | 32 | #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg |
5d898a00 | 33 | #elif defined(CONFIG_P5020DS) |
e4536f8e | 34 | #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg |
94025b1c | 35 | #elif defined(CONFIG_P5040DS) |
e4536f8e | 36 | #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg |
5d898a00 | 37 | #endif |
2a9fab82 | 38 | #endif |
467a40df | 39 | #endif |
2a9fab82 | 40 | |
461632bd | 41 | #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE |
292dc6c5 | 42 | /* Set 1M boot space */ |
461632bd LG |
43 | #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) |
44 | #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ | |
45 | (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) | |
292dc6c5 LG |
46 | #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc |
47 | #define CONFIG_SYS_NO_FLASH | |
48 | #endif | |
49 | ||
d1712369 KG |
50 | /* High Level Configuration Options */ |
51 | #define CONFIG_BOOKE | |
52 | #define CONFIG_E500 /* BOOKE e500 family */ | |
53 | #define CONFIG_E500MC /* BOOKE e500mc family */ | |
54 | #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ | |
d1712369 KG |
55 | #define CONFIG_MP /* support multiple processors */ |
56 | ||
ed179152 | 57 | #ifndef CONFIG_SYS_TEXT_BASE |
e222b1f3 | 58 | #define CONFIG_SYS_TEXT_BASE 0xeff40000 |
ed179152 KG |
59 | #endif |
60 | ||
7a577fda KG |
61 | #ifndef CONFIG_RESET_VECTOR_ADDRESS |
62 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc | |
63 | #endif | |
64 | ||
d1712369 KG |
65 | #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ |
66 | #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS | |
67 | #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ | |
737537ef | 68 | #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ |
d1712369 KG |
69 | #define CONFIG_PCI /* Enable PCI/PCIE */ |
70 | #define CONFIG_PCIE1 /* PCIE controler 1 */ | |
71 | #define CONFIG_PCIE2 /* PCIE controler 2 */ | |
d1712369 KG |
72 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ |
73 | #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ | |
d1712369 | 74 | |
d1712369 KG |
75 | #define CONFIG_FSL_LAW /* Use common FSL init code */ |
76 | ||
77 | #define CONFIG_ENV_OVERWRITE | |
78 | ||
79 | #ifdef CONFIG_SYS_NO_FLASH | |
461632bd | 80 | #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) |
d1712369 | 81 | #define CONFIG_ENV_IS_NOWHERE |
0a85a9e7 | 82 | #endif |
d1712369 | 83 | #else |
d1712369 KG |
84 | #define CONFIG_FLASH_CFI_DRIVER |
85 | #define CONFIG_SYS_FLASH_CFI | |
80e5c83a | 86 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
be827c7a SX |
87 | #endif |
88 | ||
89 | #if defined(CONFIG_SPIFLASH) | |
90 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
91 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
92 | #define CONFIG_ENV_SPI_BUS 0 | |
93 | #define CONFIG_ENV_SPI_CS 0 | |
94 | #define CONFIG_ENV_SPI_MAX_HZ 10000000 | |
95 | #define CONFIG_ENV_SPI_MODE 0 | |
96 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ | |
97 | #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ | |
98 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
99 | #elif defined(CONFIG_SDCARD) | |
100 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
101 | #define CONFIG_ENV_IS_IN_MMC | |
4394d0c2 | 102 | #define CONFIG_FSL_FIXED_MMC_LOCATION |
be827c7a SX |
103 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
104 | #define CONFIG_ENV_SIZE 0x2000 | |
e222b1f3 | 105 | #define CONFIG_ENV_OFFSET (512 * 1658) |
374a235d SX |
106 | #elif defined(CONFIG_NAND) |
107 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
108 | #define CONFIG_ENV_IS_IN_NAND | |
109 | #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE | |
e222b1f3 | 110 | #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) |
461632bd | 111 | #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) |
0a85a9e7 LG |
112 | #define CONFIG_ENV_IS_IN_REMOTE |
113 | #define CONFIG_ENV_ADDR 0xffe20000 | |
114 | #define CONFIG_ENV_SIZE 0x2000 | |
fd0451e4 LG |
115 | #elif defined(CONFIG_ENV_IS_NOWHERE) |
116 | #define CONFIG_ENV_SIZE 0x2000 | |
be827c7a SX |
117 | #else |
118 | #define CONFIG_ENV_IS_IN_FLASH | |
2a9fab82 | 119 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
be827c7a SX |
120 | #define CONFIG_ENV_SIZE 0x2000 |
121 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
d1712369 KG |
122 | #endif |
123 | ||
124 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ | |
d1712369 KG |
125 | |
126 | /* | |
127 | * These can be toggled for performance analysis, otherwise use default. | |
128 | */ | |
129 | #define CONFIG_SYS_CACHE_STASHING | |
130 | #define CONFIG_BACKSIDE_L2_CACHE | |
131 | #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E | |
132 | #define CONFIG_BTB /* toggle branch predition */ | |
8ed20f2c | 133 | #define CONFIG_DDR_ECC |
d1712369 KG |
134 | #ifdef CONFIG_DDR_ECC |
135 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
136 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef | |
137 | #endif | |
138 | ||
139 | #define CONFIG_ENABLE_36BIT_PHYS | |
140 | ||
141 | #ifdef CONFIG_PHYS_64BIT | |
142 | #define CONFIG_ADDR_MAP | |
143 | #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ | |
144 | #endif | |
145 | ||
4672e1ea | 146 | #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ |
d1712369 KG |
147 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ |
148 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
149 | #define CONFIG_SYS_ALT_MEMTEST | |
150 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ | |
151 | ||
2a9fab82 SX |
152 | /* |
153 | * Config the L3 Cache as L3 SRAM | |
154 | */ | |
155 | #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE | |
156 | #ifdef CONFIG_PHYS_64BIT | |
157 | #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) | |
158 | #else | |
159 | #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR | |
160 | #endif | |
161 | #define CONFIG_SYS_L3_SIZE (1024 << 10) | |
162 | #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) | |
163 | ||
d1712369 KG |
164 | #ifdef CONFIG_PHYS_64BIT |
165 | #define CONFIG_SYS_DCSRBAR 0xf0000000 | |
166 | #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull | |
167 | #endif | |
168 | ||
169 | /* EEPROM */ | |
170 | #define CONFIG_ID_EEPROM | |
171 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
172 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 | |
173 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
174 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
175 | ||
176 | /* | |
177 | * DDR Setup | |
178 | */ | |
179 | #define CONFIG_VERY_BIG_RAM | |
180 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
181 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
182 | ||
183 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
90870d98 | 184 | #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) |
d1712369 KG |
185 | |
186 | #define CONFIG_DDR_SPD | |
5614e71b | 187 | #define CONFIG_SYS_FSL_DDR3 |
d1712369 | 188 | |
d1712369 KG |
189 | #define CONFIG_SYS_SPD_BUS_NUM 1 |
190 | #define SPD_EEPROM_ADDRESS1 0x51 | |
191 | #define SPD_EEPROM_ADDRESS2 0x52 | |
e02aea61 | 192 | #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ |
28a96671 | 193 | #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ |
d1712369 KG |
194 | |
195 | /* | |
196 | * Local Bus Definitions | |
197 | */ | |
198 | ||
199 | /* Set the local bus clock 1/8 of platform clock */ | |
200 | #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 | |
201 | ||
202 | #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */ | |
203 | #ifdef CONFIG_PHYS_64BIT | |
204 | #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull | |
205 | #else | |
206 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE | |
207 | #endif | |
208 | ||
374a235d | 209 | #define CONFIG_SYS_FLASH_BR_PRELIM \ |
7ee41107 | 210 | (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \ |
374a235d SX |
211 | | BR_PS_16 | BR_V) |
212 | #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ | |
d1712369 KG |
213 | | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) |
214 | ||
215 | #define CONFIG_SYS_BR1_PRELIM \ | |
216 | (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) | |
217 | #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 | |
218 | ||
d1712369 KG |
219 | #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ |
220 | #ifdef CONFIG_PHYS_64BIT | |
221 | #define PIXIS_BASE_PHYS 0xfffdf0000ull | |
222 | #else | |
223 | #define PIXIS_BASE_PHYS PIXIS_BASE | |
224 | #endif | |
225 | ||
226 | #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) | |
227 | #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ | |
228 | ||
229 | #define PIXIS_LBMAP_SWITCH 7 | |
230 | #define PIXIS_LBMAP_MASK 0xf0 | |
231 | #define PIXIS_LBMAP_SHIFT 4 | |
232 | #define PIXIS_LBMAP_ALTBANK 0x40 | |
233 | ||
234 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
235 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
236 | ||
237 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ | |
238 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
239 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
240 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
241 | ||
14d0a02a | 242 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
d1712369 | 243 | |
2a9fab82 SX |
244 | #if defined(CONFIG_RAMBOOT_PBL) |
245 | #define CONFIG_SYS_RAMBOOT | |
246 | #endif | |
247 | ||
e02aea61 | 248 | /* Nand Flash */ |
e02aea61 KG |
249 | #ifdef CONFIG_NAND_FSL_ELBC |
250 | #define CONFIG_SYS_NAND_BASE 0xffa00000 | |
251 | #ifdef CONFIG_PHYS_64BIT | |
252 | #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull | |
253 | #else | |
254 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE | |
255 | #endif | |
256 | ||
257 | #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} | |
258 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
e02aea61 KG |
259 | #define CONFIG_CMD_NAND |
260 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
261 | ||
262 | /* NAND flash config */ | |
263 | #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
264 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | |
265 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
266 | | BR_MS_FCM /* MSEL = FCM */ \ | |
267 | | BR_V) /* valid */ | |
268 | #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ | |
269 | | OR_FCM_PGS /* Large Page*/ \ | |
270 | | OR_FCM_CSCT \ | |
271 | | OR_FCM_CST \ | |
272 | | OR_FCM_CHT \ | |
273 | | OR_FCM_SCY_1 \ | |
274 | | OR_FCM_TRLX \ | |
275 | | OR_FCM_EHTR) | |
276 | ||
374a235d SX |
277 | #ifdef CONFIG_NAND |
278 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ | |
279 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ | |
280 | #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ | |
281 | #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ | |
282 | #else | |
283 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ | |
284 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ | |
285 | #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ | |
286 | #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ | |
287 | #endif | |
374a235d SX |
288 | #else |
289 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ | |
290 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ | |
c6d33901 | 291 | #endif /* CONFIG_NAND_FSL_ELBC */ |
e02aea61 | 292 | |
d1712369 KG |
293 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
294 | #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 | |
295 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} | |
296 | ||
297 | #define CONFIG_BOARD_EARLY_INIT_F | |
298 | #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ | |
299 | #define CONFIG_MISC_INIT_R | |
300 | ||
301 | #define CONFIG_HWCONFIG | |
302 | ||
303 | /* define to use L1 as initial stack */ | |
304 | #define CONFIG_L1_INIT_RAM | |
305 | #define CONFIG_SYS_INIT_RAM_LOCK | |
306 | #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ | |
307 | #ifdef CONFIG_PHYS_64BIT | |
308 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf | |
309 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR | |
310 | /* The assembler doesn't like typecast */ | |
311 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ | |
312 | ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ | |
313 | CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) | |
314 | #else | |
315 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ | |
316 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 | |
317 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS | |
318 | #endif | |
553f0982 | 319 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ |
d1712369 | 320 | |
25ddd1fb | 321 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
d1712369 KG |
322 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
323 | ||
9307cbab | 324 | #define CONFIG_SYS_MONITOR_LEN (768 * 1024) |
d1712369 KG |
325 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ |
326 | ||
327 | /* Serial Port - controlled on board with jumper J8 | |
328 | * open - index 2 | |
329 | * shorted - index 1 | |
330 | */ | |
331 | #define CONFIG_CONS_INDEX 1 | |
332 | #define CONFIG_SYS_NS16550 | |
333 | #define CONFIG_SYS_NS16550_SERIAL | |
334 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
335 | #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) | |
336 | ||
337 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
338 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
339 | ||
340 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) | |
341 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) | |
342 | #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) | |
343 | #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) | |
344 | ||
345 | /* Use the HUSH parser */ | |
346 | #define CONFIG_SYS_HUSH_PARSER | |
d1712369 KG |
347 | |
348 | /* pass open firmware flat tree */ | |
349 | #define CONFIG_OF_LIBFDT | |
350 | #define CONFIG_OF_BOARD_SETUP | |
351 | #define CONFIG_OF_STDOUT_VIA_ALIAS | |
352 | ||
353 | /* new uImage format support */ | |
354 | #define CONFIG_FIT | |
355 | #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ | |
356 | ||
357 | /* I2C */ | |
00f792e0 HS |
358 | #define CONFIG_SYS_I2C |
359 | #define CONFIG_SYS_I2C_FSL | |
360 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
361 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
362 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 | |
363 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
364 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
365 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 | |
d1712369 KG |
366 | |
367 | /* | |
368 | * RapidIO | |
369 | */ | |
a09b9b68 | 370 | #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 |
d1712369 | 371 | #ifdef CONFIG_PHYS_64BIT |
a09b9b68 | 372 | #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull |
d1712369 | 373 | #else |
a09b9b68 | 374 | #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 |
d1712369 | 375 | #endif |
a09b9b68 | 376 | #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ |
d1712369 | 377 | |
a09b9b68 | 378 | #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 |
d1712369 | 379 | #ifdef CONFIG_PHYS_64BIT |
a09b9b68 | 380 | #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull |
d1712369 | 381 | #else |
a09b9b68 | 382 | #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 |
d1712369 | 383 | #endif |
a09b9b68 | 384 | #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ |
d1712369 | 385 | |
5ffa88ec LG |
386 | /* |
387 | * for slave u-boot IMAGE instored in master memory space, | |
388 | * PHYS must be aligned based on the SIZE | |
389 | */ | |
e4911815 LG |
390 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull |
391 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull | |
392 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ | |
393 | #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull | |
3f1af81b | 394 | /* |
ff65f126 | 395 | * for slave UCODE and ENV instored in master memory space, |
3f1af81b LG |
396 | * PHYS must be aligned based on the SIZE |
397 | */ | |
e4911815 | 398 | #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull |
b5f7c873 LG |
399 | #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull |
400 | #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ | |
ff65f126 | 401 | |
5056c8e0 | 402 | /* slave core release by master*/ |
b5f7c873 LG |
403 | #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 |
404 | #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ | |
5ffa88ec | 405 | |
292dc6c5 | 406 | /* |
461632bd | 407 | * SRIO_PCIE_BOOT - SLAVE |
292dc6c5 | 408 | */ |
461632bd LG |
409 | #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE |
410 | #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 | |
411 | #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ | |
412 | (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) | |
292dc6c5 LG |
413 | #endif |
414 | ||
2dd3095d SX |
415 | /* |
416 | * eSPI - Enhanced SPI | |
417 | */ | |
418 | #define CONFIG_FSL_ESPI | |
2dd3095d SX |
419 | #define CONFIG_SPI_FLASH_SPANSION |
420 | #define CONFIG_CMD_SF | |
421 | #define CONFIG_SF_DEFAULT_SPEED 10000000 | |
422 | #define CONFIG_SF_DEFAULT_MODE 0 | |
423 | ||
d1712369 KG |
424 | /* |
425 | * General PCI | |
426 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
427 | */ | |
428 | ||
429 | /* controller 1, direct to uli, tgtid 3, Base address 20000 */ | |
430 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 | |
431 | #ifdef CONFIG_PHYS_64BIT | |
432 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 | |
433 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull | |
434 | #else | |
435 | #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 | |
436 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 | |
437 | #endif | |
438 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ | |
439 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 | |
440 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
441 | #ifdef CONFIG_PHYS_64BIT | |
442 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull | |
443 | #else | |
444 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 | |
445 | #endif | |
446 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ | |
447 | ||
448 | /* controller 2, Slot 2, tgtid 2, Base address 201000 */ | |
449 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 | |
450 | #ifdef CONFIG_PHYS_64BIT | |
451 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 | |
452 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull | |
453 | #else | |
454 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 | |
455 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 | |
456 | #endif | |
457 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ | |
458 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 | |
459 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
460 | #ifdef CONFIG_PHYS_64BIT | |
461 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull | |
462 | #else | |
463 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 | |
464 | #endif | |
465 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ | |
466 | ||
467 | /* controller 3, Slot 1, tgtid 1, Base address 202000 */ | |
02bb4989 | 468 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 |
d1712369 KG |
469 | #ifdef CONFIG_PHYS_64BIT |
470 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 | |
471 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull | |
472 | #else | |
473 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 | |
474 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 | |
475 | #endif | |
476 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ | |
477 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 | |
478 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 | |
479 | #ifdef CONFIG_PHYS_64BIT | |
480 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull | |
481 | #else | |
482 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 | |
483 | #endif | |
484 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ | |
485 | ||
1bf8e9fd KG |
486 | /* controller 4, Base address 203000 */ |
487 | #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 | |
488 | #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull | |
489 | #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ | |
490 | #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 | |
491 | #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull | |
492 | #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ | |
493 | ||
d1712369 | 494 | /* Qman/Bman */ |
24995d82 | 495 | #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ |
d1712369 KG |
496 | #define CONFIG_SYS_BMAN_NUM_PORTALS 10 |
497 | #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 | |
498 | #ifdef CONFIG_PHYS_64BIT | |
499 | #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull | |
500 | #else | |
501 | #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE | |
502 | #endif | |
503 | #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 | |
3fa66db4 JL |
504 | #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 |
505 | #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 | |
506 | #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE | |
507 | #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) | |
508 | #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ | |
509 | CONFIG_SYS_BMAN_CENA_SIZE) | |
510 | #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) | |
511 | #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 | |
d1712369 KG |
512 | #define CONFIG_SYS_QMAN_NUM_PORTALS 10 |
513 | #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 | |
514 | #ifdef CONFIG_PHYS_64BIT | |
515 | #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull | |
516 | #else | |
517 | #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE | |
518 | #endif | |
519 | #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 | |
3fa66db4 JL |
520 | #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 |
521 | #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 | |
522 | #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE | |
523 | #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) | |
524 | #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ | |
525 | CONFIG_SYS_QMAN_CENA_SIZE) | |
526 | #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) | |
527 | #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 | |
d1712369 KG |
528 | |
529 | #define CONFIG_SYS_DPAA_FMAN | |
530 | #define CONFIG_SYS_DPAA_PME | |
531 | /* Default address of microcode for the Linux Fman driver */ | |
ffadc441 TT |
532 | #if defined(CONFIG_SPIFLASH) |
533 | /* | |
534 | * env is stored at 0x100000, sector size is 0x10000, ucode is stored after | |
535 | * env, so we got 0x110000. | |
536 | */ | |
f2717b47 | 537 | #define CONFIG_SYS_QE_FW_IN_SPIFLASH |
dcf1d774 | 538 | #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 |
ffadc441 TT |
539 | #elif defined(CONFIG_SDCARD) |
540 | /* | |
541 | * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is | |
e222b1f3 PK |
542 | * about 825KB (1650 blocks), Env is stored after the image, and the env size is |
543 | * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. | |
ffadc441 | 544 | */ |
f2717b47 | 545 | #define CONFIG_SYS_QE_FMAN_FW_IN_MMC |
dcf1d774 | 546 | #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) |
ffadc441 | 547 | #elif defined(CONFIG_NAND) |
f2717b47 | 548 | #define CONFIG_SYS_QE_FMAN_FW_IN_NAND |
dcf1d774 | 549 | #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) |
461632bd | 550 | #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) |
292dc6c5 LG |
551 | /* |
552 | * Slave has no ucode locally, it can fetch this from remote. When implementing | |
553 | * in two corenet boards, slave's ucode could be stored in master's memory | |
554 | * space, the address can be mapped from slave TLB->slave LAW-> | |
461632bd LG |
555 | * slave SRIO or PCIE outbound window->master inbound window-> |
556 | * master LAW->the ucode address in master's memory space. | |
292dc6c5 LG |
557 | */ |
558 | #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE | |
dcf1d774 | 559 | #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 |
d1712369 | 560 | #else |
f2717b47 | 561 | #define CONFIG_SYS_QE_FMAN_FW_IN_NOR |
dcf1d774 | 562 | #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 |
d1712369 | 563 | #endif |
f2717b47 TT |
564 | #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 |
565 | #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) | |
d1712369 KG |
566 | |
567 | #ifdef CONFIG_SYS_DPAA_FMAN | |
568 | #define CONFIG_FMAN_ENET | |
2915609a AF |
569 | #define CONFIG_PHYLIB_10G |
570 | #define CONFIG_PHY_VITESSE | |
571 | #define CONFIG_PHY_TERANETICS | |
d1712369 KG |
572 | #endif |
573 | ||
574 | #ifdef CONFIG_PCI | |
842033e6 | 575 | #define CONFIG_PCI_INDIRECT_BRIDGE |
d1712369 | 576 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
d1712369 | 577 | |
d1712369 KG |
578 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
579 | #define CONFIG_DOS_PARTITION | |
580 | #endif /* CONFIG_PCI */ | |
581 | ||
582 | /* SATA */ | |
583 | #ifdef CONFIG_FSL_SATA_V2 | |
584 | #define CONFIG_LIBATA | |
585 | #define CONFIG_FSL_SATA | |
586 | ||
587 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 | |
588 | #define CONFIG_SATA1 | |
589 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR | |
590 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
591 | #define CONFIG_SATA2 | |
592 | #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR | |
593 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
594 | ||
595 | #define CONFIG_LBA48 | |
596 | #define CONFIG_CMD_SATA | |
597 | #define CONFIG_DOS_PARTITION | |
598 | #define CONFIG_CMD_EXT2 | |
599 | #endif | |
600 | ||
601 | #ifdef CONFIG_FMAN_ENET | |
602 | #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c | |
603 | #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d | |
604 | #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e | |
605 | #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f | |
606 | #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 | |
607 | ||
d1712369 KG |
608 | #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c |
609 | #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d | |
610 | #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e | |
611 | #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f | |
612 | #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0 | |
d1712369 KG |
613 | |
614 | #define CONFIG_SYS_TBIPA_VALUE 8 | |
615 | #define CONFIG_MII /* MII PHY management */ | |
616 | #define CONFIG_ETHPRIME "FM1@DTSEC1" | |
617 | #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ | |
618 | #endif | |
619 | ||
620 | /* | |
621 | * Environment | |
622 | */ | |
d1712369 KG |
623 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ |
624 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ | |
625 | ||
626 | /* | |
627 | * Command line configuration. | |
628 | */ | |
a000b795 | 629 | #define CONFIG_CMD_DHCP |
d1712369 | 630 | #define CONFIG_CMD_ERRATA |
a000b795 | 631 | #define CONFIG_CMD_GREPENV |
d1712369 KG |
632 | #define CONFIG_CMD_IRQ |
633 | #define CONFIG_CMD_I2C | |
634 | #define CONFIG_CMD_MII | |
635 | #define CONFIG_CMD_PING | |
9570cbda | 636 | #define CONFIG_CMD_REGINFO |
d1712369 KG |
637 | |
638 | #ifdef CONFIG_PCI | |
639 | #define CONFIG_CMD_PCI | |
d1712369 KG |
640 | #endif |
641 | ||
642 | /* | |
643 | * USB | |
644 | */ | |
3d7506fa | 645 | #define CONFIG_HAS_FSL_DR_USB |
646 | #define CONFIG_HAS_FSL_MPH_USB | |
647 | ||
648 | #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) | |
d1712369 KG |
649 | #define CONFIG_CMD_USB |
650 | #define CONFIG_USB_STORAGE | |
651 | #define CONFIG_USB_EHCI | |
652 | #define CONFIG_USB_EHCI_FSL | |
653 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
654 | #define CONFIG_CMD_EXT2 | |
3d7506fa | 655 | #endif |
d1712369 | 656 | |
d1712369 KG |
657 | #ifdef CONFIG_MMC |
658 | #define CONFIG_FSL_ESDHC | |
659 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR | |
660 | #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT | |
661 | #define CONFIG_CMD_MMC | |
662 | #define CONFIG_GENERIC_MMC | |
663 | #define CONFIG_CMD_EXT2 | |
664 | #define CONFIG_CMD_FAT | |
665 | #define CONFIG_DOS_PARTITION | |
666 | #endif | |
667 | ||
737537ef RG |
668 | /* Hash command with SHA acceleration supported in hardware */ |
669 | #ifdef CONFIG_FSL_CAAM | |
670 | #define CONFIG_CMD_HASH | |
671 | #define CONFIG_SHA_HW_ACCEL | |
672 | #endif | |
673 | ||
d1712369 KG |
674 | /* |
675 | * Miscellaneous configurable options | |
676 | */ | |
677 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
678 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ | |
679 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
680 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
d1712369 KG |
681 | #ifdef CONFIG_CMD_KGDB |
682 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
683 | #else | |
684 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
685 | #endif | |
686 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
687 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
688 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
d1712369 KG |
689 | |
690 | /* | |
691 | * For booting Linux, the board info and command line data | |
a832ac41 | 692 | * have to be in the first 64 MB of memory, since this is |
d1712369 KG |
693 | * the maximum mapped by the Linux kernel during initialization. |
694 | */ | |
a832ac41 KG |
695 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ |
696 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
d1712369 | 697 | |
d1712369 KG |
698 | #ifdef CONFIG_CMD_KGDB |
699 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
d1712369 KG |
700 | #endif |
701 | ||
702 | /* | |
703 | * Environment Configuration | |
704 | */ | |
8b3637c6 | 705 | #define CONFIG_ROOTPATH "/opt/nfsroot" |
b3f44c21 | 706 | #define CONFIG_BOOTFILE "uImage" |
d1712369 KG |
707 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ |
708 | ||
709 | /* default location for tftp and bootm */ | |
710 | #define CONFIG_LOADADDR 1000000 | |
711 | ||
712 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
713 | ||
714 | #define CONFIG_BAUDRATE 115200 | |
715 | ||
055ce080 | 716 | #ifdef CONFIG_P4080DS |
68d4230c RM |
717 | #define __USB_PHY_TYPE ulpi |
718 | #else | |
719 | #define __USB_PHY_TYPE utmi | |
720 | #endif | |
721 | ||
d1712369 | 722 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
c2b3b640 | 723 | "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ |
68d4230c | 724 | "bank_intlv=cs0_cs1;" \ |
55964bb6 | 725 | "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ |
726 | "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ | |
d1712369 | 727 | "netdev=eth0\0" \ |
5368c55d MV |
728 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ |
729 | "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ | |
c2b3b640 EM |
730 | "tftpflash=tftpboot $loadaddr $uboot && " \ |
731 | "protect off $ubootaddr +$filesize && " \ | |
732 | "erase $ubootaddr +$filesize && " \ | |
733 | "cp.b $loadaddr $ubootaddr $filesize && " \ | |
734 | "protect on $ubootaddr +$filesize && " \ | |
735 | "cmp.b $loadaddr $ubootaddr $filesize\0" \ | |
d1712369 KG |
736 | "consoledev=ttyS0\0" \ |
737 | "ramdiskaddr=2000000\0" \ | |
738 | "ramdiskfile=p4080ds/ramdisk.uboot\0" \ | |
739 | "fdtaddr=c00000\0" \ | |
740 | "fdtfile=p4080ds/p4080ds.dtb\0" \ | |
3246584d | 741 | "bdev=sda3\0" |
d1712369 KG |
742 | |
743 | #define CONFIG_HDBOOT \ | |
744 | "setenv bootargs root=/dev/$bdev rw " \ | |
745 | "console=$consoledev,$baudrate $othbootargs;" \ | |
746 | "tftp $loadaddr $bootfile;" \ | |
747 | "tftp $fdtaddr $fdtfile;" \ | |
748 | "bootm $loadaddr - $fdtaddr" | |
749 | ||
750 | #define CONFIG_NFSBOOTCOMMAND \ | |
751 | "setenv bootargs root=/dev/nfs rw " \ | |
752 | "nfsroot=$serverip:$rootpath " \ | |
753 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
754 | "console=$consoledev,$baudrate $othbootargs;" \ | |
755 | "tftp $loadaddr $bootfile;" \ | |
756 | "tftp $fdtaddr $fdtfile;" \ | |
757 | "bootm $loadaddr - $fdtaddr" | |
758 | ||
759 | #define CONFIG_RAMBOOTCOMMAND \ | |
760 | "setenv bootargs root=/dev/ram rw " \ | |
761 | "console=$consoledev,$baudrate $othbootargs;" \ | |
762 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
763 | "tftp $loadaddr $bootfile;" \ | |
764 | "tftp $fdtaddr $fdtfile;" \ | |
765 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
766 | ||
767 | #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT | |
768 | ||
7065b7d4 | 769 | #include <asm/fsl_secure_boot.h> |
7065b7d4 | 770 | |
789490b6 RG |
771 | #ifdef CONFIG_SECURE_BOOT |
772 | #define CONFIG_CMD_BLOB | |
773 | #endif | |
774 | ||
d1712369 | 775 | #endif /* __CONFIG_H */ |