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d1712369 | 1 | /* |
a09b9b68 | 2 | * Copyright 2009-2011 Freescale Semiconductor, Inc. |
d1712369 KG |
3 | * |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | /* | |
24 | * Corenet DS style board configuration file | |
25 | */ | |
26 | #ifndef __CONFIG_H | |
27 | #define __CONFIG_H | |
28 | ||
29 | #include "../board/freescale/common/ics307_clk.h" | |
30 | ||
2a9fab82 SX |
31 | #ifdef CONFIG_RAMBOOT_PBL |
32 | #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE | |
33 | #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc | |
34 | #endif | |
35 | ||
d1712369 KG |
36 | /* High Level Configuration Options */ |
37 | #define CONFIG_BOOKE | |
38 | #define CONFIG_E500 /* BOOKE e500 family */ | |
39 | #define CONFIG_E500MC /* BOOKE e500mc family */ | |
40 | #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ | |
41 | #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ | |
42 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ | |
43 | #define CONFIG_MP /* support multiple processors */ | |
44 | ||
ed179152 KG |
45 | #ifndef CONFIG_SYS_TEXT_BASE |
46 | #define CONFIG_SYS_TEXT_BASE 0xeff80000 | |
47 | #endif | |
48 | ||
7a577fda KG |
49 | #ifndef CONFIG_RESET_VECTOR_ADDRESS |
50 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc | |
51 | #endif | |
52 | ||
d1712369 KG |
53 | #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ |
54 | #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS | |
55 | #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ | |
56 | #define CONFIG_PCI /* Enable PCI/PCIE */ | |
57 | #define CONFIG_PCIE1 /* PCIE controler 1 */ | |
58 | #define CONFIG_PCIE2 /* PCIE controler 2 */ | |
d1712369 KG |
59 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ |
60 | #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ | |
d1712369 | 61 | |
a09b9b68 | 62 | #define CONFIG_SYS_SRIO |
d1712369 KG |
63 | #define CONFIG_SRIO1 /* SRIO port 1 */ |
64 | #define CONFIG_SRIO2 /* SRIO port 2 */ | |
65 | ||
66 | #define CONFIG_FSL_LAW /* Use common FSL init code */ | |
67 | ||
68 | #define CONFIG_ENV_OVERWRITE | |
69 | ||
70 | #ifdef CONFIG_SYS_NO_FLASH | |
71 | #define CONFIG_ENV_IS_NOWHERE | |
72 | #else | |
d1712369 KG |
73 | #define CONFIG_FLASH_CFI_DRIVER |
74 | #define CONFIG_SYS_FLASH_CFI | |
80e5c83a | 75 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
be827c7a SX |
76 | #endif |
77 | ||
78 | #if defined(CONFIG_SPIFLASH) | |
79 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
80 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
81 | #define CONFIG_ENV_SPI_BUS 0 | |
82 | #define CONFIG_ENV_SPI_CS 0 | |
83 | #define CONFIG_ENV_SPI_MAX_HZ 10000000 | |
84 | #define CONFIG_ENV_SPI_MODE 0 | |
85 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ | |
86 | #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ | |
87 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
88 | #elif defined(CONFIG_SDCARD) | |
89 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
90 | #define CONFIG_ENV_IS_IN_MMC | |
91 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
92 | #define CONFIG_ENV_SIZE 0x2000 | |
93 | #define CONFIG_ENV_OFFSET (512 * 1097) | |
374a235d SX |
94 | #elif defined(CONFIG_NAND) |
95 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
96 | #define CONFIG_ENV_IS_IN_NAND | |
97 | #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE | |
98 | #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) | |
be827c7a SX |
99 | #else |
100 | #define CONFIG_ENV_IS_IN_FLASH | |
2a9fab82 | 101 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
be827c7a SX |
102 | #define CONFIG_ENV_SIZE 0x2000 |
103 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
d1712369 KG |
104 | #endif |
105 | ||
106 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ | |
d1712369 KG |
107 | |
108 | /* | |
109 | * These can be toggled for performance analysis, otherwise use default. | |
110 | */ | |
111 | #define CONFIG_SYS_CACHE_STASHING | |
112 | #define CONFIG_BACKSIDE_L2_CACHE | |
113 | #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E | |
114 | #define CONFIG_BTB /* toggle branch predition */ | |
8ed20f2c | 115 | #define CONFIG_DDR_ECC |
d1712369 KG |
116 | #ifdef CONFIG_DDR_ECC |
117 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
118 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef | |
119 | #endif | |
120 | ||
121 | #define CONFIG_ENABLE_36BIT_PHYS | |
122 | ||
123 | #ifdef CONFIG_PHYS_64BIT | |
124 | #define CONFIG_ADDR_MAP | |
125 | #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ | |
126 | #endif | |
127 | ||
4672e1ea | 128 | #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ |
d1712369 KG |
129 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ |
130 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
131 | #define CONFIG_SYS_ALT_MEMTEST | |
132 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ | |
133 | ||
2a9fab82 SX |
134 | /* |
135 | * Config the L3 Cache as L3 SRAM | |
136 | */ | |
137 | #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE | |
138 | #ifdef CONFIG_PHYS_64BIT | |
139 | #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) | |
140 | #else | |
141 | #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR | |
142 | #endif | |
143 | #define CONFIG_SYS_L3_SIZE (1024 << 10) | |
144 | #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) | |
145 | ||
d1712369 KG |
146 | #ifdef CONFIG_PHYS_64BIT |
147 | #define CONFIG_SYS_DCSRBAR 0xf0000000 | |
148 | #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull | |
149 | #endif | |
150 | ||
151 | /* EEPROM */ | |
152 | #define CONFIG_ID_EEPROM | |
153 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
154 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 | |
155 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
156 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
157 | ||
158 | /* | |
159 | * DDR Setup | |
160 | */ | |
161 | #define CONFIG_VERY_BIG_RAM | |
162 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
163 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
164 | ||
165 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
90870d98 | 166 | #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) |
d1712369 KG |
167 | |
168 | #define CONFIG_DDR_SPD | |
169 | #define CONFIG_FSL_DDR3 | |
170 | ||
d1712369 KG |
171 | #define CONFIG_SYS_SPD_BUS_NUM 1 |
172 | #define SPD_EEPROM_ADDRESS1 0x51 | |
173 | #define SPD_EEPROM_ADDRESS2 0x52 | |
e02aea61 | 174 | #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ |
28a96671 | 175 | #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ |
d1712369 KG |
176 | |
177 | /* | |
178 | * Local Bus Definitions | |
179 | */ | |
180 | ||
181 | /* Set the local bus clock 1/8 of platform clock */ | |
182 | #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 | |
183 | ||
184 | #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */ | |
185 | #ifdef CONFIG_PHYS_64BIT | |
186 | #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull | |
187 | #else | |
188 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE | |
189 | #endif | |
190 | ||
374a235d SX |
191 | #define CONFIG_SYS_FLASH_BR_PRELIM \ |
192 | (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \ | |
193 | | BR_PS_16 | BR_V) | |
194 | #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ | |
d1712369 KG |
195 | | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) |
196 | ||
197 | #define CONFIG_SYS_BR1_PRELIM \ | |
198 | (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) | |
199 | #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 | |
200 | ||
d1712369 KG |
201 | #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ |
202 | #ifdef CONFIG_PHYS_64BIT | |
203 | #define PIXIS_BASE_PHYS 0xfffdf0000ull | |
204 | #else | |
205 | #define PIXIS_BASE_PHYS PIXIS_BASE | |
206 | #endif | |
207 | ||
208 | #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) | |
209 | #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ | |
210 | ||
211 | #define PIXIS_LBMAP_SWITCH 7 | |
212 | #define PIXIS_LBMAP_MASK 0xf0 | |
213 | #define PIXIS_LBMAP_SHIFT 4 | |
214 | #define PIXIS_LBMAP_ALTBANK 0x40 | |
215 | ||
216 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
217 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
218 | ||
219 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ | |
220 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
221 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
222 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
223 | ||
14d0a02a | 224 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
d1712369 | 225 | |
2a9fab82 SX |
226 | #if defined(CONFIG_RAMBOOT_PBL) |
227 | #define CONFIG_SYS_RAMBOOT | |
228 | #endif | |
229 | ||
e02aea61 | 230 | /* Nand Flash */ |
e02aea61 KG |
231 | #ifdef CONFIG_NAND_FSL_ELBC |
232 | #define CONFIG_SYS_NAND_BASE 0xffa00000 | |
233 | #ifdef CONFIG_PHYS_64BIT | |
234 | #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull | |
235 | #else | |
236 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE | |
237 | #endif | |
238 | ||
239 | #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} | |
240 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
241 | #define CONFIG_MTD_NAND_VERIFY_WRITE | |
242 | #define CONFIG_CMD_NAND | |
243 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
244 | ||
245 | /* NAND flash config */ | |
246 | #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
247 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | |
248 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
249 | | BR_MS_FCM /* MSEL = FCM */ \ | |
250 | | BR_V) /* valid */ | |
251 | #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ | |
252 | | OR_FCM_PGS /* Large Page*/ \ | |
253 | | OR_FCM_CSCT \ | |
254 | | OR_FCM_CST \ | |
255 | | OR_FCM_CHT \ | |
256 | | OR_FCM_SCY_1 \ | |
257 | | OR_FCM_TRLX \ | |
258 | | OR_FCM_EHTR) | |
259 | ||
374a235d SX |
260 | #ifdef CONFIG_NAND |
261 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ | |
262 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ | |
263 | #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ | |
264 | #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ | |
265 | #else | |
266 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ | |
267 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ | |
268 | #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ | |
269 | #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ | |
270 | #endif | |
374a235d SX |
271 | #else |
272 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ | |
273 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ | |
c6d33901 | 274 | #endif /* CONFIG_NAND_FSL_ELBC */ |
e02aea61 | 275 | |
d1712369 KG |
276 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
277 | #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 | |
278 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} | |
279 | ||
280 | #define CONFIG_BOARD_EARLY_INIT_F | |
281 | #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ | |
282 | #define CONFIG_MISC_INIT_R | |
283 | ||
284 | #define CONFIG_HWCONFIG | |
285 | ||
286 | /* define to use L1 as initial stack */ | |
287 | #define CONFIG_L1_INIT_RAM | |
288 | #define CONFIG_SYS_INIT_RAM_LOCK | |
289 | #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ | |
290 | #ifdef CONFIG_PHYS_64BIT | |
291 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf | |
292 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR | |
293 | /* The assembler doesn't like typecast */ | |
294 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ | |
295 | ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ | |
296 | CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) | |
297 | #else | |
298 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ | |
299 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 | |
300 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS | |
301 | #endif | |
553f0982 | 302 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ |
d1712369 | 303 | |
25ddd1fb | 304 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
d1712369 KG |
305 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
306 | ||
307 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) | |
308 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ | |
309 | ||
310 | /* Serial Port - controlled on board with jumper J8 | |
311 | * open - index 2 | |
312 | * shorted - index 1 | |
313 | */ | |
314 | #define CONFIG_CONS_INDEX 1 | |
315 | #define CONFIG_SYS_NS16550 | |
316 | #define CONFIG_SYS_NS16550_SERIAL | |
317 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
318 | #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) | |
319 | ||
320 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
321 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
322 | ||
323 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) | |
324 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) | |
325 | #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) | |
326 | #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) | |
327 | ||
328 | /* Use the HUSH parser */ | |
329 | #define CONFIG_SYS_HUSH_PARSER | |
330 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
331 | ||
332 | /* pass open firmware flat tree */ | |
333 | #define CONFIG_OF_LIBFDT | |
334 | #define CONFIG_OF_BOARD_SETUP | |
335 | #define CONFIG_OF_STDOUT_VIA_ALIAS | |
336 | ||
337 | /* new uImage format support */ | |
338 | #define CONFIG_FIT | |
339 | #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ | |
340 | ||
341 | /* I2C */ | |
342 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
343 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
344 | #define CONFIG_I2C_MULTI_BUS | |
345 | #define CONFIG_I2C_CMD_TREE | |
346 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ | |
347 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
348 | #define CONFIG_SYS_I2C_OFFSET 0x118000 | |
349 | #define CONFIG_SYS_I2C2_OFFSET 0x118100 | |
350 | ||
351 | /* | |
352 | * RapidIO | |
353 | */ | |
a09b9b68 | 354 | #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 |
d1712369 | 355 | #ifdef CONFIG_PHYS_64BIT |
a09b9b68 | 356 | #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull |
d1712369 | 357 | #else |
a09b9b68 | 358 | #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 |
d1712369 | 359 | #endif |
a09b9b68 | 360 | #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ |
d1712369 | 361 | |
a09b9b68 | 362 | #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 |
d1712369 | 363 | #ifdef CONFIG_PHYS_64BIT |
a09b9b68 | 364 | #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull |
d1712369 | 365 | #else |
a09b9b68 | 366 | #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 |
d1712369 | 367 | #endif |
a09b9b68 | 368 | #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ |
d1712369 | 369 | |
2dd3095d SX |
370 | /* |
371 | * eSPI - Enhanced SPI | |
372 | */ | |
373 | #define CONFIG_FSL_ESPI | |
374 | #define CONFIG_SPI_FLASH | |
375 | #define CONFIG_SPI_FLASH_SPANSION | |
376 | #define CONFIG_CMD_SF | |
377 | #define CONFIG_SF_DEFAULT_SPEED 10000000 | |
378 | #define CONFIG_SF_DEFAULT_MODE 0 | |
379 | ||
d1712369 KG |
380 | /* |
381 | * General PCI | |
382 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
383 | */ | |
384 | ||
385 | /* controller 1, direct to uli, tgtid 3, Base address 20000 */ | |
386 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 | |
387 | #ifdef CONFIG_PHYS_64BIT | |
388 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 | |
389 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull | |
390 | #else | |
391 | #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 | |
392 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 | |
393 | #endif | |
394 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ | |
395 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 | |
396 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
397 | #ifdef CONFIG_PHYS_64BIT | |
398 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull | |
399 | #else | |
400 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 | |
401 | #endif | |
402 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ | |
403 | ||
404 | /* controller 2, Slot 2, tgtid 2, Base address 201000 */ | |
405 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 | |
406 | #ifdef CONFIG_PHYS_64BIT | |
407 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 | |
408 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull | |
409 | #else | |
410 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 | |
411 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 | |
412 | #endif | |
413 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ | |
414 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 | |
415 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
416 | #ifdef CONFIG_PHYS_64BIT | |
417 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull | |
418 | #else | |
419 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 | |
420 | #endif | |
421 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ | |
422 | ||
423 | /* controller 3, Slot 1, tgtid 1, Base address 202000 */ | |
02bb4989 | 424 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 |
d1712369 KG |
425 | #ifdef CONFIG_PHYS_64BIT |
426 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 | |
427 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull | |
428 | #else | |
429 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 | |
430 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 | |
431 | #endif | |
432 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ | |
433 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 | |
434 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 | |
435 | #ifdef CONFIG_PHYS_64BIT | |
436 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull | |
437 | #else | |
438 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 | |
439 | #endif | |
440 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ | |
441 | ||
1bf8e9fd KG |
442 | /* controller 4, Base address 203000 */ |
443 | #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 | |
444 | #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull | |
445 | #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ | |
446 | #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 | |
447 | #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull | |
448 | #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ | |
449 | ||
d1712369 | 450 | /* Qman/Bman */ |
24995d82 | 451 | #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ |
d1712369 KG |
452 | #define CONFIG_SYS_BMAN_NUM_PORTALS 10 |
453 | #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 | |
454 | #ifdef CONFIG_PHYS_64BIT | |
455 | #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull | |
456 | #else | |
457 | #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE | |
458 | #endif | |
459 | #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 | |
460 | #define CONFIG_SYS_QMAN_NUM_PORTALS 10 | |
461 | #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 | |
462 | #ifdef CONFIG_PHYS_64BIT | |
463 | #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull | |
464 | #else | |
465 | #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE | |
466 | #endif | |
467 | #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 | |
468 | ||
469 | #define CONFIG_SYS_DPAA_FMAN | |
470 | #define CONFIG_SYS_DPAA_PME | |
471 | /* Default address of microcode for the Linux Fman driver */ | |
ffadc441 TT |
472 | #if defined(CONFIG_SPIFLASH) |
473 | /* | |
474 | * env is stored at 0x100000, sector size is 0x10000, ucode is stored after | |
475 | * env, so we got 0x110000. | |
476 | */ | |
477 | #define CONFIG_SYS_QE_FW_IN_SPIFLASH 0x110000 | |
478 | #elif defined(CONFIG_SDCARD) | |
479 | /* | |
480 | * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is | |
481 | * about 545KB (1089 blocks), Env is stored after the image, and the env size is | |
482 | * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. | |
483 | */ | |
484 | #define CONFIG_SYS_QE_FW_IN_MMC (512 * 1130) | |
485 | #elif defined(CONFIG_NAND) | |
486 | #define CONFIG_SYS_QE_FW_IN_NAND (6 * CONFIG_SYS_NAND_BLOCK_SIZE) | |
d1712369 | 487 | #else |
ffadc441 | 488 | #define CONFIG_SYS_FMAN_FW_ADDR 0xEF000000 |
d1712369 | 489 | #endif |
ffadc441 TT |
490 | #define CONFIG_SYS_FMAN_FW_LENGTH 0x10000 |
491 | #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_FMAN_FW_LENGTH) | |
d1712369 KG |
492 | |
493 | #ifdef CONFIG_SYS_DPAA_FMAN | |
494 | #define CONFIG_FMAN_ENET | |
2915609a AF |
495 | #define CONFIG_PHYLIB_10G |
496 | #define CONFIG_PHY_VITESSE | |
497 | #define CONFIG_PHY_TERANETICS | |
d1712369 KG |
498 | #endif |
499 | ||
500 | #ifdef CONFIG_PCI | |
d1712369 KG |
501 | #define CONFIG_NET_MULTI |
502 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
503 | #define CONFIG_E1000 | |
504 | ||
d1712369 KG |
505 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
506 | #define CONFIG_DOS_PARTITION | |
507 | #endif /* CONFIG_PCI */ | |
508 | ||
509 | /* SATA */ | |
510 | #ifdef CONFIG_FSL_SATA_V2 | |
511 | #define CONFIG_LIBATA | |
512 | #define CONFIG_FSL_SATA | |
513 | ||
514 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 | |
515 | #define CONFIG_SATA1 | |
516 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR | |
517 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
518 | #define CONFIG_SATA2 | |
519 | #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR | |
520 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
521 | ||
522 | #define CONFIG_LBA48 | |
523 | #define CONFIG_CMD_SATA | |
524 | #define CONFIG_DOS_PARTITION | |
525 | #define CONFIG_CMD_EXT2 | |
526 | #endif | |
527 | ||
528 | #ifdef CONFIG_FMAN_ENET | |
529 | #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c | |
530 | #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d | |
531 | #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e | |
532 | #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f | |
533 | #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 | |
534 | ||
d1712369 KG |
535 | #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c |
536 | #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d | |
537 | #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e | |
538 | #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f | |
539 | #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0 | |
d1712369 KG |
540 | |
541 | #define CONFIG_SYS_TBIPA_VALUE 8 | |
542 | #define CONFIG_MII /* MII PHY management */ | |
543 | #define CONFIG_ETHPRIME "FM1@DTSEC1" | |
544 | #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ | |
545 | #endif | |
546 | ||
547 | /* | |
548 | * Environment | |
549 | */ | |
d1712369 KG |
550 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ |
551 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ | |
552 | ||
553 | /* | |
554 | * Command line configuration. | |
555 | */ | |
556 | #include <config_cmd_default.h> | |
557 | ||
a000b795 | 558 | #define CONFIG_CMD_DHCP |
d1712369 KG |
559 | #define CONFIG_CMD_ELF |
560 | #define CONFIG_CMD_ERRATA | |
a000b795 | 561 | #define CONFIG_CMD_GREPENV |
d1712369 KG |
562 | #define CONFIG_CMD_IRQ |
563 | #define CONFIG_CMD_I2C | |
564 | #define CONFIG_CMD_MII | |
565 | #define CONFIG_CMD_PING | |
566 | #define CONFIG_CMD_SETEXPR | |
9570cbda | 567 | #define CONFIG_CMD_REGINFO |
d1712369 KG |
568 | |
569 | #ifdef CONFIG_PCI | |
570 | #define CONFIG_CMD_PCI | |
571 | #define CONFIG_CMD_NET | |
572 | #endif | |
573 | ||
574 | /* | |
575 | * USB | |
576 | */ | |
577 | #define CONFIG_CMD_USB | |
578 | #define CONFIG_USB_STORAGE | |
579 | #define CONFIG_USB_EHCI | |
580 | #define CONFIG_USB_EHCI_FSL | |
581 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
582 | #define CONFIG_CMD_EXT2 | |
a3a3e7b2 | 583 | #define CONFIG_HAS_FSL_DR_USB |
d1712369 | 584 | |
d1712369 KG |
585 | #ifdef CONFIG_MMC |
586 | #define CONFIG_FSL_ESDHC | |
587 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR | |
588 | #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT | |
589 | #define CONFIG_CMD_MMC | |
590 | #define CONFIG_GENERIC_MMC | |
591 | #define CONFIG_CMD_EXT2 | |
592 | #define CONFIG_CMD_FAT | |
593 | #define CONFIG_DOS_PARTITION | |
594 | #endif | |
595 | ||
596 | /* | |
597 | * Miscellaneous configurable options | |
598 | */ | |
599 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
600 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ | |
601 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
602 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
603 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
604 | #ifdef CONFIG_CMD_KGDB | |
605 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
606 | #else | |
607 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
608 | #endif | |
609 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
610 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
611 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
612 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
613 | ||
614 | /* | |
615 | * For booting Linux, the board info and command line data | |
a832ac41 | 616 | * have to be in the first 64 MB of memory, since this is |
d1712369 KG |
617 | * the maximum mapped by the Linux kernel during initialization. |
618 | */ | |
a832ac41 KG |
619 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ |
620 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
d1712369 | 621 | |
d1712369 KG |
622 | #ifdef CONFIG_CMD_KGDB |
623 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
624 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
625 | #endif | |
626 | ||
627 | /* | |
628 | * Environment Configuration | |
629 | */ | |
630 | #define CONFIG_ROOTPATH /opt/nfsroot | |
631 | #define CONFIG_BOOTFILE uImage | |
632 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ | |
633 | ||
634 | /* default location for tftp and bootm */ | |
635 | #define CONFIG_LOADADDR 1000000 | |
636 | ||
637 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
638 | ||
639 | #define CONFIG_BAUDRATE 115200 | |
640 | ||
68d4230c RM |
641 | #if defined(CONFIG_P4080DS) |
642 | #define __USB_PHY_TYPE ulpi | |
643 | #else | |
644 | #define __USB_PHY_TYPE utmi | |
645 | #endif | |
646 | ||
d1712369 | 647 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
c2b3b640 | 648 | "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ |
68d4230c RM |
649 | "bank_intlv=cs0_cs1;" \ |
650 | "usb1:dr_mode=host,phy_type=" MK_STR(__USB_PHY_TYPE) "\0"\ | |
d1712369 KG |
651 | "netdev=eth0\0" \ |
652 | "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ | |
14d0a02a | 653 | "ubootaddr=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0" \ |
c2b3b640 EM |
654 | "tftpflash=tftpboot $loadaddr $uboot && " \ |
655 | "protect off $ubootaddr +$filesize && " \ | |
656 | "erase $ubootaddr +$filesize && " \ | |
657 | "cp.b $loadaddr $ubootaddr $filesize && " \ | |
658 | "protect on $ubootaddr +$filesize && " \ | |
659 | "cmp.b $loadaddr $ubootaddr $filesize\0" \ | |
d1712369 KG |
660 | "consoledev=ttyS0\0" \ |
661 | "ramdiskaddr=2000000\0" \ | |
662 | "ramdiskfile=p4080ds/ramdisk.uboot\0" \ | |
663 | "fdtaddr=c00000\0" \ | |
664 | "fdtfile=p4080ds/p4080ds.dtb\0" \ | |
665 | "bdev=sda3\0" \ | |
ffadc441 | 666 | "c=ffe\0" |
d1712369 KG |
667 | |
668 | #define CONFIG_HDBOOT \ | |
669 | "setenv bootargs root=/dev/$bdev rw " \ | |
670 | "console=$consoledev,$baudrate $othbootargs;" \ | |
671 | "tftp $loadaddr $bootfile;" \ | |
672 | "tftp $fdtaddr $fdtfile;" \ | |
673 | "bootm $loadaddr - $fdtaddr" | |
674 | ||
675 | #define CONFIG_NFSBOOTCOMMAND \ | |
676 | "setenv bootargs root=/dev/nfs rw " \ | |
677 | "nfsroot=$serverip:$rootpath " \ | |
678 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
679 | "console=$consoledev,$baudrate $othbootargs;" \ | |
680 | "tftp $loadaddr $bootfile;" \ | |
681 | "tftp $fdtaddr $fdtfile;" \ | |
682 | "bootm $loadaddr - $fdtaddr" | |
683 | ||
684 | #define CONFIG_RAMBOOTCOMMAND \ | |
685 | "setenv bootargs root=/dev/ram rw " \ | |
686 | "console=$consoledev,$baudrate $othbootargs;" \ | |
687 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
688 | "tftp $loadaddr $bootfile;" \ | |
689 | "tftp $fdtaddr $fdtfile;" \ | |
690 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
691 | ||
692 | #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT | |
693 | ||
7065b7d4 RG |
694 | #ifdef CONFIG_SECURE_BOOT |
695 | #include <asm/fsl_secure_boot.h> | |
696 | #endif | |
697 | ||
d1712369 | 698 | #endif /* __CONFIG_H */ |