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23b80982 TR |
1 | /* |
2 | * (C) Copyright 2007-2008 | |
c9e798d3 | 3 | * Stelian Pop <stelian@popies.net> |
23b80982 TR |
4 | * Lead Tech Design <www.leadtechdesign.com> |
5 | * Ilko Iliev <www.ronetix.at> | |
6 | * | |
7 | * (C) Copyright 2009 | |
8 | * Eric Benard <eric@eukrea.com> | |
9 | * | |
10 | * Configuration settings for the Eukrea CPU9260 board. | |
11 | * | |
1a459660 | 12 | * SPDX-License-Identifier: GPL-2.0+ |
23b80982 TR |
13 | */ |
14 | ||
15 | #ifndef __CONFIG_H | |
16 | #define __CONFIG_H | |
17 | ||
c2b2a07e EB |
18 | /* to be removed once maemory-map.h is fixed */ |
19 | #define AT91_BASE_SYS 0xffffe800 | |
20 | #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) | |
23b80982 | 21 | |
7c966a8b | 22 | #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 |
95d50e5c | 23 | #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 |
23b80982 TR |
24 | |
25 | #if defined(CONFIG_CPU9G20) | |
c2b2a07e | 26 | #define CONFIG_AT91SAM9G20 |
23b80982 | 27 | #elif defined(CONFIG_CPU9260) |
c2b2a07e | 28 | #define CONFIG_AT91SAM9260 |
23b80982 TR |
29 | #else |
30 | #error "Unknown board" | |
31 | #endif | |
32 | ||
95d50e5c EB |
33 | #include <asm/arch/hardware.h> |
34 | ||
23b80982 | 35 | #define CONFIG_ARCH_CPU_INIT |
c2b2a07e EB |
36 | #define CONFIG_DISPLAY_CPUINFO |
37 | #define CONFIG_BOARD_EARLY_INIT_F | |
23b80982 | 38 | |
c2b2a07e EB |
39 | #define CONFIG_CMDLINE_TAG |
40 | #define CONFIG_SETUP_MEMORY_TAGS | |
41 | #define CONFIG_INITRD_TAG | |
42 | ||
43 | #if defined(CONFIG_NANDBOOT) | |
44 | #define CONFIG_SKIP_LOWLEVEL_INIT | |
45 | #define CONFIG_SYS_TEXT_BASE 0x23f00000 | |
46 | #else | |
47 | #define CONFIG_SYS_TEXT_BASE 0x00000000 | |
48 | #endif | |
23b80982 TR |
49 | |
50 | /* clocks */ | |
51 | #if defined(CONFIG_CPU9G20) | |
52 | #define MASTER_PLL_DIV 0x01 | |
53 | #define MASTER_PLL_MUL 0x2B | |
54 | #elif defined(CONFIG_CPU9260) | |
55 | #define MASTER_PLL_DIV 0x09 | |
56 | #define MASTER_PLL_MUL 0x61 | |
57 | #endif | |
58 | ||
59 | /* CKGR_MOR - enable main osc. */ | |
60 | #define CONFIG_SYS_MOR_VAL \ | |
61 | (AT91_PMC_MOSCEN | \ | |
62 | (255 << 8)) /* Main Oscillator Start-up Time */ | |
63 | #if defined(CONFIG_CPU9G20) | |
64 | #define CONFIG_SYS_PLLAR_VAL \ | |
65 | (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \ | |
66 | ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) | |
67 | #elif defined(CONFIG_CPU9260) | |
68 | #define CONFIG_SYS_PLLAR_VAL \ | |
69 | (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \ | |
70 | AT91_PMC_OUT | \ | |
71 | ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) | |
72 | #endif | |
73 | ||
74 | #if defined(CONFIG_CPU9G20) | |
75 | #define CONFIG_SYS_MCKR1_VAL \ | |
76 | (AT91_PMC_CSS_PLLA | \ | |
77 | AT91_PMC_PRES_1 | \ | |
78 | AT91SAM9_PMC_MDIV_6 | \ | |
79 | AT91_PMC_PDIV_2) | |
80 | #define CONFIG_SYS_MCKR2_VAL \ | |
81 | CONFIG_SYS_MCKR1_VAL | |
82 | #elif defined(CONFIG_CPU9260) | |
83 | #define CONFIG_SYS_MCKR1_VAL \ | |
84 | (AT91_PMC_CSS_SLOW | \ | |
85 | AT91_PMC_PRES_1 | \ | |
86 | AT91SAM9_PMC_MDIV_2 | \ | |
87 | AT91_PMC_PDIV_1) | |
88 | #define CONFIG_SYS_MCKR2_VAL \ | |
89 | (AT91_PMC_CSS_PLLA | \ | |
90 | AT91_PMC_PRES_1 | \ | |
91 | AT91SAM9_PMC_MDIV_2 | \ | |
92 | AT91_PMC_PDIV_1) | |
93 | #endif | |
94 | ||
95 | /* define PDC[31:16] as DATA[31:16] */ | |
96 | #define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000 | |
97 | /* no pull-up for D[31:16] */ | |
98 | #define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000 | |
99 | ||
100 | /* EBI_CSA, 3.3V, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */ | |
101 | #define CONFIG_SYS_MATRIX_EBICSA_VAL \ | |
c2b2a07e EB |
102 | (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A | \ |
103 | AT91_MATRIX_CSA_EBI_CS3A | AT91_MATRIX_CSA_VDDIOMSEL_3_3V) | |
23b80982 TR |
104 | |
105 | /* SDRAM */ | |
106 | /* SDRAMC_MR Mode register */ | |
107 | #define CONFIG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL | |
108 | /* SDRAMC_TR - Refresh Timer register */ | |
109 | #define CONFIG_SYS_SDRC_TR_VAL1 0x287 | |
110 | /* SDRAMC_CR - Configuration register*/ | |
111 | #if defined(CONFIG_CPU9G20) | |
112 | #define CONFIG_SYS_SDRC_CR_VAL_64MB \ | |
113 | (AT91_SDRAMC_NC_9 | \ | |
114 | AT91_SDRAMC_NR_13 | \ | |
115 | AT91_SDRAMC_NB_4 | \ | |
116 | AT91_SDRAMC_CAS_2 | \ | |
117 | AT91_SDRAMC_DBW_32 | \ | |
118 | (2 << 8) | /* Write Recovery Delay */ \ | |
119 | (9 << 12) | /* Row Cycle Delay */ \ | |
120 | (3 << 16) | /* Row Precharge Delay */ \ | |
121 | (3 << 20) | /* Row to Column Delay */ \ | |
122 | (6 << 24) | /* Active to Precharge Delay */ \ | |
123 | (10 << 28)) /* Exit Self Refresh to Active Delay */ | |
124 | ||
125 | #define CONFIG_SYS_SDRC_CR_VAL_128MB \ | |
126 | (AT91_SDRAMC_NC_10 | \ | |
127 | AT91_SDRAMC_NR_13 | \ | |
128 | AT91_SDRAMC_NB_4 | \ | |
129 | AT91_SDRAMC_CAS_2 | \ | |
130 | AT91_SDRAMC_DBW_32 | \ | |
131 | (2 << 8) | /* Write Recovery Delay */ \ | |
132 | (9 << 12) | /* Row Cycle Delay */ \ | |
133 | (3 << 16) | /* Row Precharge Delay */ \ | |
134 | (3 << 20) | /* Row to Column Delay */ \ | |
135 | (6 << 24) | /* Active to Precharge Delay */ \ | |
136 | (10 << 28)) /* Exit Self Refresh to Active Delay */ | |
137 | #elif defined(CONFIG_CPU9260) | |
138 | #define CONFIG_SYS_SDRC_CR_VAL_64MB \ | |
139 | (AT91_SDRAMC_NC_9 | \ | |
140 | AT91_SDRAMC_NR_13 | \ | |
141 | AT91_SDRAMC_NB_4 | \ | |
142 | AT91_SDRAMC_CAS_2 | \ | |
143 | AT91_SDRAMC_DBW_32 | \ | |
144 | (2 << 8) | /* Write Recovery Delay */ \ | |
145 | (7 << 12) | /* Row Cycle Delay */ \ | |
146 | (2 << 16) | /* Row Precharge Delay */ \ | |
147 | (2 << 20) | /* Row to Column Delay */ \ | |
148 | (5 << 24) | /* Active to Precharge Delay */ \ | |
149 | (8 << 28)) /* Exit Self Refresh to Active Delay */ | |
150 | ||
151 | #define CONFIG_SYS_SDRC_CR_VAL_128MB \ | |
152 | (AT91_SDRAMC_NC_10 | \ | |
153 | AT91_SDRAMC_NR_13 | \ | |
154 | AT91_SDRAMC_NB_4 | \ | |
155 | AT91_SDRAMC_CAS_2 | \ | |
156 | AT91_SDRAMC_DBW_32 | \ | |
157 | (2 << 8) | /* Write Recovery Delay */ \ | |
158 | (7 << 12) | /* Row Cycle Delay */ \ | |
159 | (2 << 16) | /* Row Precharge Delay */ \ | |
160 | (2 << 20) | /* Row to Column Delay */ \ | |
161 | (5 << 24) | /* Active to Precharge Delay */ \ | |
162 | (8 << 28)) /* Exit Self Refresh to Active Delay */ | |
163 | #endif | |
164 | ||
165 | /* Memory Device Register -> SDRAM */ | |
166 | #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM | |
167 | #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE | |
168 | #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ | |
169 | #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH | |
170 | #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ | |
171 | #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ | |
172 | #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ | |
173 | #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ | |
174 | #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ | |
175 | #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ | |
176 | #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ | |
177 | #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ | |
178 | #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR | |
179 | #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ | |
180 | #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL | |
181 | #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ | |
182 | #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ | |
183 | #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ | |
184 | ||
185 | /* setup SMC0, CS0 (NOR Flash) - 16-bit */ | |
186 | #if defined(CONFIG_CPU9G20) | |
187 | #define CONFIG_SYS_SMC0_SETUP0_VAL \ | |
c2b2a07e EB |
188 | (AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) | \ |
189 | AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0)) | |
23b80982 | 190 | #define CONFIG_SYS_SMC0_PULSE0_VAL \ |
c2b2a07e EB |
191 | (AT91_SMC_PULSE_NWE(8) | AT91_SMC_PULSE_NCS_WR(8) | \ |
192 | AT91_SMC_PULSE_NRD(14) | AT91_SMC_PULSE_NCS_RD(14)) | |
23b80982 | 193 | #define CONFIG_SYS_SMC0_CYCLE0_VAL \ |
c2b2a07e | 194 | (AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(14)) |
23b80982 | 195 | #define CONFIG_SYS_SMC0_MODE0_VAL \ |
c2b2a07e EB |
196 | (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ |
197 | AT91_SMC_MODE_DBW_16 | \ | |
198 | AT91_SMC_MODE_TDF | \ | |
199 | AT91_SMC_MODE_TDF_CYCLE(3)) | |
23b80982 TR |
200 | #elif defined(CONFIG_CPU9260) |
201 | #define CONFIG_SYS_SMC0_SETUP0_VAL \ | |
c2b2a07e EB |
202 | (AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) | \ |
203 | AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0)) | |
23b80982 | 204 | #define CONFIG_SYS_SMC0_PULSE0_VAL \ |
c2b2a07e EB |
205 | (AT91_SMC_PULSE_NWE(6) | AT91_SMC_PULSE_NCS_WR(6) | \ |
206 | AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(10)) | |
23b80982 | 207 | #define CONFIG_SYS_SMC0_CYCLE0_VAL \ |
c2b2a07e | 208 | (AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(10)) |
23b80982 | 209 | #define CONFIG_SYS_SMC0_MODE0_VAL \ |
c2b2a07e EB |
210 | (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ |
211 | AT91_SMC_MODE_DBW_16 | \ | |
212 | AT91_SMC_MODE_TDF | \ | |
213 | AT91_SMC_MODE_TDF_CYCLE(2)) | |
23b80982 TR |
214 | #endif |
215 | ||
216 | /* user reset enable */ | |
217 | #define CONFIG_SYS_RSTC_RMR_VAL \ | |
218 | (AT91_RSTC_KEY | \ | |
c2b2a07e EB |
219 | AT91_RSTC_CR_PROCRST | \ |
220 | AT91_RSTC_MR_ERSTL(1) | \ | |
221 | AT91_RSTC_MR_ERSTL(2)) | |
23b80982 TR |
222 | |
223 | /* Disable Watchdog */ | |
224 | #define CONFIG_SYS_WDTC_WDMR_VAL \ | |
c2b2a07e EB |
225 | (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ |
226 | AT91_WDT_MR_WDV(0xfff) | \ | |
227 | AT91_WDT_MR_WDDIS | \ | |
228 | AT91_WDT_MR_WDD(0xfff)) | |
23b80982 TR |
229 | |
230 | /* | |
231 | * Hardware drivers | |
232 | */ | |
c2b2a07e EB |
233 | #define CONFIG_AT91SAM9_WATCHDOG |
234 | #define CONFIG_AT91_GPIO | |
235 | #define CONFIG_ATMEL_USART | |
95d50e5c EB |
236 | #define CONFIG_USART_BASE ATMEL_BASE_DBGU |
237 | #define CONFIG_USART_ID ATMEL_ID_SYS | |
23b80982 TR |
238 | |
239 | #define CONFIG_BOOTDELAY 3 | |
240 | ||
241 | /* | |
242 | * BOOTP options | |
243 | */ | |
c2b2a07e EB |
244 | #define CONFIG_BOOTP_BOOTFILESIZE |
245 | #define CONFIG_BOOTP_BOOTPATH | |
246 | #define CONFIG_BOOTP_GATEWAY | |
247 | #define CONFIG_BOOTP_HOSTNAME | |
23b80982 TR |
248 | |
249 | /* | |
250 | * Command line configuration. | |
251 | */ | |
252 | #include <config_cmd_default.h> | |
253 | #undef CONFIG_CMD_BDI | |
254 | #undef CONFIG_CMD_IMI | |
255 | #undef CONFIG_CMD_FPGA | |
256 | #undef CONFIG_CMD_LOADS | |
257 | #undef CONFIG_CMD_IMLS | |
258 | ||
c2b2a07e EB |
259 | #define CONFIG_CMD_PING |
260 | #define CONFIG_CMD_DHCP | |
261 | #define CONFIG_CMD_NAND | |
262 | #define CONFIG_CMD_USB | |
263 | #define CONFIG_CMD_FAT | |
264 | #define CONFIG_CMD_MII | |
23b80982 TR |
265 | |
266 | /* SDRAM */ | |
267 | #define CONFIG_NR_DRAM_BANKS 1 | |
c2b2a07e | 268 | #define CONFIG_SYS_SDRAM_BASE 0x20000000 |
23b80982 | 269 | #if defined(CONFIG_CPU9260_128M) || defined(CONFIG_CPU9G20_128M) |
c2b2a07e | 270 | #define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024) |
23b80982 TR |
271 | #define CONFIG_SYS_SDRC_CR_VAL CONFIG_SYS_SDRC_CR_VAL_128MB |
272 | #else | |
c2b2a07e | 273 | #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) |
23b80982 TR |
274 | #define CONFIG_SYS_SDRC_CR_VAL CONFIG_SYS_SDRC_CR_VAL_64MB |
275 | #endif | |
276 | ||
277 | /* NAND flash */ | |
c2b2a07e | 278 | #define CONFIG_NAND_ATMEL |
23b80982 TR |
279 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
280 | #define CONFIG_SYS_NAND_BASE 0x40000000 | |
281 | #define CONFIG_SYS_NAND_DBW_8 1 | |
ac45bb16 AB |
282 | #define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PC(13) |
283 | #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14) | |
23b80982 TR |
284 | #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) |
285 | #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) | |
286 | ||
287 | /* NOR flash */ | |
c2b2a07e EB |
288 | #if defined(CONFIG_NANDBOOT) |
289 | #define CONFIG_SYS_NO_FLASH | |
290 | #else | |
291 | #define CONFIG_SYS_FLASH_CFI | |
292 | #define CONFIG_FLASH_CFI_DRIVER | |
23b80982 TR |
293 | #define PHYS_FLASH_1 0x10000000 |
294 | #define PHYS_FLASH_2 0x12000000 | |
295 | #define CONFIG_SYS_FLASH_BANKS_LIST \ | |
296 | { PHYS_FLASH_1, PHYS_FLASH_2 } | |
297 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 | |
298 | #define CONFIG_SYS_MAX_FLASH_SECT (255+4) | |
299 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 | |
300 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT | |
c2b2a07e EB |
301 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
302 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
303 | #define CONFIG_SYS_FLASH_PROTECTION | |
23b80982 | 304 | #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 |
c2b2a07e | 305 | #endif |
23b80982 TR |
306 | |
307 | /* Ethernet */ | |
c2b2a07e EB |
308 | #define CONFIG_MACB |
309 | #define CONFIG_RMII | |
23b80982 | 310 | #define CONFIG_NET_RETRY_COUNT 20 |
c2b2a07e | 311 | #define CONFIG_MACB_SEARCH_PHY |
4535a24c | 312 | #define CONFIG_AT91_WANTS_COMMON_PHY |
23b80982 TR |
313 | |
314 | /* LEDS */ | |
315 | /* Status LED */ | |
c2b2a07e EB |
316 | #define CONFIG_STATUS_LED |
317 | #define CONFIG_BOARD_SPECIFIC_LED | |
23b80982 TR |
318 | #define STATUS_LED_RED 0 |
319 | #define STATUS_LED_GREEN 1 | |
320 | #define STATUS_LED_YELLOW 2 | |
321 | #define STATUS_LED_BLUE 3 | |
322 | /* Red */ | |
323 | #define STATUS_LED_BIT STATUS_LED_RED | |
324 | #define STATUS_LED_STATE STATUS_LED_OFF | |
325 | #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) | |
326 | /* Green */ | |
327 | #define STATUS_LED_BIT1 STATUS_LED_GREEN | |
328 | #define STATUS_LED_STATE1 STATUS_LED_OFF | |
329 | #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) | |
330 | /* Yellow */ | |
331 | #define STATUS_LED_BIT2 STATUS_LED_YELLOW | |
332 | #define STATUS_LED_STATE2 STATUS_LED_OFF | |
333 | #define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2) | |
334 | /* Blue */ | |
335 | #define STATUS_LED_BIT3 STATUS_LED_BLUE | |
336 | #define STATUS_LED_STATE3 STATUS_LED_ON | |
337 | #define STATUS_LED_PERIOD3 (CONFIG_SYS_HZ / 2) | |
338 | /* Optional value */ | |
339 | #define STATUS_LED_BOOT STATUS_LED_BIT | |
340 | ||
c2b2a07e EB |
341 | #define CONFIG_RED_LED AT91_PIO_PORTC, 11 |
342 | #define CONFIG_GREEN_LED AT91_PIO_PORTC, 12 | |
343 | #define CONFIG_YELLOW_LED AT91_PIO_PORTC, 7 | |
344 | #define CONFIG_BLUE_LED AT91_PIO_PORTC, 9 | |
23b80982 TR |
345 | |
346 | /* USB */ | |
c2b2a07e | 347 | #define CONFIG_USB_ATMEL |
dcd2f1a0 | 348 | #define CONFIG_USB_ATMEL_CLK_SEL_PLLB |
c2b2a07e EB |
349 | #define CONFIG_USB_OHCI_NEW |
350 | #define CONFIG_DOS_PARTITION | |
351 | #define CONFIG_SYS_USB_OHCI_CPU_INIT | |
23b80982 | 352 | #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 |
c2b2a07e EB |
353 | #if defined(CONFIG_CPU9G20) |
354 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g20" | |
355 | #elif defined(CONFIG_CPU9260) | |
23b80982 | 356 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260" |
c2b2a07e | 357 | #endif |
23b80982 | 358 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 |
c2b2a07e | 359 | #define CONFIG_USB_STORAGE |
23b80982 TR |
360 | |
361 | #define CONFIG_SYS_LOAD_ADDR 0x21000000 | |
c2b2a07e | 362 | #define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR |
23b80982 | 363 | |
c2b2a07e EB |
364 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE |
365 | #define CONFIG_SYS_MEMTEST_END \ | |
366 | (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - 512 * 1024) | |
23b80982 | 367 | |
c2b2a07e EB |
368 | #if defined(CONFIG_NANDBOOT) |
369 | #define CONFIG_SYS_USE_NANDFLASH | |
370 | #undef CONFIG_SYS_USE_FLASH | |
371 | #else | |
372 | #define CONFIG_SYS_USE_FLASH | |
23b80982 | 373 | #undef CONFIG_SYS_USE_NANDFLASH |
c2b2a07e EB |
374 | #endif |
375 | ||
376 | #if defined(CONFIG_CPU9G20) | |
377 | #define CONFIG_SYS_BASEDIR "cpu9G20" | |
378 | #elif defined(CONFIG_CPU9260) | |
379 | #define CONFIG_SYS_BASEDIR "cpu9260" | |
380 | #endif | |
23b80982 TR |
381 | |
382 | #if defined(CONFIG_SYS_USE_FLASH) | |
c2b2a07e | 383 | #define CONFIG_ENV_IS_IN_FLASH |
23b80982 TR |
384 | #define CONFIG_ENV_OFFSET 0x40000 |
385 | #define CONFIG_ENV_SECT_SIZE 0x20000 | |
386 | #define CONFIG_ENV_SIZE 0x20000 | |
c2b2a07e | 387 | #define CONFIG_ENV_OVERWRITE |
23b80982 TR |
388 | |
389 | #define CONFIG_BOOTCOMMAND "run flashboot" | |
390 | ||
c2b2a07e | 391 | #define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=atmel_nand" |
23b80982 TR |
392 | #define MTDPARTS_DEFAULT \ |
393 | "mtdparts=physmap-flash.0:" \ | |
394 | "256k(u-boot)ro," \ | |
395 | "128k(u-boot-env)ro," \ | |
396 | "1792k(kernel)," \ | |
397 | "-(rootfs);" \ | |
398 | "atmel_nand:-(nand)" | |
399 | ||
400 | #define CONFIG_BOOTARGS "root=/dev/mtdblock3 rootfstype=jffs2 " | |
401 | ||
23b80982 TR |
402 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
403 | "mtdids=" MTDIDS_DEFAULT "\0" \ | |
404 | "mtdparts=" MTDPARTS_DEFAULT "\0" \ | |
405 | "partition=nand0,0\0" \ | |
406 | "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ | |
c2b2a07e | 407 | "ramboot=tftpboot 0x22000000 $(basedir)/uImage;" \ |
23b80982 TR |
408 | "run ramargs;bootm 22000000\0" \ |
409 | "flashboot=run ramargs;bootm 0x10060000\0" \ | |
410 | "basedir=" CONFIG_SYS_BASEDIR "\0" \ | |
411 | "updtub=tftp 0x24000000 $(basedir)/u-boot.bin;protect " \ | |
412 | "off 0x10000000 0x1003ffff;erase 0x10000000 " \ | |
413 | "0x1003ffff;cp.b 0x24000000 0x10000000 " \ | |
414 | "$(filesize)\0" \ | |
415 | "updtui=tftp 0x24000000 $(basedir)/uImage;protect off" \ | |
416 | " 0x10060000 0x1021ffff;erase 0x10060000 " \ | |
417 | "0x1021ffff;cp.b 0x24000000 0x10060000 " \ | |
418 | "$(filesize)\0" \ | |
419 | "updtrfs=tftp 0x24000000 $(basedir)/rootfs.jffs2; " \ | |
420 | "protect off 0x10220000 0x13ffffff;erase " \ | |
421 | "0x10220000 0x13ffffff;cp.b 0x24000000 " \ | |
422 | "0x10220000 $(filesize)\0" \ | |
423 | "" | |
c2b2a07e EB |
424 | #elif defined(CONFIG_NANDBOOT) |
425 | #define CONFIG_ENV_IS_IN_NAND | |
426 | #define CONFIG_ENV_OFFSET 0x60000 | |
427 | #define CONFIG_ENV_OFFSET_REDUND 0x80000 | |
428 | #define CONFIG_ENV_SECT_SIZE 0x20000 | |
429 | #define CONFIG_ENV_SIZE 0x20000 | |
430 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
431 | #define CONFIG_ENV_OVERWRITE | |
432 | ||
433 | #define CONFIG_BOOTCOMMAND "run flashboot" | |
434 | ||
435 | #define MTDIDS_DEFAULT "nand0=atmel_nand" | |
436 | #define MTDPARTS_DEFAULT \ | |
437 | "mtdparts=atmel_nand:" \ | |
438 | "128k(bootstrap)ro," \ | |
439 | "256k(u-boot)ro," \ | |
440 | "128k(u-boot-env)ro," \ | |
441 | "128k(u-boot-env2)ro," \ | |
442 | "2M(kernel)," \ | |
443 | "-(rootfs)" | |
444 | ||
445 | #define CONFIG_BOOTARGS "root=ubi0:eukrea-cpu9260-rootfs " \ | |
446 | "ubi.mtd=5 rootfstype=ubifs at91sam9_wdt.heartbeat=60" | |
447 | ||
448 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
449 | "mtdids=" MTDIDS_DEFAULT "\0" \ | |
450 | "mtdparts=" MTDPARTS_DEFAULT "\0" \ | |
451 | "partition=nand0,5\0" \ | |
452 | "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ | |
453 | "ramboot=tftpboot 0x22000000 $(basedir)/uImage;" \ | |
454 | "run ramargs;bootm 22000000\0" \ | |
455 | "flashboot=run ramargs; nand read 0x22000000 0xA0000 " \ | |
456 | "0x200000; bootm 0x22000000\0" \ | |
457 | "basedir=" CONFIG_SYS_BASEDIR "\0" \ | |
458 | "u-boot=u-boot-eukrea-cpu9260.bin\0" \ | |
459 | "kernel=uImage-eukrea-cpu9260.bin\0" \ | |
460 | "rootfs=image-eukrea-cpu9260.ubi\0" \ | |
461 | "updtub=tftp ${loadaddr} $(basedir)/${u-boot}; " \ | |
462 | "nand erase 20000 40000; " \ | |
463 | "nand write ${loadaddr} 20000 40000\0" \ | |
464 | "updtui=tftp ${loadaddr} $(basedir)/${kernel}; " \ | |
465 | "nand erase a0000 200000; " \ | |
466 | "nand write ${loadaddr} a0000 200000\0" \ | |
467 | "updtrfs=tftp ${loadaddr} $(basedir)/${rootfs}; " \ | |
468 | "nand erase 2a0000 fd60000; " \ | |
469 | "nand write ${loadaddr} 2a0000 ${filesize}\0" | |
23b80982 TR |
470 | #endif |
471 | ||
472 | #define CONFIG_BAUDRATE 115200 | |
23b80982 TR |
473 | |
474 | #if defined(CONFIG_CPU9G20) | |
475 | #define CONFIG_SYS_PROMPT "CPU9G20=> " | |
476 | #elif defined(CONFIG_CPU9260) | |
477 | #define CONFIG_SYS_PROMPT "CPU9260=> " | |
478 | #endif | |
479 | #define CONFIG_SYS_CBSIZE 256 | |
480 | #define CONFIG_SYS_MAXARGS 16 | |
481 | #define CONFIG_SYS_PBSIZE \ | |
482 | (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
c2b2a07e EB |
483 | #define CONFIG_SYS_LONGHELP |
484 | #define CONFIG_CMDLINE_EDITING | |
485 | #define CONFIG_SILENT_CONSOLE | |
486 | #define CONFIG_NETCONSOLE | |
23b80982 TR |
487 | |
488 | /* | |
489 | * Size of malloc() pool | |
490 | */ | |
491 | #define CONFIG_SYS_MALLOC_LEN \ | |
492 | ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000) | |
23b80982 | 493 | |
c2b2a07e EB |
494 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - \ |
495 | GENERATED_GBL_DATA_SIZE) | |
496 | ||
23b80982 | 497 | #endif |