[people/ms/u-boot.git] / include / configs / davinci_sffsdr.h

/*
 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
 *
 * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
 * Copyright (C) 2008 Philip Balister, OpenSDR <philip@opensdr.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* Board */
#define SFFSDR
#define CONFIG_SYS_NAND_LARGEPAGE
#define CONFIG_SYS_USE_NAND
#define CONFIG_SYS_USE_DSPLINK		/* don't power up the DSP. */
/* SoC Configuration */
#define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK		27000000	/* Timer Input clock freq */
#define CONFIG_SOC_DM644X
/* EEPROM definitions for Atmel 24LC64 EEPROM chip */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	20
/* Memory Info */
#define CONFIG_SYS_MALLOC_LEN		(0x10000 + 256*1024)	/* malloc() len */
#define CONFIG_SYS_MEMTEST_START	0x80000000	/* memtest start address */
#define CONFIG_SYS_MEMTEST_END		0x81000000	/* 16MB RAM test */
#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
#define PHYS_SDRAM_1		0x80000000	/* DDR Start */
#define PHYS_SDRAM_1_SIZE	0x08000000	/* DDR size 128MB */
#define DDR_4BANKS				/* 4-bank DDR2 (128MB) */
/* Serial Driver info */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	-4	/* NS16550 register size, byteorder */
#define CONFIG_SYS_NS16550_COM1	0x01c20000	/* Base address of UART0 */
#define CONFIG_SYS_NS16550_CLK	CONFIG_SYS_HZ_CLOCK	/* Input clock to NS16550 */
#define CONFIG_CONS_INDEX	1		/* use UART0 for console */
#define CONFIG_BAUDRATE		115200		/* Default baud rate */
/* I2C Configuration */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_DAVINCI
#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10    /* Bogus, master-only in U-Boot */
/* Network & Ethernet Configuration */
#define CONFIG_DRIVER_TI_EMAC
#define CONFIG_MII
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT	10
#define CONFIG_OVERWRITE_ETHADDR_ONCE
/* Flash & Environment */
#undef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_SYS_NO_FLASH
#define CONFIG_NAND_DAVINCI
#define CONFIG_SYS_NAND_CS		2
#define CONFIG_ENV_IS_IN_NAND		/* U-Boot env in NAND Flash  */
#define CONFIG_ENV_SECT_SIZE	2048	/* Env sector Size */
#define CONFIG_ENV_SIZE		(128 << 10)	/* 128 KiB */
#define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is loaded by a bootloader */
#define CONFIG_SYS_NAND_BASE		0x02000000
#define CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND devices */
#define CONFIG_ENV_OFFSET		0x0	/* Block 0--not used by bootcode */
/* I2C switch definitions for PCA9543 chip */
#define CONFIG_SYS_I2C_PCA9543_ADDR		0x70
#define CONFIG_SYS_I2C_PCA9543_ADDR_LEN	0	/* Single register. */
#define CONFIG_SYS_I2C_PCA9543_ENABLE_CH0	0x01	/* Enable channel 0. */
/* U-Boot general configuration */
#define CONFIG_MISC_INIT_R
#define CONFIG_BOOTDELAY	5		/* Autoboot after 5 seconds. */
#define CONFIG_BOOTFILE		"uImage"	/* Boot file name */
#define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size  */
#define CONFIG_SYS_PBSIZE							\
		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)	/* Print buffer size */
#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
#define CONFIG_SYS_LOAD_ADDR		0x80700000	/* Default Linux kernel
						 * load address. */
#define CONFIG_VERSION_VARIABLE
#define CONFIG_AUTO_COMPLETE		/* Won't work with hush so far,
					 * may be later */
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_LONGHELP
#define CONFIG_CRC32_VERIFY
#define CONFIG_MX_CYCLIC
/* Linux Information */
#define LINUX_BOOT_PARAM_ADDR	0x80000100
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_BOOTARGS			\
	"mem=56M "			\
	"console=ttyS0,115200n8 "	\
	"root=/dev/nfs rw noinitrd ip=dhcp "	\
	"nfsroot=${serverip}:/nfsroot/sffsdr "	\
	"eth0=${ethaddr}"
#define CONFIG_BOOTCOMMAND	\
	"nand read 87A00000 100000 300000;"	\
	"bootelf 87A00000"
/* U-Boot commands */
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_NAND
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF	/* Needed to load Integrity kernel. */

#ifdef CONFIG_CMD_BDI
#define CONFIG_CLOCKS
#endif

#define CONFIG_MAX_RAM_BANK_SIZE	(256 << 20)	/* 256 MB */

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + \
					 CONFIG_SYS_INIT_RAM_SIZE - \
					 GENERATED_GBL_DATA_SIZE)

#endif /* __CONFIG_H */
Commit	Line	Data
c7f879ec HV	1	/*
	2	* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
	3	*
2b1fa9d3 HV	4	* Copyright (C) 2008 Lyrtech <www.lyrtech.com>
	5	* Copyright (C) 2008 Philip Balister, OpenSDR <philip@opensdr.com>
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
c7f879ec HV	8	*/
	9
	10	#ifndef __CONFIG_H
	11	#define __CONFIG_H
c7f879ec	12
c7f879ec	13	/* Board */
c7f879ec	14	#define SFFSDR
6d0f6bcf JCPV	15	#define CONFIG_SYS_NAND_LARGEPAGE
6d0f6bcf JCPV	16	#define CONFIG_SYS_USE_NAND
7a4f511b	17	#define CONFIG_SYS_USE_DSPLINK /* don't power up the DSP. */
c7f879ec	18	/* SoC Configuration */
6d0f6bcf JCPV	19	#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
6d0f6bcf JCPV	20	#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */
f7904368	21	#define CONFIG_SOC_DM644X
2b1fa9d3	22	/* EEPROM definitions for Atmel 24LC64 EEPROM chip */
6d0f6bcf JCPV	23	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
	24	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
	25	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
	26	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
c7f879ec	27	/* Memory Info */
6d0f6bcf	28	#define CONFIG_SYS_MALLOC_LEN (0x10000 + 2561024) / malloc() len */
6d0f6bcf JCPV	29	#define CONFIG_SYS_MEMTEST_START 0x80000000 /* memtest start address */
6d0f6bcf JCPV	30	#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */
c7f879ec	31	#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
c7f879ec HV	32	#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
	33	#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
	34	#define DDR_4BANKS /* 4-bank DDR2 (128MB) */
c7f879ec	35	/* Serial Driver info */
6d0f6bcf JCPV	36	#define CONFIG_SYS_NS16550
6d0f6bcf JCPV	37	#define CONFIG_SYS_NS16550_SERIAL
7ee38c04	38	#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size, byteorder */
6d0f6bcf	39	#define CONFIG_SYS_NS16550_COM1 0x01c20000 /* Base address of UART0 */
7239c5da	40	#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK /* Input clock to NS16550 */
c7f879ec HV	41	#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
c7f879ec HV	42	#define CONFIG_BAUDRATE 115200 /* Default baud rate */
c7f879ec	43	/* I2C Configuration */
e8459dcc VA	44	#define CONFIG_SYS_I2C
	45	#define CONFIG_SYS_I2C_DAVINCI
	46	#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
	47	#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
c7f879ec	48	/* Network & Ethernet Configuration */
c7f879ec HV	49	#define CONFIG_DRIVER_TI_EMAC
c7f879ec HV	50	#define CONFIG_MII
c7f879ec HV	51	#define CONFIG_BOOTP_DNS
	52	#define CONFIG_BOOTP_DNS2
	53	#define CONFIG_BOOTP_SEND_HOSTNAME
	54	#define CONFIG_NET_RETRY_COUNT 10
	55	#define CONFIG_OVERWRITE_ETHADDR_ONCE
c7f879ec	56	/* Flash & Environment */
5a1aceb0	57	#undef CONFIG_ENV_IS_IN_FLASH
6d0f6bcf	58	#define CONFIG_SYS_NO_FLASH
ee4f3e27	59	#define CONFIG_NAND_DAVINCI
97f4eb8c	60	#define CONFIG_SYS_NAND_CS 2
51bfee19	61	#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
0e8d1586	62	#define CONFIG_ENV_SECT_SIZE 2048 /* Env sector Size */
a16df2c1	63	#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
c7f879ec	64	#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
6d0f6bcf JCPV	65	#define CONFIG_SYS_NAND_BASE 0x02000000
	66	#define CONFIG_SYS_NAND_HW_ECC
	67	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
0e8d1586	68	#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
2b1fa9d3	69	/* I2C switch definitions for PCA9543 chip */
6d0f6bcf JCPV	70	#define CONFIG_SYS_I2C_PCA9543_ADDR 0x70
	71	#define CONFIG_SYS_I2C_PCA9543_ADDR_LEN 0 /* Single register. */
	72	#define CONFIG_SYS_I2C_PCA9543_ENABLE_CH0 0x01 /* Enable channel 0. */
c7f879ec	73	/* U-Boot general configuration */
c7f879ec	74	#define CONFIG_MISC_INIT_R
2b1fa9d3	75	#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds. */
c7f879ec	76	#define CONFIG_BOOTFILE "uImage" /* Boot file name */
6d0f6bcf JCPV	77	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
	78	#define CONFIG_SYS_PBSIZE \
	79	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print buffer size */
	80	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	81	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	82	#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* Default Linux kernel
c7f879ec HV	83	* load address. */
	84	#define CONFIG_VERSION_VARIABLE
	85	#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far,
	86	* may be later */
6d0f6bcf	87	#define CONFIG_SYS_HUSH_PARSER
c7f879ec	88	#define CONFIG_CMDLINE_EDITING
6d0f6bcf	89	#define CONFIG_SYS_LONGHELP
c7f879ec HV	90	#define CONFIG_CRC32_VERIFY
c7f879ec HV	91	#define CONFIG_MX_CYCLIC
c7f879ec	92	/* Linux Information */
c7f879ec HV	93	#define LINUX_BOOT_PARAM_ADDR 0x80000100
	94	#define CONFIG_CMDLINE_TAG
	95	#define CONFIG_SETUP_MEMORY_TAGS
2b1fa9d3 HV	96	#define CONFIG_BOOTARGS \
	97	"mem=56M " \
	98	"console=ttyS0,115200n8 " \
	99	"root=/dev/nfs rw noinitrd ip=dhcp " \
	100	"nfsroot=${serverip}:/nfsroot/sffsdr " \
	101	"eth0=${ethaddr}"
	102	#define CONFIG_BOOTCOMMAND \
	103	"nand read 87A00000 100000 300000;" \
	104	"bootelf 87A00000"
c7f879ec	105	/* U-Boot commands */
c7f879ec HV	106	#define CONFIG_CMD_ASKENV
	107	#define CONFIG_CMD_DHCP
	108	#define CONFIG_CMD_DIAG
	109	#define CONFIG_CMD_I2C
	110	#define CONFIG_CMD_MII
	111	#define CONFIG_CMD_PING
	112	#define CONFIG_CMD_SAVES
	113	#define CONFIG_CMD_NAND
	114	#define CONFIG_CMD_EEPROM
c15947d6	115	#define CONFIG_CMD_ELF /* Needed to load Integrity kernel. */
ebc3c6cf	116
8f5d4687 HM	117	#ifdef CONFIG_CMD_BDI
	118	#define CONFIG_CLOCKS
	119	#endif
	120
ebc3c6cf SP	121	#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
	122
	123	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	124	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
	125	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
	126	CONFIG_SYS_INIT_RAM_SIZE - \
	127	GENERATED_GBL_DATA_SIZE)
	128
c7f879ec	129	#endif /* __CONFIG_H */