[people/ms/u-boot.git] / include / configs / davinci_sffsdr.h

/*
 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
 *
 * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
 * Copyright (C) 2008 Philip Balister, OpenSDR <philip@opensdr.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* Board */
#define SFFSDR
#define CONFIG_SYS_NAND_LARGEPAGE
#define CONFIG_SYS_USE_NAND
#define CONFIG_SYS_USE_DSPLINK		/* don't power up the DSP. */
#define CONFIG_DISPLAY_CPUINFO
/* SoC Configuration */
#define CONFIG_ARM926EJS			/* arm926ejs CPU core */
#define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK		27000000	/* Timer Input clock freq */
#define CONFIG_SYS_HZ			1000
#define CONFIG_SOC_DM644X
/* EEPROM definitions for Atmel 24LC64 EEPROM chip */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	20
/* Memory Info */
#define CONFIG_SYS_MALLOC_LEN		(0x10000 + 256*1024)	/* malloc() len */
#define CONFIG_SYS_GBL_DATA_SIZE	128		/* reserved for initial data */
#define CONFIG_SYS_MEMTEST_START	0x80000000	/* memtest start address */
#define CONFIG_SYS_MEMTEST_END		0x81000000	/* 16MB RAM test */
#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
#define CONFIG_STACKSIZE	(256*1024)	/* regular stack */
#define PHYS_SDRAM_1		0x80000000	/* DDR Start */
#define PHYS_SDRAM_1_SIZE	0x08000000	/* DDR size 128MB */
#define DDR_4BANKS				/* 4-bank DDR2 (128MB) */
/* Serial Driver info */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	-4	/* NS16550 register size, byteorder */
#define CONFIG_SYS_NS16550_COM1	0x01c20000	/* Base address of UART0 */
#define CONFIG_SYS_NS16550_CLK	CONFIG_SYS_HZ_CLOCK	/* Input clock to NS16550 */
#define CONFIG_CONS_INDEX	1		/* use UART0 for console */
#define CONFIG_BAUDRATE		115200		/* Default baud rate */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
/* I2C Configuration */
#define CONFIG_HARD_I2C
#define CONFIG_DRIVER_DAVINCI_I2C
#define CONFIG_SYS_I2C_SPEED		80000	/* 100Kbps won't work, silicon bug */
#define CONFIG_SYS_I2C_SLAVE		10	/* Bogus, master-only in U-Boot */
/* Network & Ethernet Configuration */
#define CONFIG_DRIVER_TI_EMAC
#define CONFIG_EMAC_MDIO_PHY_NUM	1
#define CONFIG_MII
#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT	10
#define CONFIG_OVERWRITE_ETHADDR_ONCE
#define CONFIG_NET_MULTI
/* Flash & Environment */
#undef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_SYS_NO_FLASH
#define CONFIG_NAND_DAVINCI
#define CONFIG_SYS_NAND_CS		2
#define CONFIG_ENV_IS_IN_NAND		/* U-Boot env in NAND Flash  */
#define CONFIG_ENV_SECT_SIZE	2048	/* Env sector Size */
#define CONFIG_ENV_SIZE		(128 << 10)	/* 128 KiB */
#define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is loaded by a bootloader */
#define CONFIG_SKIP_RELOCATE_UBOOT	/* to a proper address, init done */
#define CONFIG_SYS_NAND_BASE		0x02000000
#define CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND devices */
#define CONFIG_ENV_OFFSET		0x0	/* Block 0--not used by bootcode */
/* I2C switch definitions for PCA9543 chip */
#define CONFIG_SYS_I2C_PCA9543_ADDR		0x70
#define CONFIG_SYS_I2C_PCA9543_ADDR_LEN	0	/* Single register. */
#define CONFIG_SYS_I2C_PCA9543_ENABLE_CH0	0x01	/* Enable channel 0. */
/* U-Boot general configuration */
#undef CONFIG_USE_IRQ				/* No IRQ/FIQ in U-Boot */
#define CONFIG_MISC_INIT_R
#define CONFIG_BOOTDELAY	5		/* Autoboot after 5 seconds. */
#define CONFIG_BOOTFILE		"uImage"	/* Boot file name */
#define CONFIG_SYS_PROMPT		"U-Boot > "	/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size  */
#define CONFIG_SYS_PBSIZE							\
		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)	/* Print buffer size */
#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
#define CONFIG_SYS_LOAD_ADDR		0x80700000	/* Default Linux kernel
						 * load address. */
#define CONFIG_VERSION_VARIABLE
#define CONFIG_AUTO_COMPLETE		/* Won't work with hush so far,
					 * may be later */
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_LONGHELP
#define CONFIG_CRC32_VERIFY
#define CONFIG_MX_CYCLIC
/* Linux Information */
#define LINUX_BOOT_PARAM_ADDR	0x80000100
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_BOOTARGS			\
	"mem=56M "			\
	"console=ttyS0,115200n8 "	\
	"root=/dev/nfs rw noinitrd ip=dhcp "	\
	"nfsroot=${serverip}:/nfsroot/sffsdr "	\
	"eth0=${ethaddr}"
#define CONFIG_BOOTCOMMAND	\
	"nand read 87A00000 100000 300000;"	\
	"bootelf 87A00000"
/* U-Boot commands */
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_NAND
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF	/* Needed to load Integrity kernel. */
#undef CONFIG_CMD_BDI
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_SETGETDCR
#undef CONFIG_CMD_FLASH
#undef CONFIG_CMD_IMLS
/* KGDB support (if any) */
#ifdef CONFIG_CMD_KGDB
#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	1	/* which serial port to use */
#endif
#endif /* __CONFIG_H */
Commit	Line	Data
c7f879ec HV	1	/*
	2	* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
	3	*
2b1fa9d3 HV	4	* Copyright (C) 2008 Lyrtech <www.lyrtech.com>
	5	* Copyright (C) 2008 Philip Balister, OpenSDR <philip@opensdr.com>
	6	*
c7f879ec HV	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*/
	22
	23	#ifndef __CONFIG_H
	24	#define __CONFIG_H
c7f879ec	25
c7f879ec	26	/* Board */
c7f879ec	27	#define SFFSDR
6d0f6bcf JCPV	28	#define CONFIG_SYS_NAND_LARGEPAGE
6d0f6bcf JCPV	29	#define CONFIG_SYS_USE_NAND
7a4f511b DB	30	#define CONFIG_SYS_USE_DSPLINK /* don't power up the DSP. */
7a4f511b DB	31	#define CONFIG_DISPLAY_CPUINFO
c7f879ec	32	/* SoC Configuration */
c7f879ec	33	#define CONFIG_ARM926EJS /* arm926ejs CPU core */
6d0f6bcf JCPV	34	#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
	35	#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */
	36	#define CONFIG_SYS_HZ 1000
f7904368	37	#define CONFIG_SOC_DM644X
2b1fa9d3	38	/* EEPROM definitions for Atmel 24LC64 EEPROM chip */
6d0f6bcf JCPV	39	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
	40	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
	41	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
	42	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
c7f879ec	43	/* Memory Info */
6d0f6bcf JCPV	44	#define CONFIG_SYS_MALLOC_LEN (0x10000 + 2561024) / malloc() len */
	45	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* reserved for initial data */
	46	#define CONFIG_SYS_MEMTEST_START 0x80000000 /* memtest start address */
	47	#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */
c7f879ec HV	48	#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
	49	#define CONFIG_STACKSIZE (2561024) / regular stack */
	50	#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
	51	#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
	52	#define DDR_4BANKS /* 4-bank DDR2 (128MB) */
c7f879ec	53	/* Serial Driver info */
6d0f6bcf JCPV	54	#define CONFIG_SYS_NS16550
6d0f6bcf JCPV	55	#define CONFIG_SYS_NS16550_SERIAL
7ee38c04	56	#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size, byteorder */
6d0f6bcf	57	#define CONFIG_SYS_NS16550_COM1 0x01c20000 /* Base address of UART0 */
7239c5da	58	#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK /* Input clock to NS16550 */
c7f879ec HV	59	#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
c7f879ec HV	60	#define CONFIG_BAUDRATE 115200 /* Default baud rate */
6d0f6bcf	61	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
c7f879ec	62	/* I2C Configuration */
c7f879ec HV	63	#define CONFIG_HARD_I2C
c7f879ec HV	64	#define CONFIG_DRIVER_DAVINCI_I2C
6d0f6bcf JCPV	65	#define CONFIG_SYS_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
6d0f6bcf JCPV	66	#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
c7f879ec	67	/* Network & Ethernet Configuration */
c7f879ec	68	#define CONFIG_DRIVER_TI_EMAC
e6441c4f	69	#define CONFIG_EMAC_MDIO_PHY_NUM 1
c7f879ec HV	70	#define CONFIG_MII
	71	#define CONFIG_BOOTP_DEFAULT
	72	#define CONFIG_BOOTP_DNS
	73	#define CONFIG_BOOTP_DNS2
	74	#define CONFIG_BOOTP_SEND_HOSTNAME
	75	#define CONFIG_NET_RETRY_COUNT 10
	76	#define CONFIG_OVERWRITE_ETHADDR_ONCE
8453587e	77	#define CONFIG_NET_MULTI
c7f879ec	78	/* Flash & Environment */
5a1aceb0	79	#undef CONFIG_ENV_IS_IN_FLASH
6d0f6bcf	80	#define CONFIG_SYS_NO_FLASH
ee4f3e27	81	#define CONFIG_NAND_DAVINCI
97f4eb8c	82	#define CONFIG_SYS_NAND_CS 2
51bfee19	83	#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
0e8d1586	84	#define CONFIG_ENV_SECT_SIZE 2048 /* Env sector Size */
a16df2c1	85	#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
c7f879ec HV	86	#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
c7f879ec HV	87	#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */
6d0f6bcf JCPV	88	#define CONFIG_SYS_NAND_BASE 0x02000000
	89	#define CONFIG_SYS_NAND_HW_ECC
	90	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
0e8d1586	91	#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
2b1fa9d3	92	/* I2C switch definitions for PCA9543 chip */
6d0f6bcf JCPV	93	#define CONFIG_SYS_I2C_PCA9543_ADDR 0x70
	94	#define CONFIG_SYS_I2C_PCA9543_ADDR_LEN 0 /* Single register. */
	95	#define CONFIG_SYS_I2C_PCA9543_ENABLE_CH0 0x01 /* Enable channel 0. */
c7f879ec	96	/* U-Boot general configuration */
2b1fa9d3	97	#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
c7f879ec	98	#define CONFIG_MISC_INIT_R
2b1fa9d3	99	#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds. */
c7f879ec	100	#define CONFIG_BOOTFILE "uImage" /* Boot file name */
6d0f6bcf JCPV	101	#define CONFIG_SYS_PROMPT "U-Boot > " /* Monitor Command Prompt */
	102	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
	103	#define CONFIG_SYS_PBSIZE \
	104	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print buffer size */
	105	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	106	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	107	#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* Default Linux kernel
c7f879ec HV	108	* load address. */
	109	#define CONFIG_VERSION_VARIABLE
	110	#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far,
	111	* may be later */
6d0f6bcf JCPV	112	#define CONFIG_SYS_HUSH_PARSER
6d0f6bcf JCPV	113	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
c7f879ec	114	#define CONFIG_CMDLINE_EDITING
6d0f6bcf	115	#define CONFIG_SYS_LONGHELP
c7f879ec HV	116	#define CONFIG_CRC32_VERIFY
c7f879ec HV	117	#define CONFIG_MX_CYCLIC
c7f879ec	118	/* Linux Information */
c7f879ec HV	119	#define LINUX_BOOT_PARAM_ADDR 0x80000100
	120	#define CONFIG_CMDLINE_TAG
	121	#define CONFIG_SETUP_MEMORY_TAGS
2b1fa9d3 HV	122	#define CONFIG_BOOTARGS \
	123	"mem=56M " \
	124	"console=ttyS0,115200n8 " \
	125	"root=/dev/nfs rw noinitrd ip=dhcp " \
	126	"nfsroot=${serverip}:/nfsroot/sffsdr " \
	127	"eth0=${ethaddr}"
	128	#define CONFIG_BOOTCOMMAND \
	129	"nand read 87A00000 100000 300000;" \
	130	"bootelf 87A00000"
c7f879ec	131	/* U-Boot commands */
c7f879ec HV	132	#include <config_cmd_default.h>
	133	#define CONFIG_CMD_ASKENV
	134	#define CONFIG_CMD_DHCP
	135	#define CONFIG_CMD_DIAG
	136	#define CONFIG_CMD_I2C
	137	#define CONFIG_CMD_MII
	138	#define CONFIG_CMD_PING
	139	#define CONFIG_CMD_SAVES
	140	#define CONFIG_CMD_NAND
	141	#define CONFIG_CMD_EEPROM
c15947d6	142	#define CONFIG_CMD_ELF /* Needed to load Integrity kernel. */
c7f879ec HV	143	#undef CONFIG_CMD_BDI
	144	#undef CONFIG_CMD_FPGA
	145	#undef CONFIG_CMD_SETGETDCR
	146	#undef CONFIG_CMD_FLASH
	147	#undef CONFIG_CMD_IMLS
c7f879ec	148	/* KGDB support (if any) */
c7f879ec HV	149	#ifdef CONFIG_CMD_KGDB
	150	#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
	151	#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
	152	#endif
	153	#endif /* __CONFIG_H */