[people/ms/u-boot.git] / include / configs / db-88f6820-gp.h

/*
 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _CONFIG_DB_88F6820_GP_H
#define _CONFIG_DB_88F6820_GP_H

/*
 * High Level Configuration Options (easy to change)
 */
#define CONFIG_ARMADA_XP		/* SOC Family Name */
#define CONFIG_ARMADA_38X
#define CONFIG_DB_88F6820_GP		/* Board target name for DDR training */

#define CONFIG_SYS_L2_PL310

#ifdef CONFIG_SPL_BUILD
#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
#endif
#define CONFIG_DISPLAY_BOARDINFO_LATE

/*
 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
 * for DDR ECC byte filling in the SPL before loading the main
 * U-Boot into it.
 */
#define	CONFIG_SYS_TEXT_BASE	0x00800000
#define CONFIG_SYS_TCLK		250000000	/* 250MHz */

/*
 * Commands configuration
 */
#define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ENV
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_EXT4
#define CONFIG_CMD_FAT
#define CONFIG_CMD_FS_GENERIC
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MMC
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_SCSI
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
#define CONFIG_CMD_TFTPPUT
#define CONFIG_CMD_TIME

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MVTWSI
#define CONFIG_I2C_MVTWSI_BASE0		MVEBU_TWSI_BASE
#define CONFIG_SYS_I2C_SLAVE		0x0
#define CONFIG_SYS_I2C_SPEED		100000

/* SPI NOR flash default params, used by sf commands */
#define CONFIG_SF_DEFAULT_SPEED		1000000
#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3
#define CONFIG_SPI_FLASH_STMICRO

/*
 * SDIO/MMC Card Configuration
 */
#define CONFIG_MMC
#define CONFIG_MMC_SDMA
#define CONFIG_GENERIC_MMC
#define CONFIG_SDHCI
#define CONFIG_MV_SDHCI
#define CONFIG_SYS_MMC_BASE		MVEBU_SDIO_BASE

/*
 * SATA/SCSI/AHCI configuration
 */
#define CONFIG_LIBATA
#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SCSI_MAX_SCSI_ID	2
#define CONFIG_SYS_SCSI_MAX_LUN		1
#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
					 CONFIG_SYS_SCSI_MAX_LUN)

/* Partition support */
#define CONFIG_DOS_PARTITION
#define CONFIG_EFI_PARTITION

/* Additional FS support/configuration */
#define CONFIG_SUPPORT_VFAT

/* USB/EHCI configuration */
#define CONFIG_EHCI_IS_TDI

/* Environment in SPI NOR flash */
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET		(1 << 20) /* 1MiB in */
#define CONFIG_ENV_SIZE			(64 << 10) /* 64KiB */
#define CONFIG_ENV_SECT_SIZE		(256 << 10) /* 256KiB sectors */

#define CONFIG_PHY_MARVELL		/* there is a marvell phy */
#define CONFIG_PHY_ADDR			{ 1, 0 }
#define CONFIG_SYS_NETA_INTERFACE_TYPE	PHY_INTERFACE_MODE_RGMII
#define PHY_ANEG_TIMEOUT	8000	/* PHY needs a longer aneg time */

/* PCIe support */
#define CONFIG_PCI
#define CONFIG_PCI_MVEBU
#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_E1000	/* enable Intel E1000 support for testing */

#define CONFIG_SYS_CONSOLE_INFO_QUIET	/* don't print console @ startup */
#define CONFIG_SYS_ALT_MEMTEST

/* Keep device tree and initrd in lower memory so the kernel can access them */
#define CONFIG_EXTRA_ENV_SETTINGS	\
	"fdt_high=0x10000000\0"		\
	"initrd_high=0x10000000\0"

/* SPL */
/*
 * Select the boot device here
 *
 * Currently supported are:
 * SPL_BOOT_SPI_NOR_FLASH	- Booting via SPI NOR flash
 * SPL_BOOT_SDIO_MMC_CARD	- Booting via SDIO/MMC card (partition 1)
 */
#define SPL_BOOT_SPI_NOR_FLASH		1
#define SPL_BOOT_SDIO_MMC_CARD		2
#define CONFIG_SPL_BOOT_DEVICE		SPL_BOOT_SPI_NOR_FLASH

/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_SIZE			(140 << 10)
#define CONFIG_SPL_TEXT_BASE		0x40000030
#define CONFIG_SPL_MAX_SIZE		(CONFIG_SPL_SIZE - 0x0030)

#define CONFIG_SPL_BSS_START_ADDR	(0x40000000 + CONFIG_SPL_SIZE)
#define CONFIG_SPL_BSS_MAX_SIZE		(16 << 10)

#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SPL_BSS_START_ADDR + \
					 CONFIG_SPL_BSS_MAX_SIZE)
#define CONFIG_SYS_SPL_MALLOC_SIZE	(16 << 10)

#define CONFIG_SPL_STACK		(0x40000000 + ((192 - 16) << 10))
#define CONFIG_SPL_BOOTROM_SAVE		(CONFIG_SPL_STACK + 4)

#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT

#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH
/* SPL related SPI defines */
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SPL_SPI_BUS		0
#define CONFIG_SPL_SPI_CS		0
#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x20000
#define CONFIG_SYS_U_BOOT_OFFS		CONFIG_SYS_SPI_U_BOOT_OFFS
#endif

#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD
/* SPL related MMC defines */
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_LIBDISK_SUPPORT
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1
#define CONFIG_SYS_MMC_U_BOOT_OFFS		(160 << 10)
#define CONFIG_SYS_U_BOOT_OFFS			CONFIG_SYS_MMC_U_BOOT_OFFS
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	(CONFIG_SYS_U_BOOT_OFFS / 512)
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	((512 << 10) / 512) /* 512KiB */
#ifdef CONFIG_SPL_BUILD
#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER	0x00180000	/* in SDRAM */
#endif
#endif

/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
#define CONFIG_SYS_MVEBU_DDR_A38X
#define CONFIG_DDR3

/*
 * mv-common.h should be defined after CMD configs since it used them
 * to enable certain macros
 */
#include "mv-common.h"

#endif /* _CONFIG_DB_88F6820_GP_H */
Commit	Line	Data
2bae75a4 SR	1	/*
	2	* Copyright (C) 2014 Stefan Roese <sr@denx.de>
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#ifndef _CONFIG_DB_88F6820_GP_H
	8	#define _CONFIG_DB_88F6820_GP_H
	9
	10	/*
	11	* High Level Configuration Options (easy to change)
	12	*/
	13	#define CONFIG_ARMADA_XP /* SOC Family Name */
9e30b31d	14	#define CONFIG_ARMADA_38X
2bae75a4 SR	15	#define CONFIG_DB_88F6820_GP /* Board target name for DDR training */
	16
	17	#define CONFIG_SYS_L2_PL310
	18
42cc034f	19	#ifdef CONFIG_SPL_BUILD
2bae75a4	20	#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
42cc034f	21	#endif
2bae75a4 SR	22	#define CONFIG_DISPLAY_BOARDINFO_LATE
2bae75a4 SR	23
2923c2d2 SR	24	/*
	25	* TEXT_BASE needs to be below 16MiB, since this area is scrubbed
	26	* for DDR ECC byte filling in the SPL before loading the main
	27	* U-Boot into it.
	28	*/
	29	#define CONFIG_SYS_TEXT_BASE 0x00800000
2bae75a4 SR	30	#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
	31
	32	/*
	33	* Commands configuration
	34	*/
	35	#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
2bae75a4 SR	36	#define CONFIG_CMD_CACHE
	37	#define CONFIG_CMD_DHCP
	38	#define CONFIG_CMD_ENV
e80f1e85 SR	39	#define CONFIG_CMD_EXT2
	40	#define CONFIG_CMD_EXT4
	41	#define CONFIG_CMD_FAT
	42	#define CONFIG_CMD_FS_GENERIC
2bae75a4	43	#define CONFIG_CMD_I2C
e80f1e85	44	#define CONFIG_CMD_MMC
ce2cb1d3	45	#define CONFIG_CMD_PCI
2bae75a4	46	#define CONFIG_CMD_PING
4d991cb3	47	#define CONFIG_CMD_SCSI
2bae75a4 SR	48	#define CONFIG_CMD_SF
	49	#define CONFIG_CMD_SPI
	50	#define CONFIG_CMD_TFTPPUT
	51	#define CONFIG_CMD_TIME
	52
	53	/* I2C */
	54	#define CONFIG_SYS_I2C
	55	#define CONFIG_SYS_I2C_MVTWSI
	56	#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
	57	#define CONFIG_SYS_I2C_SLAVE 0x0
	58	#define CONFIG_SYS_I2C_SPEED 100000
	59
	60	/* SPI NOR flash default params, used by sf commands */
	61	#define CONFIG_SF_DEFAULT_SPEED 1000000
	62	#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
	63	#define CONFIG_SPI_FLASH_STMICRO
	64
e80f1e85 SR	65	/*
	66	* SDIO/MMC Card Configuration
	67	*/
	68	#define CONFIG_MMC
	69	#define CONFIG_MMC_SDMA
	70	#define CONFIG_GENERIC_MMC
	71	#define CONFIG_SDHCI
	72	#define CONFIG_MV_SDHCI
	73	#define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE
	74
7cbaff95 SR	75	/*
	76	* SATA/SCSI/AHCI configuration
	77	*/
	78	#define CONFIG_LIBATA
	79	#define CONFIG_SCSI_AHCI
	80	#define CONFIG_SCSI_AHCI_PLAT
	81	#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
	82	#define CONFIG_SYS_SCSI_MAX_LUN 1
	83	#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
	84	CONFIG_SYS_SCSI_MAX_LUN)
	85
e80f1e85 SR	86	/* Partition support */
	87	#define CONFIG_DOS_PARTITION
	88	#define CONFIG_EFI_PARTITION
	89
	90	/* Additional FS support/configuration */
	91	#define CONFIG_SUPPORT_VFAT
	92
59565736	93	/* USB/EHCI configuration */
59565736 SR	94	#define CONFIG_EHCI_IS_TDI
59565736 SR	95
2bae75a4 SR	96	/* Environment in SPI NOR flash */
	97	#define CONFIG_ENV_IS_IN_SPI_FLASH
	98	#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
	99	#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
	100	#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */
	101
	102	#define CONFIG_PHY_MARVELL /* there is a marvell phy */
	103	#define CONFIG_PHY_ADDR { 1, 0 }
	104	#define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII
	105	#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
	106
ce2cb1d3 SR	107	/* PCIe support */
	108	#define CONFIG_PCI
	109	#define CONFIG_PCI_MVEBU
	110	#define CONFIG_PCI_PNP
	111	#define CONFIG_PCI_SCAN_SHOW
	112	#define CONFIG_E1000 /* enable Intel E1000 support for testing */
	113
2bae75a4 SR	114	#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
	115	#define CONFIG_SYS_ALT_MEMTEST
	116
3fd38af7 KS	117	/* Keep device tree and initrd in lower memory so the kernel can access them */
	118	#define CONFIG_EXTRA_ENV_SETTINGS \
	119	"fdt_high=0x10000000\0" \
	120	"initrd_high=0x10000000\0"
	121
9e30b31d	122	/* SPL */
7853c508 SR	123	/*
	124	* Select the boot device here
	125	*
	126	* Currently supported are:
	127	* SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash
	128	* SPL_BOOT_SDIO_MMC_CARD - Booting via SDIO/MMC card (partition 1)
	129	*/
	130	#define SPL_BOOT_SPI_NOR_FLASH 1
	131	#define SPL_BOOT_SDIO_MMC_CARD 2
	132	#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SPI_NOR_FLASH
	133
9e30b31d SR	134	/* Defines for SPL */
	135	#define CONFIG_SPL_FRAMEWORK
	136	#define CONFIG_SPL_SIZE (140 << 10)
	137	#define CONFIG_SPL_TEXT_BASE 0x40000030
	138	#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030)
	139
	140	#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE)
	141	#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
	142
	143	#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
	144	CONFIG_SPL_BSS_MAX_SIZE)
	145	#define CONFIG_SYS_SPL_MALLOC_SIZE (16 << 10)
	146
	147	#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
	148	#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
	149
	150	#define CONFIG_SPL_LIBCOMMON_SUPPORT
	151	#define CONFIG_SPL_LIBGENERIC_SUPPORT
	152	#define CONFIG_SPL_SERIAL_SUPPORT
	153	#define CONFIG_SPL_I2C_SUPPORT
	154
7853c508	155	#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH
9e30b31d SR	156	/* SPL related SPI defines */
	157	#define CONFIG_SPL_SPI_SUPPORT
	158	#define CONFIG_SPL_SPI_FLASH_SUPPORT
	159	#define CONFIG_SPL_SPI_LOAD
	160	#define CONFIG_SPL_SPI_BUS 0
	161	#define CONFIG_SPL_SPI_CS 0
	162	#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
7853c508 SR	163	#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
	164	#endif
	165
	166	#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD
	167	/* SPL related MMC defines */
	168	#define CONFIG_SPL_MMC_SUPPORT
	169	#define CONFIG_SPL_LIBDISK_SUPPORT
	170	#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1
	171	#define CONFIG_SYS_MMC_U_BOOT_OFFS (160 << 10)
	172	#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS
	173	#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR (CONFIG_SYS_U_BOOT_OFFS / 512)
	174	#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS ((512 << 10) / 512) /* 512KiB */
	175	#ifdef CONFIG_SPL_BUILD
	176	#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */
	177	#endif
	178	#endif
9e30b31d SR	179
	180	/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
	181	#define CONFIG_SYS_MVEBU_DDR_A38X
	182	#define CONFIG_DDR3
	183
2bae75a4 SR	184	/*
	185	* mv-common.h should be defined after CMD configs since it used them
	186	* to enable certain macros
	187	*/
	188	#include "mv-common.h"
	189
	190	#endif /* _CONFIG_DB_88F6820_GP_H */