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2bae75a4 SR |
1 | /* |
2 | * Copyright (C) 2014 Stefan Roese <sr@denx.de> | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | #ifndef _CONFIG_DB_88F6820_GP_H | |
8 | #define _CONFIG_DB_88F6820_GP_H | |
9 | ||
10 | /* | |
11 | * High Level Configuration Options (easy to change) | |
12 | */ | |
13 | #define CONFIG_ARMADA_XP /* SOC Family Name */ | |
9e30b31d | 14 | #define CONFIG_ARMADA_38X |
2bae75a4 SR |
15 | #define CONFIG_DB_88F6820_GP /* Board target name for DDR training */ |
16 | ||
17 | #define CONFIG_SYS_L2_PL310 | |
18 | ||
42cc034f | 19 | #ifdef CONFIG_SPL_BUILD |
2bae75a4 | 20 | #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ |
42cc034f | 21 | #endif |
2bae75a4 SR |
22 | #define CONFIG_DISPLAY_BOARDINFO_LATE |
23 | ||
2923c2d2 SR |
24 | /* |
25 | * TEXT_BASE needs to be below 16MiB, since this area is scrubbed | |
26 | * for DDR ECC byte filling in the SPL before loading the main | |
27 | * U-Boot into it. | |
28 | */ | |
29 | #define CONFIG_SYS_TEXT_BASE 0x00800000 | |
2bae75a4 SR |
30 | #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ |
31 | ||
32 | /* | |
33 | * Commands configuration | |
34 | */ | |
35 | #define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ | |
2bae75a4 SR |
36 | #define CONFIG_CMD_CACHE |
37 | #define CONFIG_CMD_DHCP | |
38 | #define CONFIG_CMD_ENV | |
e80f1e85 SR |
39 | #define CONFIG_CMD_EXT2 |
40 | #define CONFIG_CMD_EXT4 | |
41 | #define CONFIG_CMD_FAT | |
42 | #define CONFIG_CMD_FS_GENERIC | |
2bae75a4 | 43 | #define CONFIG_CMD_I2C |
e80f1e85 | 44 | #define CONFIG_CMD_MMC |
ce2cb1d3 | 45 | #define CONFIG_CMD_PCI |
2bae75a4 | 46 | #define CONFIG_CMD_PING |
4d991cb3 | 47 | #define CONFIG_CMD_SCSI |
2bae75a4 SR |
48 | #define CONFIG_CMD_SF |
49 | #define CONFIG_CMD_SPI | |
50 | #define CONFIG_CMD_TFTPPUT | |
51 | #define CONFIG_CMD_TIME | |
52 | ||
53 | /* I2C */ | |
54 | #define CONFIG_SYS_I2C | |
55 | #define CONFIG_SYS_I2C_MVTWSI | |
56 | #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE | |
57 | #define CONFIG_SYS_I2C_SLAVE 0x0 | |
58 | #define CONFIG_SYS_I2C_SPEED 100000 | |
59 | ||
60 | /* SPI NOR flash default params, used by sf commands */ | |
61 | #define CONFIG_SF_DEFAULT_SPEED 1000000 | |
62 | #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 | |
2bae75a4 | 63 | |
e80f1e85 SR |
64 | /* |
65 | * SDIO/MMC Card Configuration | |
66 | */ | |
67 | #define CONFIG_MMC | |
68 | #define CONFIG_MMC_SDMA | |
69 | #define CONFIG_GENERIC_MMC | |
70 | #define CONFIG_SDHCI | |
71 | #define CONFIG_MV_SDHCI | |
72 | #define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE | |
73 | ||
7cbaff95 SR |
74 | /* |
75 | * SATA/SCSI/AHCI configuration | |
76 | */ | |
77 | #define CONFIG_LIBATA | |
78 | #define CONFIG_SCSI_AHCI | |
79 | #define CONFIG_SCSI_AHCI_PLAT | |
80 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 | |
81 | #define CONFIG_SYS_SCSI_MAX_LUN 1 | |
82 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ | |
83 | CONFIG_SYS_SCSI_MAX_LUN) | |
84 | ||
e80f1e85 SR |
85 | /* Partition support */ |
86 | #define CONFIG_DOS_PARTITION | |
87 | #define CONFIG_EFI_PARTITION | |
88 | ||
89 | /* Additional FS support/configuration */ | |
90 | #define CONFIG_SUPPORT_VFAT | |
91 | ||
59565736 | 92 | /* USB/EHCI configuration */ |
59565736 SR |
93 | #define CONFIG_EHCI_IS_TDI |
94 | ||
2bae75a4 SR |
95 | /* Environment in SPI NOR flash */ |
96 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
97 | #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ | |
98 | #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ | |
99 | #define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */ | |
100 | ||
101 | #define CONFIG_PHY_MARVELL /* there is a marvell phy */ | |
102 | #define CONFIG_PHY_ADDR { 1, 0 } | |
103 | #define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII | |
104 | #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ | |
105 | ||
ce2cb1d3 | 106 | /* PCIe support */ |
6451223a | 107 | #ifndef CONFIG_SPL_BUILD |
ce2cb1d3 SR |
108 | #define CONFIG_PCI |
109 | #define CONFIG_PCI_MVEBU | |
110 | #define CONFIG_PCI_PNP | |
111 | #define CONFIG_PCI_SCAN_SHOW | |
112 | #define CONFIG_E1000 /* enable Intel E1000 support for testing */ | |
6451223a | 113 | #endif |
ce2cb1d3 | 114 | |
2bae75a4 SR |
115 | #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */ |
116 | #define CONFIG_SYS_ALT_MEMTEST | |
117 | ||
3fd38af7 KS |
118 | /* Keep device tree and initrd in lower memory so the kernel can access them */ |
119 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
120 | "fdt_high=0x10000000\0" \ | |
121 | "initrd_high=0x10000000\0" | |
122 | ||
9e30b31d | 123 | /* SPL */ |
7853c508 SR |
124 | /* |
125 | * Select the boot device here | |
126 | * | |
127 | * Currently supported are: | |
128 | * SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash | |
129 | * SPL_BOOT_SDIO_MMC_CARD - Booting via SDIO/MMC card (partition 1) | |
130 | */ | |
131 | #define SPL_BOOT_SPI_NOR_FLASH 1 | |
132 | #define SPL_BOOT_SDIO_MMC_CARD 2 | |
133 | #define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SPI_NOR_FLASH | |
134 | ||
9e30b31d SR |
135 | /* Defines for SPL */ |
136 | #define CONFIG_SPL_FRAMEWORK | |
137 | #define CONFIG_SPL_SIZE (140 << 10) | |
138 | #define CONFIG_SPL_TEXT_BASE 0x40000030 | |
139 | #define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030) | |
140 | ||
141 | #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) | |
142 | #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) | |
143 | ||
6451223a SR |
144 | #ifdef CONFIG_SPL_BUILD |
145 | #define CONFIG_SYS_MALLOC_SIMPLE | |
146 | #endif | |
9e30b31d SR |
147 | |
148 | #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) | |
149 | #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) | |
150 | ||
151 | #define CONFIG_SPL_LIBCOMMON_SUPPORT | |
152 | #define CONFIG_SPL_LIBGENERIC_SUPPORT | |
153 | #define CONFIG_SPL_SERIAL_SUPPORT | |
154 | #define CONFIG_SPL_I2C_SUPPORT | |
155 | ||
7853c508 | 156 | #if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH |
9e30b31d SR |
157 | /* SPL related SPI defines */ |
158 | #define CONFIG_SPL_SPI_SUPPORT | |
159 | #define CONFIG_SPL_SPI_FLASH_SUPPORT | |
160 | #define CONFIG_SPL_SPI_LOAD | |
161 | #define CONFIG_SPL_SPI_BUS 0 | |
162 | #define CONFIG_SPL_SPI_CS 0 | |
163 | #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 | |
7853c508 SR |
164 | #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS |
165 | #endif | |
166 | ||
167 | #if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD | |
168 | /* SPL related MMC defines */ | |
169 | #define CONFIG_SPL_MMC_SUPPORT | |
170 | #define CONFIG_SPL_LIBDISK_SUPPORT | |
171 | #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1 | |
172 | #define CONFIG_SYS_MMC_U_BOOT_OFFS (160 << 10) | |
173 | #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS | |
174 | #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR (CONFIG_SYS_U_BOOT_OFFS / 512) | |
175 | #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS ((512 << 10) / 512) /* 512KiB */ | |
176 | #ifdef CONFIG_SPL_BUILD | |
177 | #define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ | |
178 | #endif | |
179 | #endif | |
9e30b31d SR |
180 | |
181 | /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ | |
182 | #define CONFIG_SYS_MVEBU_DDR_A38X | |
183 | #define CONFIG_DDR3 | |
184 | ||
2bae75a4 SR |
185 | /* |
186 | * mv-common.h should be defined after CMD configs since it used them | |
187 | * to enable certain macros | |
188 | */ | |
189 | #include "mv-common.h" | |
190 | ||
191 | #endif /* _CONFIG_DB_88F6820_GP_H */ |