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5da627a4
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1/*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
1a459660 5 * SPDX-License-Identifier: GPL-2.0+
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6 */
7
8/*
9 * This file contains the configuration parameters for the dbau1x00 board.
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
5da627a4 15#define CONFIG_DBAU1X00 1
8bde63eb 16#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
5da627a4 17
74368693
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18#define CONFIG_SYS_GENERIC_BOARD
19#define CONFIG_DISPLAY_BOARDINFO
20
a2663ea4 21#ifdef CONFIG_DBAU1000
5da627a4 22/* Also known as Merlot */
8bde63eb 23#define CONFIG_SOC_AU1000 1
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24#else
25#ifdef CONFIG_DBAU1100
8bde63eb 26#define CONFIG_SOC_AU1100 1
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27#else
28#ifdef CONFIG_DBAU1500
8bde63eb 29#define CONFIG_SOC_AU1500 1
d4ca31c4 30#else
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31#ifdef CONFIG_DBAU1550
32/* Cabernet */
8bde63eb 33#define CONFIG_SOC_AU1550 1
ff36fd85 34#else
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35#error "No valid board set"
36#endif
37#endif
38#endif
ff36fd85 39#endif
5da627a4 40
d4ca31c4 41#define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */
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42
43#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
44
45#define CONFIG_BAUDRATE 115200
46
47/* valid baudrates */
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48
49#define CONFIG_TIMESTAMP /* Print image info with timestamp */
50#undef CONFIG_BOOTARGS
51
52#define CONFIG_EXTRA_ENV_SETTINGS \
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53 "addmisc=setenv bootargs ${bootargs} " \
54 "console=ttyS0,${baudrate} " \
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55 "panic=1\0" \
56 "bootfile=/tftpboot/vmlinux.srec\0" \
fe126d8b 57 "load=tftp 80500000 ${u-boot}\0" \
5da627a4 58 ""
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59
60#ifdef CONFIG_DBAU1550
61/* Boot from flash by default, revert to bootp */
62#define CONFIG_BOOTCOMMAND "bootm 0xbfc20000; bootp; bootm"
ff36fd85 63#else /* CONFIG_DBAU1550 */
ad88297e 64#define CONFIG_BOOTCOMMAND "bootp;bootm"
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65#endif /* CONFIG_DBAU1550 */
66
ab999ba1 67
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68/*
69 * BOOTP options
70 */
71#define CONFIG_BOOTP_BOOTFILESIZE
72#define CONFIG_BOOTP_BOOTPATH
73#define CONFIG_BOOTP_GATEWAY
74#define CONFIG_BOOTP_HOSTNAME
75
76
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77/*
78 * Command line configuration.
79 */
80#include <config_cmd_default.h>
81
82#undef CONFIG_CMD_BDI
83#undef CONFIG_CMD_BEDBUG
84#undef CONFIG_CMD_ELF
bdab39d3 85#undef CONFIG_CMD_SAVEENV
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86#undef CONFIG_CMD_FAT
87#undef CONFIG_CMD_FPGA
88#undef CONFIG_CMD_MII
89#undef CONFIG_CMD_RUN
90
91
92#ifdef CONFIG_DBAU1550
93
94#define CONFIG_CMD_FLASH
95#define CONFIG_CMD_LOADB
96#define CONFIG_CMD_NET
97
98#undef CONFIG_CMD_I2C
99#undef CONFIG_CMD_IDE
100#undef CONFIG_CMD_NFS
101#undef CONFIG_CMD_PCMCIA
102
103#else
104
105#define CONFIG_CMD_IDE
106#define CONFIG_CMD_DHCP
107
108#undef CONFIG_CMD_FLASH
109#undef CONFIG_CMD_LOADB
110#undef CONFIG_CMD_LOADS
111
112#endif
113
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114
115/*
116 * Miscellaneous configurable options
117 */
6d0f6bcf 118#define CONFIG_SYS_LONGHELP /* undef to save memory */
ff36fd85 119
6d0f6bcf 120#define CONFIG_SYS_PROMPT "DbAu1xx0 # " /* Monitor Command Prompt */
ff36fd85 121
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122#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
123#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
124#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
5da627a4 125
6d0f6bcf 126#define CONFIG_SYS_MALLOC_LEN 128*1024
5da627a4 127
6d0f6bcf 128#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
5da627a4 129
6d0f6bcf 130#define CONFIG_SYS_MHZ 396
ff36fd85 131
6d0f6bcf 132#if (CONFIG_SYS_MHZ % 12) != 0
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133#error "Invalid CPU frequency - must be multiple of 12!"
134#endif
135
6d0f6bcf 136#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
a55d4817 137
6d0f6bcf 138#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
5da627a4 139
6d0f6bcf 140#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */
5da627a4 141
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142#define CONFIG_SYS_MEMTEST_START 0x80100000
143#define CONFIG_SYS_MEMTEST_END 0x80800000
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144
145/*-----------------------------------------------------------------------
146 * FLASH and environment organization
147 */
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148#ifdef CONFIG_DBAU1550
149
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150#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
151#define CONFIG_SYS_MAX_FLASH_SECT (512) /* max number of sectors on one chip */
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152
153#define PHYS_FLASH_1 0xb8000000 /* Flash Bank #1 */
154#define PHYS_FLASH_2 0xbc000000 /* Flash Bank #2 */
155
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156#else /* CONFIG_DBAU1550 */
157
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158#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
159#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
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160
161#define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */
162#define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */
163
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164#endif /* CONFIG_DBAU1550 */
165
6d0f6bcf 166#define CONFIG_SYS_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2}
ad88297e 167
6d0f6bcf 168#define CONFIG_SYS_FLASH_CFI 1
00b1883a 169#define CONFIG_FLASH_CFI_DRIVER 1
ff36fd85 170
5da627a4 171/* The following #defines are needed to get flash environment right */
14d0a02a 172#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf 173#define CONFIG_SYS_MONITOR_LEN (192 << 10)
5da627a4 174
6d0f6bcf 175#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
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176
177/* We boot from this flash, selected with dip switch */
6d0f6bcf 178#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2
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179
180/* timeout values are in ticks */
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181#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
182#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
5da627a4 183
93f6d725 184#define CONFIG_ENV_IS_NOWHERE 1
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185
186/* Address and size of Primary Environment Sector */
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187#define CONFIG_ENV_ADDR 0xB0030000
188#define CONFIG_ENV_SIZE 0x10000
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189
190#define CONFIG_FLASH_16BIT
191
192#define CONFIG_NR_DRAM_BANKS 2
193
5da627a4 194
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195#ifdef CONFIG_DBAU1550
196#define MEM_SIZE 192
197#else
198#define MEM_SIZE 64
199#endif
200
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201#define CONFIG_MEMSIZE_IN_BYTES
202
ff36fd85 203#ifndef CONFIG_DBAU1550
5da627a4 204/*---ATA PCMCIA ------------------------------------*/
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205#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
206#define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000
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207#define CONFIG_PCMCIA_SLOT_A
208
209#define CONFIG_ATAPI 1
210#define CONFIG_MAC_PARTITION 1
211
212/* We run CF in "true ide" mode or a harddrive via pcmcia */
213#define CONFIG_IDE_PCMCIA 1
214
215/* We only support one slot for now */
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216#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
217#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
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218
219#undef CONFIG_IDE_LED /* LED for ide not supported */
220#undef CONFIG_IDE_RESET /* reset for ide not supported */
221
6d0f6bcf 222#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
5da627a4 223
6d0f6bcf 224#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
5da627a4 225
d4ca31c4 226/* Offset for data I/O */
6d0f6bcf 227#define CONFIG_SYS_ATA_DATA_OFFSET 8
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228
229/* Offset for normal register accesses */
6d0f6bcf 230#define CONFIG_SYS_ATA_REG_OFFSET 0
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231
232/* Offset for alternate registers */
6d0f6bcf 233#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
ff36fd85 234#endif /* CONFIG_DBAU1550 */
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235
236/*-----------------------------------------------------------------------
237 * Cache Configuration
238 */
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239#define CONFIG_SYS_DCACHE_SIZE 16384
240#define CONFIG_SYS_ICACHE_SIZE 16384
241#define CONFIG_SYS_CACHELINE_SIZE 32
5da627a4 242
5da627a4 243#endif /* __CONFIG_H */