]> git.ipfire.org Git - people/ms/u-boot.git/blame - include/configs/dbau1x00.h
Merge branch 'u-boot-socfpga/topic/arm/socfpga-20141010' into 'u-boot-arm/master'
[people/ms/u-boot.git] / include / configs / dbau1x00.h
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5da627a4
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1/*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
1a459660 5 * SPDX-License-Identifier: GPL-2.0+
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6 */
7
8/*
9 * This file contains the configuration parameters for the dbau1x00 board.
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
5da627a4 15#define CONFIG_DBAU1X00 1
8bde63eb 16#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
5da627a4 17
a2663ea4 18#ifdef CONFIG_DBAU1000
5da627a4 19/* Also known as Merlot */
8bde63eb 20#define CONFIG_SOC_AU1000 1
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21#else
22#ifdef CONFIG_DBAU1100
8bde63eb 23#define CONFIG_SOC_AU1100 1
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24#else
25#ifdef CONFIG_DBAU1500
8bde63eb 26#define CONFIG_SOC_AU1500 1
d4ca31c4 27#else
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28#ifdef CONFIG_DBAU1550
29/* Cabernet */
8bde63eb 30#define CONFIG_SOC_AU1550 1
ff36fd85 31#else
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32#error "No valid board set"
33#endif
34#endif
35#endif
ff36fd85 36#endif
5da627a4 37
d4ca31c4 38#define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */
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39
40#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
41
42#define CONFIG_BAUDRATE 115200
43
44/* valid baudrates */
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45
46#define CONFIG_TIMESTAMP /* Print image info with timestamp */
47#undef CONFIG_BOOTARGS
48
49#define CONFIG_EXTRA_ENV_SETTINGS \
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50 "addmisc=setenv bootargs ${bootargs} " \
51 "console=ttyS0,${baudrate} " \
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52 "panic=1\0" \
53 "bootfile=/tftpboot/vmlinux.srec\0" \
fe126d8b 54 "load=tftp 80500000 ${u-boot}\0" \
5da627a4 55 ""
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56
57#ifdef CONFIG_DBAU1550
58/* Boot from flash by default, revert to bootp */
59#define CONFIG_BOOTCOMMAND "bootm 0xbfc20000; bootp; bootm"
ff36fd85 60#else /* CONFIG_DBAU1550 */
ad88297e 61#define CONFIG_BOOTCOMMAND "bootp;bootm"
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62#endif /* CONFIG_DBAU1550 */
63
ab999ba1 64
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65/*
66 * BOOTP options
67 */
68#define CONFIG_BOOTP_BOOTFILESIZE
69#define CONFIG_BOOTP_BOOTPATH
70#define CONFIG_BOOTP_GATEWAY
71#define CONFIG_BOOTP_HOSTNAME
72
73
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74/*
75 * Command line configuration.
76 */
77#include <config_cmd_default.h>
78
79#undef CONFIG_CMD_BDI
80#undef CONFIG_CMD_BEDBUG
81#undef CONFIG_CMD_ELF
bdab39d3 82#undef CONFIG_CMD_SAVEENV
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83#undef CONFIG_CMD_FAT
84#undef CONFIG_CMD_FPGA
85#undef CONFIG_CMD_MII
86#undef CONFIG_CMD_RUN
87
88
89#ifdef CONFIG_DBAU1550
90
91#define CONFIG_CMD_FLASH
92#define CONFIG_CMD_LOADB
93#define CONFIG_CMD_NET
94
95#undef CONFIG_CMD_I2C
96#undef CONFIG_CMD_IDE
97#undef CONFIG_CMD_NFS
98#undef CONFIG_CMD_PCMCIA
99
100#else
101
102#define CONFIG_CMD_IDE
103#define CONFIG_CMD_DHCP
104
105#undef CONFIG_CMD_FLASH
106#undef CONFIG_CMD_LOADB
107#undef CONFIG_CMD_LOADS
108
109#endif
110
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111
112/*
113 * Miscellaneous configurable options
114 */
6d0f6bcf 115#define CONFIG_SYS_LONGHELP /* undef to save memory */
ff36fd85 116
6d0f6bcf 117#define CONFIG_SYS_PROMPT "DbAu1xx0 # " /* Monitor Command Prompt */
ff36fd85 118
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119#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
120#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
121#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
5da627a4 122
6d0f6bcf 123#define CONFIG_SYS_MALLOC_LEN 128*1024
5da627a4 124
6d0f6bcf 125#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
5da627a4 126
6d0f6bcf 127#define CONFIG_SYS_MHZ 396
ff36fd85 128
6d0f6bcf 129#if (CONFIG_SYS_MHZ % 12) != 0
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130#error "Invalid CPU frequency - must be multiple of 12!"
131#endif
132
6d0f6bcf 133#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
a55d4817 134
6d0f6bcf 135#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
5da627a4 136
6d0f6bcf 137#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */
5da627a4 138
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139#define CONFIG_SYS_MEMTEST_START 0x80100000
140#define CONFIG_SYS_MEMTEST_END 0x80800000
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141
142/*-----------------------------------------------------------------------
143 * FLASH and environment organization
144 */
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145#ifdef CONFIG_DBAU1550
146
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147#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
148#define CONFIG_SYS_MAX_FLASH_SECT (512) /* max number of sectors on one chip */
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149
150#define PHYS_FLASH_1 0xb8000000 /* Flash Bank #1 */
151#define PHYS_FLASH_2 0xbc000000 /* Flash Bank #2 */
152
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153#else /* CONFIG_DBAU1550 */
154
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155#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
156#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
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157
158#define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */
159#define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */
160
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161#endif /* CONFIG_DBAU1550 */
162
6d0f6bcf 163#define CONFIG_SYS_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2}
ad88297e 164
6d0f6bcf 165#define CONFIG_SYS_FLASH_CFI 1
00b1883a 166#define CONFIG_FLASH_CFI_DRIVER 1
ff36fd85 167
5da627a4 168/* The following #defines are needed to get flash environment right */
14d0a02a 169#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf 170#define CONFIG_SYS_MONITOR_LEN (192 << 10)
5da627a4 171
6d0f6bcf 172#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
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173
174/* We boot from this flash, selected with dip switch */
6d0f6bcf 175#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2
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176
177/* timeout values are in ticks */
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178#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
179#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
5da627a4 180
93f6d725 181#define CONFIG_ENV_IS_NOWHERE 1
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182
183/* Address and size of Primary Environment Sector */
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184#define CONFIG_ENV_ADDR 0xB0030000
185#define CONFIG_ENV_SIZE 0x10000
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186
187#define CONFIG_FLASH_16BIT
188
189#define CONFIG_NR_DRAM_BANKS 2
190
5da627a4 191
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192#ifdef CONFIG_DBAU1550
193#define MEM_SIZE 192
194#else
195#define MEM_SIZE 64
196#endif
197
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198#define CONFIG_MEMSIZE_IN_BYTES
199
ff36fd85 200#ifndef CONFIG_DBAU1550
5da627a4 201/*---ATA PCMCIA ------------------------------------*/
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202#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
203#define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000
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204#define CONFIG_PCMCIA_SLOT_A
205
206#define CONFIG_ATAPI 1
207#define CONFIG_MAC_PARTITION 1
208
209/* We run CF in "true ide" mode or a harddrive via pcmcia */
210#define CONFIG_IDE_PCMCIA 1
211
212/* We only support one slot for now */
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213#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
214#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
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215
216#undef CONFIG_IDE_LED /* LED for ide not supported */
217#undef CONFIG_IDE_RESET /* reset for ide not supported */
218
6d0f6bcf 219#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
5da627a4 220
6d0f6bcf 221#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
5da627a4 222
d4ca31c4 223/* Offset for data I/O */
6d0f6bcf 224#define CONFIG_SYS_ATA_DATA_OFFSET 8
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225
226/* Offset for normal register accesses */
6d0f6bcf 227#define CONFIG_SYS_ATA_REG_OFFSET 0
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228
229/* Offset for alternate registers */
6d0f6bcf 230#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
ff36fd85 231#endif /* CONFIG_DBAU1550 */
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232
233/*-----------------------------------------------------------------------
234 * Cache Configuration
235 */
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236#define CONFIG_SYS_DCACHE_SIZE 16384
237#define CONFIG_SYS_ICACHE_SIZE 16384
238#define CONFIG_SYS_CACHELINE_SIZE 32
5da627a4 239
5da627a4 240#endif /* __CONFIG_H */