]>
Commit | Line | Data |
---|---|---|
463ec1ca VZ |
1 | /* |
2 | * Embest/Timll DevKit3250 board configuration file | |
3 | * | |
768ddeee | 4 | * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com> |
463ec1ca | 5 | * |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
463ec1ca VZ |
7 | */ |
8 | ||
9 | #ifndef __CONFIG_DEVKIT3250_H__ | |
10 | #define __CONFIG_DEVKIT3250_H__ | |
11 | ||
12 | /* SoC and board defines */ | |
1ace4022 | 13 | #include <linux/sizes.h> |
463ec1ca VZ |
14 | #include <asm/arch/cpu.h> |
15 | ||
463ec1ca VZ |
16 | #define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT3250 |
17 | ||
18 | #define CONFIG_SYS_ICACHE_OFF | |
19 | #define CONFIG_SYS_DCACHE_OFF | |
e9b3ce3f | 20 | #if !defined(CONFIG_SPL_BUILD) |
463ec1ca | 21 | #define CONFIG_SKIP_LOWLEVEL_INIT |
e9b3ce3f | 22 | #endif |
463ec1ca VZ |
23 | |
24 | /* | |
25 | * Memory configurations | |
26 | */ | |
27 | #define CONFIG_NR_DRAM_BANKS 1 | |
463ec1ca | 28 | #define CONFIG_SYS_MALLOC_LEN SZ_1M |
463ec1ca VZ |
29 | #define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE |
30 | #define CONFIG_SYS_SDRAM_SIZE SZ_64M | |
6cbaf4c1 | 31 | #define CONFIG_SYS_TEXT_BASE 0x83F00000 |
463ec1ca VZ |
32 | #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + SZ_32K) |
33 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - SZ_1M) | |
34 | ||
35 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K) | |
36 | ||
37 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \ | |
38 | - GENERATED_GBL_DATA_SIZE) | |
39 | ||
40 | /* | |
41 | * Serial Driver | |
42 | */ | |
768ddeee | 43 | #define CONFIG_SYS_LPC32XX_UART 5 /* UART5 */ |
463ec1ca | 44 | |
6cbaf4c1 VZ |
45 | /* |
46 | * DMA | |
47 | */ | |
48 | #if !defined(CONFIG_SPL_BUILD) | |
49 | #define CONFIG_DMA_LPC32XX | |
50 | #endif | |
51 | ||
768ddeee VZ |
52 | /* |
53 | * I2C | |
54 | */ | |
55 | #define CONFIG_SYS_I2C | |
56 | #define CONFIG_SYS_I2C_LPC32XX | |
57 | #define CONFIG_SYS_I2C_SPEED 100000 | |
768ddeee VZ |
58 | |
59 | /* | |
60 | * GPIO | |
61 | */ | |
62 | #define CONFIG_LPC32XX_GPIO | |
768ddeee VZ |
63 | |
64 | /* | |
65 | * SSP/SPI | |
66 | */ | |
67 | #define CONFIG_LPC32XX_SSP | |
68 | #define CONFIG_LPC32XX_SSP_TIMEOUT 100000 | |
768ddeee VZ |
69 | |
70 | /* | |
71 | * Ethernet | |
72 | */ | |
73 | #define CONFIG_RMII | |
74 | #define CONFIG_PHY_SMSC | |
75 | #define CONFIG_LPC32XX_ETH | |
76 | #define CONFIG_PHYLIB | |
77 | #define CONFIG_PHY_ADDR 0x1F | |
78 | #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
768ddeee | 79 | |
463ec1ca VZ |
80 | /* |
81 | * NOR Flash | |
82 | */ | |
463ec1ca VZ |
83 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
84 | #define CONFIG_SYS_MAX_FLASH_SECT 71 | |
85 | #define CONFIG_SYS_FLASH_BASE EMC_CS0_BASE | |
86 | #define CONFIG_SYS_FLASH_SIZE SZ_4M | |
87 | #define CONFIG_SYS_FLASH_CFI | |
88 | ||
768ddeee VZ |
89 | /* |
90 | * NAND controller | |
91 | */ | |
92 | #define CONFIG_NAND_LPC32XX_SLC | |
93 | #define CONFIG_SYS_NAND_BASE SLC_NAND_BASE | |
94 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
95 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } | |
96 | ||
97 | /* | |
98 | * NAND chip timings | |
99 | */ | |
100 | #define CONFIG_LPC32XX_NAND_SLC_WDR_CLKS 14 | |
101 | #define CONFIG_LPC32XX_NAND_SLC_WWIDTH 66666666 | |
102 | #define CONFIG_LPC32XX_NAND_SLC_WHOLD 200000000 | |
103 | #define CONFIG_LPC32XX_NAND_SLC_WSETUP 50000000 | |
104 | #define CONFIG_LPC32XX_NAND_SLC_RDR_CLKS 14 | |
105 | #define CONFIG_LPC32XX_NAND_SLC_RWIDTH 66666666 | |
106 | #define CONFIG_LPC32XX_NAND_SLC_RHOLD 200000000 | |
107 | #define CONFIG_LPC32XX_NAND_SLC_RSETUP 50000000 | |
108 | ||
327f0d23 VZ |
109 | #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 |
110 | #define CONFIG_SYS_NAND_PAGE_SIZE NAND_LARGE_BLOCK_PAGE_SIZE | |
768ddeee | 111 | #define CONFIG_SYS_NAND_USE_FLASH_BBT |
327f0d23 | 112 | |
6cbaf4c1 | 113 | #define CONFIG_CMD_JFFS2 |
768ddeee VZ |
114 | #define CONFIG_CMD_NAND |
115 | ||
6cbaf4c1 VZ |
116 | /* |
117 | * USB | |
118 | */ | |
119 | #define CONFIG_USB_OHCI_LPC32XX | |
120 | #define CONFIG_USB_ISP1301_I2C_ADDR 0x2d | |
6cbaf4c1 | 121 | |
463ec1ca VZ |
122 | /* |
123 | * U-Boot General Configurations | |
124 | */ | |
125 | #define CONFIG_SYS_LONGHELP | |
463ec1ca VZ |
126 | #define CONFIG_SYS_CBSIZE 1024 |
127 | #define CONFIG_SYS_PBSIZE \ | |
128 | (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
129 | #define CONFIG_SYS_MAXARGS 16 | |
130 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
131 | ||
132 | #define CONFIG_AUTO_COMPLETE | |
133 | #define CONFIG_CMDLINE_EDITING | |
463ec1ca | 134 | |
768ddeee VZ |
135 | /* |
136 | * Pass open firmware flat tree | |
137 | */ | |
768ddeee VZ |
138 | |
139 | /* | |
140 | * Environment | |
141 | */ | |
142 | #define CONFIG_ENV_IS_IN_NAND 1 | |
463ec1ca | 143 | #define CONFIG_ENV_SIZE SZ_128K |
768ddeee VZ |
144 | #define CONFIG_ENV_OFFSET 0x000A0000 |
145 | ||
146 | #define CONFIG_BOOTCOMMAND \ | |
147 | "dhcp; " \ | |
148 | "tftp ${loadaddr} ${serverip}:${tftpdir}/${bootfile}; " \ | |
149 | "tftp ${dtbaddr} ${serverip}:${tftpdir}/devkit3250.dtb; " \ | |
150 | "setenv nfsargs ip=dhcp root=/dev/nfs nfsroot=${serverip}:${nfsroot},tcp; " \ | |
151 | "setenv bootargs ${bootargs} ${nfsargs} ${userargs}; " \ | |
152 | "bootm ${loadaddr} - ${dtbaddr}" | |
153 | ||
154 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
155 | "autoload=no\0" \ | |
156 | "ethaddr=00:01:90:00:C0:81\0" \ | |
157 | "dtbaddr=0x81000000\0" \ | |
158 | "nfsroot=/opt/projects/images/vladimir/oe/devkit3250/rootfs\0" \ | |
159 | "tftpdir=vladimir/oe/devkit3250\0" \ | |
160 | "userargs=oops=panic\0" | |
463ec1ca VZ |
161 | |
162 | /* | |
163 | * U-Boot Commands | |
164 | */ | |
463ec1ca VZ |
165 | |
166 | /* | |
167 | * Boot Linux | |
168 | */ | |
169 | #define CONFIG_CMDLINE_TAG | |
170 | #define CONFIG_SETUP_MEMORY_TAGS | |
463ec1ca VZ |
171 | |
172 | #define CONFIG_BOOTFILE "uImage" | |
768ddeee | 173 | #define CONFIG_BOOTARGS "console=ttyS0,115200n8" |
463ec1ca VZ |
174 | #define CONFIG_LOADADDR 0x80008000 |
175 | ||
e9b3ce3f VZ |
176 | /* |
177 | * SPL specific defines | |
178 | */ | |
179 | /* SPL will be executed at offset 0 */ | |
180 | #define CONFIG_SPL_TEXT_BASE 0x00000000 | |
181 | ||
182 | /* SPL will use SRAM as stack */ | |
183 | #define CONFIG_SPL_STACK 0x0000FFF8 | |
e9b3ce3f VZ |
184 | |
185 | /* Use the framework and generic lib */ | |
186 | #define CONFIG_SPL_FRAMEWORK | |
e9b3ce3f VZ |
187 | |
188 | /* SPL will use serial */ | |
e9b3ce3f VZ |
189 | |
190 | /* SPL loads an image from NAND */ | |
191 | #define CONFIG_SPL_NAND_SIMPLE | |
192 | #define CONFIG_SPL_NAND_RAW_ONLY | |
e9b3ce3f VZ |
193 | #define CONFIG_SPL_NAND_DRIVERS |
194 | ||
e9b3ce3f VZ |
195 | #define CONFIG_SPL_NAND_ECC |
196 | #define CONFIG_SPL_NAND_SOFTECC | |
197 | ||
198 | #define CONFIG_SPL_MAX_SIZE 0x20000 | |
199 | #define CONFIG_SPL_PAD_TO CONFIG_SPL_MAX_SIZE | |
200 | ||
201 | /* U-Boot will be 0x60000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */ | |
202 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 | |
203 | #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000 | |
204 | ||
205 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE | |
206 | #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE | |
207 | ||
208 | /* See common/spl/spl.c spl_set_header_raw_uboot() */ | |
209 | #define CONFIG_SYS_MONITOR_LEN CONFIG_SYS_NAND_U_BOOT_SIZE | |
210 | ||
463ec1ca VZ |
211 | /* |
212 | * Include SoC specific configuration | |
213 | */ | |
214 | #include <asm/arch/config.h> | |
215 | ||
216 | #endif /* __CONFIG_DEVKIT3250_H__*/ |