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c35d7cf0 FK |
1 | /* |
2 | * (C) Copyright 2006-2008 | |
3 | * Texas Instruments. | |
4 | * Richard Woodruff <r-woodruff2@ti.com> | |
5 | * Syed Mohammed Khasim <x0khasim@ti.com> | |
6 | * | |
7 | * (C) Copyright 2009 | |
8 | * Frederik Kriewitz <frederik@kriewitz.eu> | |
9 | * | |
10 | * Configuration settings for the DevKit8000 board. | |
11 | * | |
12 | * See file CREDITS for list of people who contributed to this | |
13 | * project. | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License as | |
17 | * published by the Free Software Foundation; either version 2 of | |
18 | * the License, or (at your option) any later version. | |
19 | * | |
20 | * This program is distributed in the hope that it will be useful, | |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
24 | * | |
25 | * You should have received a copy of the GNU General Public License | |
26 | * along with this program; if not, write to the Free Software | |
27 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
28 | * MA 02111-1307 USA | |
29 | */ | |
30 | ||
31 | #ifndef __CONFIG_H | |
32 | #define __CONFIG_H | |
c35d7cf0 FK |
33 | |
34 | /* High Level Configuration Options */ | |
c35d7cf0 FK |
35 | #define CONFIG_OMAP 1 /* in a TI OMAP core */ |
36 | #define CONFIG_OMAP34XX 1 /* which is a 34XX */ | |
c35d7cf0 | 37 | #define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */ |
2d52a9a3 | 38 | #define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT8000 |
308252ad MV |
39 | #define CONFIG_OMAP_GPIO |
40 | ||
5183b7ec SS |
41 | /* |
42 | * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM | |
43 | * 64 bytes before this address should be set aside for u-boot.img's | |
44 | * header. That is 0x800FFFC0--0x80100000 should not be used for any | |
45 | * other needs. | |
46 | */ | |
47 | #define CONFIG_SYS_TEXT_BASE 0x80100000 | |
66fca016 | 48 | |
cae377b5 VH |
49 | #define CONFIG_SDRC /* The chip has SDRC controller */ |
50 | ||
c35d7cf0 FK |
51 | #include <asm/arch/cpu.h> /* get chip and board defs */ |
52 | #include <asm/arch/omap3.h> | |
53 | ||
54 | /* Display CPU and Board information */ | |
55 | #define CONFIG_DISPLAY_CPUINFO 1 | |
56 | #define CONFIG_DISPLAY_BOARDINFO 1 | |
57 | ||
58 | /* Clock Defines */ | |
59 | #define V_OSCK 26000000 /* Clock output from T2 */ | |
60 | #define V_SCLK (V_OSCK >> 1) | |
61 | ||
c35d7cf0 FK |
62 | #define CONFIG_MISC_INIT_R |
63 | ||
64 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ | |
65 | #define CONFIG_SETUP_MEMORY_TAGS 1 | |
66 | #define CONFIG_INITRD_TAG 1 | |
67 | #define CONFIG_REVISION_TAG 1 | |
68 | ||
2fa8ca98 GL |
69 | #define CONFIG_OF_LIBFDT 1 |
70 | ||
c35d7cf0 | 71 | /* Size of malloc() pool */ |
9c44ddcc | 72 | #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ |
c35d7cf0 | 73 | /* Sector */ |
9c44ddcc | 74 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) |
c35d7cf0 FK |
75 | |
76 | /* Hardware drivers */ | |
c35d7cf0 | 77 | /* DM9000 */ |
c35d7cf0 FK |
78 | #define CONFIG_NET_RETRY_COUNT 20 |
79 | #define CONFIG_DRIVER_DM9000 1 | |
80 | #define CONFIG_DM9000_BASE 0x2c000000 | |
81 | #define DM9000_IO CONFIG_DM9000_BASE | |
82 | #define DM9000_DATA (CONFIG_DM9000_BASE + 0x400) | |
83 | #define CONFIG_DM9000_USE_16BIT 1 | |
84 | #define CONFIG_DM9000_NO_SROM 1 | |
85 | #undef CONFIG_DM9000_DEBUG | |
86 | ||
87 | /* NS16550 Configuration */ | |
88 | #define CONFIG_SYS_NS16550 | |
89 | #define CONFIG_SYS_NS16550_SERIAL | |
90 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) | |
91 | #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ | |
92 | ||
93 | /* select serial console configuration */ | |
94 | #define CONFIG_CONS_INDEX 3 | |
95 | #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 | |
96 | #define CONFIG_SERIAL3 3 | |
97 | #define CONFIG_BAUDRATE 115200 | |
98 | #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ | |
99 | 115200} | |
100 | ||
101 | /* MMC */ | |
f408501d | 102 | #define CONFIG_GENERIC_MMC 1 |
c35d7cf0 | 103 | #define CONFIG_MMC 1 |
f408501d | 104 | #define CONFIG_OMAP_HSMMC 1 |
c35d7cf0 FK |
105 | #define CONFIG_DOS_PARTITION 1 |
106 | ||
107 | /* I2C */ | |
0297ec7e | 108 | #define CONFIG_HARD_I2C 1 |
c35d7cf0 FK |
109 | #define CONFIG_SYS_I2C_SPEED 100000 |
110 | #define CONFIG_SYS_I2C_SLAVE 1 | |
c35d7cf0 FK |
111 | #define CONFIG_DRIVER_OMAP34XX_I2C 1 |
112 | ||
113 | /* TWL4030 */ | |
114 | #define CONFIG_TWL4030_POWER 1 | |
115 | #define CONFIG_TWL4030_LED 1 | |
116 | ||
117 | /* Board NAND Info */ | |
118 | #define CONFIG_SYS_NO_FLASH /* no NOR flash */ | |
119 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ | |
120 | #define MTDIDS_DEFAULT "nand0=nand" | |
121 | #define MTDPARTS_DEFAULT "mtdparts=nand:" \ | |
122 | "512k(x-loader)," \ | |
123 | "1920k(u-boot)," \ | |
124 | "128k(u-boot-env)," \ | |
125 | "4m(kernel)," \ | |
126 | "-(fs)" | |
127 | ||
128 | #define CONFIG_NAND_OMAP_GPMC | |
129 | #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ | |
130 | /* to access nand */ | |
131 | #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ | |
132 | /* to access nand at */ | |
133 | /* CS0 */ | |
134 | #define GPMC_NAND_ECC_LP_x16_LAYOUT 1 | |
135 | ||
136 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ | |
137 | /* devices */ | |
c35d7cf0 FK |
138 | #define CONFIG_JFFS2_NAND |
139 | /* nand device jffs2 lives on */ | |
140 | #define CONFIG_JFFS2_DEV "nand0" | |
141 | /* start of jffs2 partition */ | |
142 | #define CONFIG_JFFS2_PART_OFFSET 0x680000 | |
143 | #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ | |
144 | /* partition */ | |
145 | ||
146 | /* commands to include */ | |
147 | #include <config_cmd_default.h> | |
148 | ||
149 | #define CONFIG_CMD_DHCP /* DHCP support */ | |
150 | #define CONFIG_CMD_EXT2 /* EXT2 Support */ | |
151 | #define CONFIG_CMD_FAT /* FAT support */ | |
152 | #define CONFIG_CMD_I2C /* I2C serial bus support */ | |
153 | #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ | |
154 | #define CONFIG_CMD_MMC /* MMC support */ | |
155 | #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ | |
156 | #define CONFIG_CMD_NAND /* NAND support */ | |
157 | #define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */ | |
158 | ||
159 | #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ | |
160 | #undef CONFIG_CMD_IMI /* iminfo */ | |
161 | ||
162 | /* BOOTP/DHCP options */ | |
163 | #define CONFIG_BOOTP_SUBNETMASK | |
164 | #define CONFIG_BOOTP_GATEWAY | |
165 | #define CONFIG_BOOTP_HOSTNAME | |
166 | #define CONFIG_BOOTP_NISDOMAIN | |
167 | #define CONFIG_BOOTP_BOOTPATH | |
168 | #define CONFIG_BOOTP_BOOTFILESIZE | |
169 | #define CONFIG_BOOTP_DNS | |
170 | #define CONFIG_BOOTP_DNS2 | |
171 | #define CONFIG_BOOTP_SEND_HOSTNAME | |
172 | #define CONFIG_BOOTP_NTPSERVER | |
173 | #define CONFIG_BOOTP_TIMEOFFSET | |
174 | #undef CONFIG_BOOTP_VENDOREX | |
175 | ||
176 | /* Environment information */ | |
177 | #define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */ | |
178 | ||
179 | #define CONFIG_BOOTDELAY 3 | |
180 | ||
181 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
182 | "loadaddr=0x82000000\0" \ | |
2d76da24 | 183 | "console=ttyO2,115200n8\0" \ |
f408501d | 184 | "mmcdev=0\0" \ |
c35d7cf0 FK |
185 | "vram=12M\0" \ |
186 | "dvimode=1024x768MR-16@60\0" \ | |
187 | "defaultdisplay=dvi\0" \ | |
188 | "nfsopts=hard,tcp,rsize=65536,wsize=65536\0" \ | |
189 | "kernelopts=rw\0" \ | |
190 | "commonargs=" \ | |
191 | "setenv bootargs console=${console} " \ | |
192 | "vram=${vram} " \ | |
193 | "omapfb.mode=dvi:${dvimode} " \ | |
194 | "omapdss.def_disp=${defaultdisplay}\0" \ | |
195 | "mmcargs=" \ | |
196 | "run commonargs; " \ | |
197 | "setenv bootargs ${bootargs} " \ | |
198 | "root=/dev/mmcblk0p2 " \ | |
b72db208 | 199 | "rootwait " \ |
c35d7cf0 FK |
200 | "${kernelopts}\0" \ |
201 | "nandargs=" \ | |
202 | "run commonargs; " \ | |
203 | "setenv bootargs ${bootargs} " \ | |
204 | "omapfb.mode=dvi:${dvimode} " \ | |
205 | "omapdss.def_disp=${defaultdisplay} " \ | |
206 | "root=/dev/mtdblock4 " \ | |
207 | "rootfstype=jffs2 " \ | |
208 | "${kernelopts}\0" \ | |
209 | "netargs=" \ | |
210 | "run commonargs; " \ | |
211 | "setenv bootargs ${bootargs} " \ | |
212 | "root=/dev/nfs " \ | |
213 | "nfsroot=${serverip}:${rootpath},${nfsopts} " \ | |
214 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \ | |
215 | "${kernelopts} " \ | |
216 | "dnsip1=${dnsip} " \ | |
217 | "dnsip2=${dnsip2}\0" \ | |
f408501d | 218 | "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ |
c35d7cf0 FK |
219 | "bootscript=echo Running bootscript from mmc ...; " \ |
220 | "source ${loadaddr}\0" \ | |
f408501d | 221 | "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ |
c35d7cf0 FK |
222 | "eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \ |
223 | "mmcboot=echo Booting from mmc ...; " \ | |
224 | "run mmcargs; " \ | |
225 | "bootm ${loadaddr}\0" \ | |
226 | "nandboot=echo Booting from nand ...; " \ | |
227 | "run nandargs; " \ | |
228 | "nand read ${loadaddr} 280000 400000; " \ | |
229 | "bootm ${loadaddr}\0" \ | |
230 | "netboot=echo Booting from network ...; " \ | |
231 | "dhcp ${loadaddr}; " \ | |
232 | "run netargs; " \ | |
233 | "bootm ${loadaddr}\0" \ | |
66968110 | 234 | "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \ |
c35d7cf0 FK |
235 | "if run loadbootscript; then " \ |
236 | "run bootscript; " \ | |
237 | "else " \ | |
238 | "if run loaduimage; then " \ | |
239 | "run mmcboot; " \ | |
240 | "else run nandboot; " \ | |
241 | "fi; " \ | |
242 | "fi; " \ | |
243 | "else run nandboot; fi\0" | |
244 | ||
245 | ||
246 | #define CONFIG_BOOTCOMMAND "run autoboot" | |
247 | ||
248 | /* Miscellaneous configurable options */ | |
249 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
250 | #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ | |
251 | #define CONFIG_AUTO_COMPLETE 1 | |
c35d7cf0 FK |
252 | #define CONFIG_SYS_PROMPT "OMAP3 DevKit8000 # " |
253 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ | |
254 | /* Print Buffer Size */ | |
255 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
256 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
257 | #define CONFIG_SYS_MAXARGS 128 /* max number of command args */ | |
258 | ||
259 | /* Boot Argument Buffer Size */ | |
260 | #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) | |
261 | ||
262 | #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x07000000) | |
263 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ | |
264 | 0x01000000) /* 16MB */ | |
265 | ||
266 | #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000) | |
267 | ||
268 | /* | |
269 | * OMAP3 has 12 GP timers, they can be driven by the system clock | |
270 | * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). | |
271 | * This rate is divided by a local divisor. | |
272 | */ | |
273 | #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) | |
274 | #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ | |
275 | #define CONFIG_SYS_HZ 1000 | |
276 | ||
c35d7cf0 FK |
277 | /* Physical Memory Map */ |
278 | #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ | |
279 | #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 | |
c35d7cf0 FK |
280 | #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 |
281 | ||
c35d7cf0 FK |
282 | /* NAND and environment organization */ |
283 | #define PISMO1_NAND_SIZE GPMC_SIZE_128M | |
284 | ||
9c44ddcc | 285 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ |
c35d7cf0 FK |
286 | |
287 | #define CONFIG_ENV_IS_IN_NAND 1 | |
288 | #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ | |
289 | ||
6cbec7b3 | 290 | #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET |
c35d7cf0 | 291 | |
66fca016 | 292 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
30f305c9 TW |
293 | #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 |
294 | #define CONFIG_SYS_INIT_RAM_SIZE 0x800 | |
295 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ | |
296 | CONFIG_SYS_INIT_RAM_SIZE - \ | |
297 | GENERATED_GBL_DATA_SIZE) | |
66fca016 | 298 | |
3f6a4922 SS |
299 | /* SRAM config */ |
300 | #define CONFIG_SYS_SRAM_START 0x40200000 | |
301 | #define CONFIG_SYS_SRAM_SIZE 0x10000 | |
302 | ||
303 | /* Defines for SPL */ | |
304 | #define CONFIG_SPL | |
47f7bcae | 305 | #define CONFIG_SPL_FRAMEWORK |
3f6a4922 SS |
306 | #define CONFIG_SPL_NAND_SIMPLE |
307 | ||
308 | #define CONFIG_SPL_LIBCOMMON_SUPPORT | |
309 | #define CONFIG_SPL_LIBDISK_SUPPORT | |
ee08a826 | 310 | #define CONFIG_SPL_BOARD_INIT |
3f6a4922 SS |
311 | #define CONFIG_SPL_I2C_SUPPORT |
312 | #define CONFIG_SPL_LIBGENERIC_SUPPORT | |
313 | #define CONFIG_SPL_SERIAL_SUPPORT | |
16e41c85 | 314 | #define CONFIG_SPL_GPIO_SUPPORT |
3f6a4922 SS |
315 | #define CONFIG_SPL_POWER_SUPPORT |
316 | #define CONFIG_SPL_NAND_SUPPORT | |
6f2f01b9 SW |
317 | #define CONFIG_SPL_NAND_BASE |
318 | #define CONFIG_SPL_NAND_DRIVERS | |
319 | #define CONFIG_SPL_NAND_ECC | |
99154714 SS |
320 | #define CONFIG_SPL_MMC_SUPPORT |
321 | #define CONFIG_SPL_FAT_SUPPORT | |
3f6a4922 | 322 | #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" |
99154714 SS |
323 | #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" |
324 | #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 | |
325 | #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ | |
3f6a4922 SS |
326 | |
327 | #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ | |
e0820ccc | 328 | #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ |
3f6a4922 SS |
329 | #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK |
330 | ||
2d52a9a3 | 331 | #define CONFIG_SPL_BSS_START_ADDR 0x80000500 /* leave space for bootargs*/ |
3f6a4922 SS |
332 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 |
333 | ||
334 | /* NAND boot config */ | |
c471ccb9 | 335 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE |
3f6a4922 SS |
336 | #define CONFIG_SYS_NAND_PAGE_COUNT 64 |
337 | #define CONFIG_SYS_NAND_PAGE_SIZE 2048 | |
338 | #define CONFIG_SYS_NAND_OOBSIZE 64 | |
339 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) | |
340 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 | |
341 | #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ | |
342 | 10, 11, 12, 13} | |
343 | ||
344 | #define CONFIG_SYS_NAND_ECCSIZE 512 | |
345 | #define CONFIG_SYS_NAND_ECCBYTES 3 | |
346 | ||
3f6a4922 SS |
347 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE |
348 | ||
349 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 | |
350 | #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000 | |
351 | ||
5183b7ec | 352 | #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 |
ba75a81a TR |
353 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ |
354 | ||
d38bc97d | 355 | /* SPL OS boot options */ |
2d52a9a3 SS |
356 | #define CONFIG_SPL_OS_BOOT |
357 | #define CONFIG_SPL_OS_BOOT_KEY 26 | |
358 | ||
d38bc97d SS |
359 | #define CONFIG_CMD_SPL |
360 | #define CONFIG_CMD_SPL_WRITE_SIZE 0x400 /* 1024 byte */ | |
361 | #define CONFIG_CMD_SPL_NAND_OFS (CONFIG_SYS_NAND_SPL_KERNEL_OFFS+\ | |
362 | 0x400000) | |
363 | #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 | |
364 | #define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100) | |
365 | ||
c35d7cf0 | 366 | #endif /* __CONFIG_H */ |