[people/ms/u-boot.git] / include / configs / digsy_mtc.h

/*
 * (C) Copyright 2003-2004
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2005-2007
 * Modified for InterControl digsyMTC MPC5200 board by
 * Frank Bodammer, GCD Hard- & Software GmbH,
 *                 frank.bodammer@gcd-solutions.de
 *
 * (C) Copyright 2009 Semihalf
 * Optimized for digsyMTC by: Grzegorz Bernacki <gjb@semihalf.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software\; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation\; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY\; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program\; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */

#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
#define CONFIG_MPC5200		1	/* (more precisely an MPC5200 CPU) */
#define CONFIG_DIGSY_MTC	1	/* ... on InterControl digsyMTC board */

#define CONFIG_SYS_MPC5XXX_CLKIN	33000000

#define BOOTFLAG_COLD		0x01
#define BOOTFLAG_WARM		0x02

#define CONFIG_SYS_CACHELINE_SIZE	32

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	4	/* console is on PSC4  */
#define CONFIG_BAUDRATE		115200	/* ... at 115200  bps  */
#define CONFIG_SYS_BAUDRATE_TABLE	\
	{ 9600, 19200, 38400, 57600, 115200, 230400 }

/*
 * PCI Mapping:
 * 0x40000000 - 0x4fffffff - PCI Memory
 * 0x50000000 - 0x50ffffff - PCI IO Space
 */
#define CONFIG_PCI		1
#define CONFIG_PCI_PNP		1
#define CONFIG_PCI_SCAN_SHOW	1

#define CONFIG_PCI_MEM_BUS	0x40000000
#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE	0x10000000

#define CONFIG_PCI_IO_BUS	0x50000000
#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE	0x01000000

/*
 *  Partitions
 */
#define CONFIG_DOS_PARTITION
#define CONFIG_BZIP2

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DFL
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IDE
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MII
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_SPI
#define CONFIG_CMD_USB

#if (TEXT_BASE == 0xFF000000)
#define CONFIG_SYS_LOWBOOT	1
#endif

/*
 * Autobooting
 */
#define CONFIG_BOOTDELAY	1

#undef	CONFIG_BOOTARGS

#define CONFIG_EXTRA_ENV_SETTINGS					\
	"fw_image=digsyMPC.img\0"					\
	"mtcb_start=mtc led diag orange; run mtcb_1\0"			\
	"mtcb_clearled=for x in user1 user2 usbpwr usbbusy; "		\
		"do mtc led $x; done\0"					\
	"mtcb_1=if mtc key; then run mtcb_clearled mtcb_update; "	\
		"else run mtcb_fw; fi\0"				\
	"mtcb_fw=if bootm ff000000; then echo FIRMWARE OK!; "		\
		"else echo BAD FIRMWARE CRC!; mtc led diag red; fi\0"	\
	"mtcb_update=mtc led user1 orange;"				\
		"while mtc key; do ; done; run mtcb_2;\0"		\
	"mtcb_2=mtc led user1 green 2; usb reset; run mtcb_usb1;\0"	\
	"mtcb_usb1=if fatload usb 0 400000 script.img; "		\
		"then run mtcb_doscript; else run mtcb_usb2; fi\0"	\
	"mtcb_usb2=if fatload usb 0 400000 $fw_image; "			\
		"then run mtcb_dousb; else run mtcb_ide; fi\0"		\
	"mtcb_doscript=run mtcb_usbleds; mtc led user2 orange 2; "	\
		"run mtcb_wait_flickr mtcb_ds_1;\0"			\
	"mtcb_ds_1=if imi 400000; then mtc led usbbusy; "		\
		"source 400000; else run mtcb_error; fi\0"		\
	"mtcb_dousb=run mtcb_usbleds mtcb_wait_flickr mtcb_du_1;\0"	\
	"mtcb_du_1=if imi 400000; then run mtcb_du_2; "			\
		"else run mtcb_error; fi\0"				\
	"mtcb_du_2=run mtcb_clear mtcb_prog; mtc led usbbusy; "		\
		"run mtcb_checkfw\0"					\
	"mtcb_checkfw=if imi ff000000; then run mtcb_success; "		\
		"else run mtcb_error; fi\0"				\
	"mtcb_waitkey=mtc key; until test $? -eq 0; do mtc key; done\0"	\
	"mtcb_wait_flickr=run mtcb_waitkey mtcb_uledflckr\0"		\
	"mtcb_usbleds=mtc led usbpwr green; mtc led usbbusy orange 1;\0"\
	"mtcb_uledflckr=mtc led user1 orange 11\0"			\
	"mtcb_error=mtc led user1 red\0"				\
	"mtcb_clear=erase ff000000 ff0fffff\0"				\
	"mtcb_prog=cp.b 400000 ff000000 ${filesize}\0"			\
	"mtcb_success=mtc led user1 green\0"				\
	"mtcb_ide=if fatload ide 0 400000 $fw_image;"			\
		"then run mtcb_doide; else run mtcb_error; fi\0"	\
	"mtcb_doide=mtc led user2 green 1;"				\
		"run mtcb_wait_flickr mtcb_di_1;\0"			\
	"mtcb_di_1=if imi 400000; then run mtcb_di_2;"			\
		"else run mtcb_error; fi\0"				\
	"mtcb_di_2=run mtcb_clear; run mtcb_prog mtcb_checkfw\0"	\
	"ramdisk_num_sector=16\0"					\
	"flash_base=ff000000\0"						\
	"flashdisk_size=e00000\0"					\
	"env_sector=fff60000\0"						\
	"flashdisk_start=ff100000\0"					\
	"load_cmd=tftp 400000 digsyMPC.img\0"				\
	"clear_cmd=erase ff000000 ff0fffff\0"				\
	"flash_cmd=cp.b 400000 ff000000 ${filesize}\0"			\
	"update_cmd=run load_cmd; "					\
	"iminfo 400000; "						\
	"run clear_cmd flash_cmd; "					\
	"iminfo ff000000\0"						\
	"spi_driver=yes\0"						\
	"spi_watchdog=no\0"						\
	"ftps_start=yes\0"						\
	"ftps_user1=admin\0"						\
	"ftps_pass1=admin\0"						\
	"ftps_base1=/\0"						\
	"ftps_home1=/\0"						\
	"plc_sio_srv=no\0"						\
	"plc_sio_baud=57600\0"						\
	"plc_sio_parity=no\0"						\
	"plc_sio_stop=1\0"						\
	"plc_sio_com=2\0"						\
	"plc_eth_srv=yes\0"						\
	"plc_eth_port=1200\0"						\
	"plc_root=/ide/\0"						\
	"diag_level=0\0"						\
	"webvisu=no\0"							\
	"plc_can1_routing=no\0"						\
	"plc_can1_baudrate=250\0"					\
	"plc_can2_routing=no\0"						\
	"plc_can2_baudrate=250\0"					\
	"plc_can3_routing=no\0"						\
	"plc_can3_baudrate=250\0"					\
	"plc_can4_routing=no\0"						\
	"plc_can4_baudrate=250\0"					\
	"netdev=eth0\0"							\
	"console=ttyPSC0\0"						\
	"kernel_addr_r=400000\0"					\
	"fdt_addr_r=600000\0"						\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
	"nfsroot=${serverip}:${rootpath}\0"				\
	"addip=setenv bootargs ${bootargs} "				\
	"ip=${ipaddr}:${serverip}:${gatewayip}:"			\
	"${netmask}:${hostname}:${netdev}:off panic=1\0"		\
	"addcons=setenv bootargs ${bootargs} console=${console},${baudrate}\0"\
	"rootpath=/opt/eldk/ppc_6xx\0"					\
	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
		"tftp ${fdt_addr_r} ${fdt_file};"			\
		"run nfsargs addip addcons;"				\
		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
	"load=tftp 200000 ${u-boot}\0"					\
	"update=protect off FFF00000 +${filesize};"			\
		"erase FFF00000 +${filesize};"				\
		"cp.b 200000 FFF00000 ${filesize};"			\
		"protect on FFF00000 +${filesize}\0"			\
	""

#define CONFIG_BOOTCOMMAND	"run mtcb_start"

/*
 * SPI configuration
 */
#define CONFIG_HARD_SPI		1
#define CONFIG_MPC52XX_SPI	1

/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C		1
#define CONFIG_SYS_I2C_MODULE	1
#define CONFIG_SYS_I2C_SPEED	100000
#define CONFIG_SYS_I2C_SLAVE	0x7F

/*
 * EEPROM configuration
 */
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 	1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	70

/*
 * RTC configuration
 */
#define CONFIG_RTC_DS1337
#define CONFIG_SYS_I2C_RTC_ADDR	0x68
#define CONFIG_SYS_DS1339_TCR_VAL	0xAB	/* diode + 4k resistor */

/*
 * Flash configuration
 */
#define	CONFIG_SYS_FLASH_CFI		1
#define	CONFIG_FLASH_CFI_DRIVER	1

#define CONFIG_SYS_FLASH_BASE		0xFF000000
#define CONFIG_SYS_FLASH_SIZE	0x01000000

#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define CONFIG_SYS_MAX_FLASH_SECT	256
#define CONFIG_FLASH_16BIT
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
#define CONFIG_SYS_FLASH_ERASE_TOUT	240000
#define CONFIG_SYS_FLASH_WRITE_TOUT	500

#define CONFIG_OF_LIBFDT  1
#define CONFIG_OF_BOARD_SETUP	1

#define OF_CPU			"PowerPC,5200@0"
#define OF_SOC			"soc5200@f0000000"
#define OF_TBCLK		(bd->bi_busfreq / 4)

#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_MISC_INIT_R

/*
 * Environment settings
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#if defined(CONFIG_LOWBOOT)
#define CONFIG_ENV_ADDR		0xFF060000
#else	/* CONFIG_LOWBOOT */
#define CONFIG_ENV_ADDR		0xFFF60000
#endif	/* CONFIG_LOWBOOT */
#define CONFIG_ENV_SIZE		0x10000
#define CONFIG_ENV_SECT_SIZE	0x20000
#define CONFIG_ENV_OVERWRITE	1

/*
 * Memory map
 */
#define CONFIG_SYS_MBAR		0xF0000000
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#if !defined(CONFIG_SYS_LOWBOOT)
#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
#else
#define CONFIG_SYS_DEFAULT_MBAR	0xF0000000
#endif

/*
 *  Use SRAM until RAM will be available
 */
#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
#define CONFIG_SYS_INIT_RAM_END		MPC5XXX_SRAM_SIZE

#define CONFIG_SYS_GBL_DATA_SIZE	4096
#define CONFIG_SYS_GBL_DATA_OFFSET	\
	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT		1
#endif

#define CONFIG_SYS_MONITOR_LEN	(256 << 10)
#define CONFIG_SYS_MALLOC_LEN	(4096 << 10)
#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)

/*
 * Ethernet configuration
 */
#define CONFIG_MPC5xxx_FEC	1
#define CONFIG_MPC5xxx_FEC_MII100
#define CONFIG_PHY_ADDR		0x00
#define CONFIG_PHY_RESET_DELAY	1000

#define CONFIG_NETCONSOLE		/* include NetConsole support	*/

/*
 * GPIO configuration
 * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1)
 *  Bit 0   (mask 0x80000000) : 0x1
 * SPI on Tmr2/3/4/5 pins
 *  Bit 2:3 (mask 0x30000000) : 0x2
 * ATA cs0/1 on csb_4/5
 *  Bit 6:7 (mask 0x03000000) : 0x2
 * Ethernet 100Mbit with MD
 *  Bits 12:15 (mask 0x000f0000): 0x5
 * USB - Two UARTs
 *  Bits 18:19 (mask 0x00003000) : 0x2
 * PSC3 - USB2 on PSC3
 *  Bits 20:23 (mask 0x00000f00) : 0x1
 * PSC2 - CAN1&2 on PSC2 pins
 *  Bits 25:27 (mask 0x00000070) : 0x1
 * PSC1 - AC97 functionality
 *  Bits 29:31 (mask 0x00000007) : 0x2
 */
#define CONFIG_SYS_GPS_PORT_CONFIG	0xA2552112

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP
#define CONFIG_AUTO_COMPLETE	1
#define CONFIG_CMDLINE_EDITING	1
#define CONFIG_SYS_PROMPT	"=> "
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "

#define CONFIG_AUTOBOOT_KEYED
#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n", bootdelay
#define CONFIG_AUTOBOOT_DELAY_STR	" "

#define CONFIG_LOOPW		1
#define CONFIG_MX_CYCLIC	1
#define CONFIG_ZERO_BOOTDELAY_CHECK

#define CONFIG_SYS_CBSIZE		1024
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS		32
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE

#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_SYS_MEMTEST_SCRATCH	0x00001000
#define CONFIG_SYS_MEMTEST_START	0x00010000
#define CONFIG_SYS_MEMTEST_END		0x019fffff

#define CONFIG_SYS_LOAD_ADDR		0x00100000

#define CONFIG_SYS_HZ			1000

/*
 * Various low-level settings
 */
#define CONFIG_SYS_SDRAM_CS1		1
#define CONFIG_SYS_XLB_PIPELINING	1

#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL		HID0_ICE

#if defined(CONFIG_SYS_LOWBOOT)
#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_BOOTCS_CFG		0x0002DD00
#endif

#define CONFIG_SYS_CS4_START		0x60000000
#define CONFIG_SYS_CS4_SIZE		0x1000
#define CONFIG_SYS_CS4_CFG		0x0008FC00

#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_CS0_CFG		0x0002DD00

#define CONFIG_SYS_CS_BURST		0x00000000
#define CONFIG_SYS_CS_DEADCYCLE	0x11111111

#if !defined(CONFIG_SYS_LOWBOOT)
#define CONFIG_SYS_RESET_ADDRESS	0xfff00100
#else
#define CONFIG_SYS_RESET_ADDRESS	0xff000100
#endif

/*
 * USB
 */
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SYS_OHCI_BE_CONTROLLER
#define CONFIG_USB_STORAGE

#define CONFIG_USB_CLOCK	0x00013333
#define CONFIG_USB_CONFIG	0x00002000

#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
#define CONFIG_SYS_USB_OHCI_REGS_BASE	MPC5XXX_USB
#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"mpc5200"
#define CONFIG_SYS_USB_OHCI_CPU_INIT

/*
 * IDE/ATA
 */
#define CONFIG_IDE_RESET
#define CONFIG_IDE_PREINIT

#define CONFIG_SYS_ATA_CS_ON_I2C2
#define CONFIG_SYS_IDE_MAXBUS		1
#define CONFIG_SYS_IDE_MAXDEVICE	1

#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)
#define CONFIG_SYS_ATA_STRIDE		4

#define CONFIG_ATAPI		1
#define CONFIG_LBA48		1

#endif /* __CONFIG_H */
Commit	Line	Data
5c4fa9b4 GB	1	/*
	2	* (C) Copyright 2003-2004
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* (C) Copyright 2005-2007
	6	* Modified for InterControl digsyMTC MPC5200 board by
	7	* Frank Bodammer, GCD Hard- & Software GmbH,
	8	* frank.bodammer@gcd-solutions.de
	9	*
	10	* (C) Copyright 2009 Semihalf
	11	* Optimized for digsyMTC by: Grzegorz Bernacki <gjb@semihalf.com>
	12	*
	13	* See file CREDITS for list of people who contributed to this
	14	* project.
	15	*
	16	* This program is free software\; you can redistribute it and/or
	17	* modify it under the terms of the GNU General Public License as
	18	* published by the Free Software Foundation\; either version 2 of
	19	* the License, or (at your option) any later version.
	20	*
	21	* This program is distributed in the hope that it will be useful,
	22	* but WITHOUT ANY WARRANTY\; without even the implied warranty of
	23	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	24	* GNU General Public License for more details.
	25	*
	26	* You should have received a copy of the GNU General Public License
	27	* along with this program\; if not, write to the Free Software
	28	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	29	* MA 02111-1307 USA
	30	*/
	31
	32	#ifndef __CONFIG_H
	33	#define __CONFIG_H
	34
	35	/*
	36	* High Level Configuration Options
	37	*/
	38
	39	#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
	40	#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
	41	#define CONFIG_DIGSY_MTC 1 /* ... on InterControl digsyMTC board */
	42
	43	#define CONFIG_SYS_MPC5XXX_CLKIN 33000000
	44
	45	#define BOOTFLAG_COLD 0x01
	46	#define BOOTFLAG_WARM 0x02
	47
	48	#define CONFIG_SYS_CACHELINE_SIZE 32
	49
	50	/*
	51	* Serial console configuration
	52	*/
	53	#define CONFIG_PSC_CONSOLE 4 /* console is on PSC4 */
	54	#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
	55	#define CONFIG_SYS_BAUDRATE_TABLE \
	56	{ 9600, 19200, 38400, 57600, 115200, 230400 }
	57
	58	/*
	59	* PCI Mapping:
	60	* 0x40000000 - 0x4fffffff - PCI Memory
	61	* 0x50000000 - 0x50ffffff - PCI IO Space
	62	*/
	63	#define CONFIG_PCI 1
	64	#define CONFIG_PCI_PNP 1
65	#define CONFIG_PCI_SCAN_SHOW 1
66
67	#define CONFIG_PCI_MEM_BUS 0x40000000
68	#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
69	#define CONFIG_PCI_MEM_SIZE 0x10000000
70
71	#define CONFIG_PCI_IO_BUS 0x50000000
72	#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
73	#define CONFIG_PCI_IO_SIZE 0x01000000
74
75	/*
76	* Partitions
77	*/
78	#define CONFIG_DOS_PARTITION
79	#define CONFIG_BZIP2
80
81	/*
82	* Command line configuration.
83	*/
84	#include <config_cmd_default.h>
85
86	#define CONFIG_CMD_DFL
87	#define CONFIG_CMD_CACHE
88	#define CONFIG_CMD_DATE
89	#define CONFIG_CMD_DHCP
90	#define CONFIG_CMD_DIAG
91	#define CONFIG_CMD_EEPROM
92	#define CONFIG_CMD_ELF
93	#define CONFIG_CMD_EXT2
94	#define CONFIG_CMD_FAT
95	#define CONFIG_CMD_I2C
96	#define CONFIG_CMD_IDE
97	#define CONFIG_CMD_IRQ
98	#define CONFIG_CMD_MII
99	#define CONFIG_CMD_PCI
100	#define CONFIG_CMD_PING
101	#define CONFIG_CMD_REGINFO
102	#define CONFIG_CMD_SAVES
f1f66edf	103	#define CONFIG_CMD_SPI
5c4fa9b4 GB	104	#define CONFIG_CMD_USB
	105
	106	#if (TEXT_BASE == 0xFF000000)
	107	#define CONFIG_SYS_LOWBOOT 1
	108	#endif
	109
	110	/*
	111	* Autobooting
	112	*/
	113	#define CONFIG_BOOTDELAY 1
	114
	115	#undef CONFIG_BOOTARGS
	116
ff27650b DZ	117	#define CONFIG_EXTRA_ENV_SETTINGS \
	118	"fw_image=digsyMPC.img\0" \
	119	"mtcb_start=mtc led diag orange; run mtcb_1\0" \
	120	"mtcb_clearled=for x in user1 user2 usbpwr usbbusy; " \
	121	"do mtc led $x; done\0" \
	122	"mtcb_1=if mtc key; then run mtcb_clearled mtcb_update; " \
	123	"else run mtcb_fw; fi\0" \
	124	"mtcb_fw=if bootm ff000000; then echo FIRMWARE OK!; " \
	125	"else echo BAD FIRMWARE CRC!; mtc led diag red; fi\0" \
	126	"mtcb_update=mtc led user1 orange;" \
	127	"while mtc key; do ; done; run mtcb_2;\0" \
	128	"mtcb_2=mtc led user1 green 2; usb reset; run mtcb_usb1;\0" \
	129	"mtcb_usb1=if fatload usb 0 400000 script.img; " \
	130	"then run mtcb_doscript; else run mtcb_usb2; fi\0" \
	131	"mtcb_usb2=if fatload usb 0 400000 $fw_image; " \
	132	"then run mtcb_dousb; else run mtcb_ide; fi\0" \
	133	"mtcb_doscript=run mtcb_usbleds; mtc led user2 orange 2; " \
	134	"run mtcb_wait_flickr mtcb_ds_1;\0" \
	135	"mtcb_ds_1=if imi 400000; then mtc led usbbusy; " \
	136	"source 400000; else run mtcb_error; fi\0" \
	137	"mtcb_dousb=run mtcb_usbleds mtcb_wait_flickr mtcb_du_1;\0" \
	138	"mtcb_du_1=if imi 400000; then run mtcb_du_2; " \
	139	"else run mtcb_error; fi\0" \
	140	"mtcb_du_2=run mtcb_clear mtcb_prog; mtc led usbbusy; " \
	141	"run mtcb_checkfw\0" \
	142	"mtcb_checkfw=if imi ff000000; then run mtcb_success; " \
	143	"else run mtcb_error; fi\0" \
	144	"mtcb_waitkey=mtc key; until test $? -eq 0; do mtc key; done\0" \
	145	"mtcb_wait_flickr=run mtcb_waitkey mtcb_uledflckr\0" \
	146	"mtcb_usbleds=mtc led usbpwr green; mtc led usbbusy orange 1;\0"\
	147	"mtcb_uledflckr=mtc led user1 orange 11\0" \
	148	"mtcb_error=mtc led user1 red\0" \
	149	"mtcb_clear=erase ff000000 ff0fffff\0" \
	150	"mtcb_prog=cp.b 400000 ff000000 ${filesize}\0" \
	151	"mtcb_success=mtc led user1 green\0" \
	152	"mtcb_ide=if fatload ide 0 400000 $fw_image;" \
	153	"then run mtcb_doide; else run mtcb_error; fi\0" \
	154	"mtcb_doide=mtc led user2 green 1;" \
	155	"run mtcb_wait_flickr mtcb_di_1;\0" \
	156	"mtcb_di_1=if imi 400000; then run mtcb_di_2;" \
	157	"else run mtcb_error; fi\0" \
	158	"mtcb_di_2=run mtcb_clear; run mtcb_prog mtcb_checkfw\0" \
	159	"ramdisk_num_sector=16\0" \
	160	"flash_base=ff000000\0" \
	161	"flashdisk_size=e00000\0" \
	162	"env_sector=fff60000\0" \
	163	"flashdisk_start=ff100000\0" \
	164	"load_cmd=tftp 400000 digsyMPC.img\0" \
	165	"clear_cmd=erase ff000000 ff0fffff\0" \
	166	"flash_cmd=cp.b 400000 ff000000 ${filesize}\0" \
	167	"update_cmd=run load_cmd; " \
	168	"iminfo 400000; " \
	169	"run clear_cmd flash_cmd; " \
	170	"iminfo ff000000\0" \
	171	"spi_driver=yes\0" \
	172	"spi_watchdog=no\0" \
	173	"ftps_start=yes\0" \
	174	"ftps_user1=admin\0" \
	175	"ftps_pass1=admin\0" \
	176	"ftps_base1=/\0" \
	177	"ftps_home1=/\0" \
	178	"plc_sio_srv=no\0" \
	179	"plc_sio_baud=57600\0" \
	180	"plc_sio_parity=no\0" \
181	"plc_sio_stop=1\0" \
182	"plc_sio_com=2\0" \
183	"plc_eth_srv=yes\0" \
184	"plc_eth_port=1200\0" \
185	"plc_root=/ide/\0" \
186	"diag_level=0\0" \
187	"webvisu=no\0" \
188	"plc_can1_routing=no\0" \
189	"plc_can1_baudrate=250\0" \
190	"plc_can2_routing=no\0" \
191	"plc_can2_baudrate=250\0" \
192	"plc_can3_routing=no\0" \
193	"plc_can3_baudrate=250\0" \
194	"plc_can4_routing=no\0" \
195	"plc_can4_baudrate=250\0" \
196	"netdev=eth0\0" \
197	"console=ttyPSC0\0" \
198	"kernel_addr_r=400000\0" \
199	"fdt_addr_r=600000\0" \
200	"nfsargs=setenv bootargs root=/dev/nfs rw " \
201	"nfsroot=${serverip}:${rootpath}\0" \
202	"addip=setenv bootargs ${bootargs} " \
203	"ip=${ipaddr}:${serverip}:${gatewayip}:" \
204	"${netmask}:${hostname}:${netdev}:off panic=1\0" \
5c4fa9b4	205	"addcons=setenv bootargs ${bootargs} console=${console},${baudrate}\0"\
ff27650b DZ	206	"rootpath=/opt/eldk/ppc_6xx\0" \
	207	"net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
	208	"tftp ${fdt_addr_r} ${fdt_file};" \
	209	"run nfsargs addip addcons;" \
	210	"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
	211	"load=tftp 200000 ${u-boot}\0" \
	212	"update=protect off FFF00000 +${filesize};" \
	213	"erase FFF00000 +${filesize};" \
	214	"cp.b 200000 FFF00000 ${filesize};" \
	215	"protect on FFF00000 +${filesize}\0" \
5c4fa9b4 GB	216	""
5c4fa9b4 GB	217
ff27650b DZ	218	#define CONFIG_BOOTCOMMAND "run mtcb_start"
ff27650b DZ	219
f1f66edf GB	220	/*
	221	* SPI configuration
	222	*/
	223	#define CONFIG_HARD_SPI 1
	224	#define CONFIG_MPC52XX_SPI 1
	225
5c4fa9b4 GB	226	/*
	227	* I2C configuration
	228	*/
	229	#define CONFIG_HARD_I2C 1
	230	#define CONFIG_SYS_I2C_MODULE 1
	231	#define CONFIG_SYS_I2C_SPEED 100000
	232	#define CONFIG_SYS_I2C_SLAVE 0x7F
	233
	234	/*
	235	* EEPROM configuration
	236	*/
	237	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
	238	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	239	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	240	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
	241
	242	/*
	243	* RTC configuration
	244	*/
	245	#define CONFIG_RTC_DS1337
	246	#define CONFIG_SYS_I2C_RTC_ADDR 0x68
c569ad6e	247	#define CONFIG_SYS_DS1339_TCR_VAL 0xAB /* diode + 4k resistor */
5c4fa9b4 GB	248
	249	/*
	250	* Flash configuration
	251	*/
	252	#define CONFIG_SYS_FLASH_CFI 1
	253	#define CONFIG_FLASH_CFI_DRIVER 1
	254
	255	#define CONFIG_SYS_FLASH_BASE 0xFF000000
	256	#define CONFIG_SYS_FLASH_SIZE 0x01000000
	257
	258	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	259	#define CONFIG_SYS_MAX_FLASH_SECT 256
	260	#define CONFIG_FLASH_16BIT
	261	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
	262	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
	263	#define CONFIG_SYS_FLASH_ERASE_TOUT 240000
	264	#define CONFIG_SYS_FLASH_WRITE_TOUT 500
	265
	266	#define CONFIG_OF_LIBFDT 1
	267	#define CONFIG_OF_BOARD_SETUP 1
	268
	269	#define OF_CPU "PowerPC,5200@0"
	270	#define OF_SOC "soc5200@f0000000"
	271	#define OF_TBCLK (bd->bi_busfreq / 4)
	272
	273	#define CONFIG_BOARD_EARLY_INIT_R
	274	#define CONFIG_MISC_INIT_R
	275
	276	/*
	277	* Environment settings
	278	*/
	279	#define CONFIG_ENV_IS_IN_FLASH 1
	280	#if defined(CONFIG_LOWBOOT)
	281	#define CONFIG_ENV_ADDR 0xFF060000
	282	#else /* CONFIG_LOWBOOT */
	283	#define CONFIG_ENV_ADDR 0xFFF60000
	284	#endif /* CONFIG_LOWBOOT */
	285	#define CONFIG_ENV_SIZE 0x10000
	286	#define CONFIG_ENV_SECT_SIZE 0x20000
	287	#define CONFIG_ENV_OVERWRITE 1
	288
	289	/*
	290	* Memory map
	291	*/
	292	#define CONFIG_SYS_MBAR 0xF0000000
	293	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	294	#if !defined(CONFIG_SYS_LOWBOOT)
	295	#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
	296	#else
	297	#define CONFIG_SYS_DEFAULT_MBAR 0xF0000000
	298	#endif
	299
	300	/*
	301	* Use SRAM until RAM will be available
	302	*/
	303	#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
	304	#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
	305
	306	#define CONFIG_SYS_GBL_DATA_SIZE 4096
	307	#define CONFIG_SYS_GBL_DATA_OFFSET \
	308	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
	309	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
	310
	311	#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
312	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
313	#define CONFIG_SYS_RAMBOOT 1
314	#endif
315
316	#define CONFIG_SYS_MONITOR_LEN (256 << 10)
317	#define CONFIG_SYS_MALLOC_LEN (4096 << 10)
318	#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
319
320	/*
321	* Ethernet configuration
322	*/
323	#define CONFIG_MPC5xxx_FEC 1
324	#define CONFIG_MPC5xxx_FEC_MII100
325	#define CONFIG_PHY_ADDR 0x00
326	#define CONFIG_PHY_RESET_DELAY 1000
327
328	#define CONFIG_NETCONSOLE /* include NetConsole support */
329
330	/*
331	* GPIO configuration
12602339 GB	332	* use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1)
	333	* Bit 0 (mask 0x80000000) : 0x1
	334	* SPI on Tmr2/3/4/5 pins
	335	* Bit 2:3 (mask 0x30000000) : 0x2
	336	* ATA cs0/1 on csb_4/5
	337	* Bit 6:7 (mask 0x03000000) : 0x2
	338	* Ethernet 100Mbit with MD
	339	* Bits 12:15 (mask 0x000f0000): 0x5
	340	* USB - Two UARTs
	341	* Bits 18:19 (mask 0x00003000) : 0x2
	342	* PSC3 - USB2 on PSC3
	343	* Bits 20:23 (mask 0x00000f00) : 0x1
	344	* PSC2 - CAN1&2 on PSC2 pins
	345	* Bits 25:27 (mask 0x00000070) : 0x1
	346	* PSC1 - AC97 functionality
	347	* Bits 29:31 (mask 0x00000007) : 0x2
5c4fa9b4 GB	348	*/
	349	#define CONFIG_SYS_GPS_PORT_CONFIG 0xA2552112
	350
	351	/*
	352	* Miscellaneous configurable options
	353	*/
	354	#define CONFIG_SYS_LONGHELP
	355	#define CONFIG_AUTO_COMPLETE 1
a781de12	356	#define CONFIG_CMDLINE_EDITING 1
5c4fa9b4 GB	357	#define CONFIG_SYS_PROMPT "=> "
	358	#define CONFIG_SYS_HUSH_PARSER
	359	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
	360
	361	#define CONFIG_AUTOBOOT_KEYED
	362	#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n", bootdelay
	363	#define CONFIG_AUTOBOOT_DELAY_STR " "
	364
	365	#define CONFIG_LOOPW 1
	366	#define CONFIG_MX_CYCLIC 1
	367	#define CONFIG_ZERO_BOOTDELAY_CHECK
	368
	369	#define CONFIG_SYS_CBSIZE 1024
	370	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
	371	#define CONFIG_SYS_MAXARGS 32
	372	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	373
	374	#define CONFIG_SYS_ALT_MEMTEST
	375	#define CONFIG_SYS_MEMTEST_SCRATCH 0x00001000
	376	#define CONFIG_SYS_MEMTEST_START 0x00010000
	377	#define CONFIG_SYS_MEMTEST_END 0x019fffff
	378
	379	#define CONFIG_SYS_LOAD_ADDR 0x00100000
	380
	381	#define CONFIG_SYS_HZ 1000
	382
	383	/*
	384	* Various low-level settings
	385	*/
	386	#define CONFIG_SYS_SDRAM_CS1 1
	387	#define CONFIG_SYS_XLB_PIPELINING 1
	388
	389	#define CONFIG_SYS_HID0_INIT HID0_ICE \| HID0_ICFI
	390	#define CONFIG_SYS_HID0_FINAL HID0_ICE
	391
	392	#if defined(CONFIG_SYS_LOWBOOT)
	393	#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
	394	#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
	395	#define CONFIG_SYS_BOOTCS_CFG 0x0002DD00
	396	#endif
	397
	398	#define CONFIG_SYS_CS4_START 0x60000000
	399	#define CONFIG_SYS_CS4_SIZE 0x1000
	400	#define CONFIG_SYS_CS4_CFG 0x0008FC00
	401
	402	#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
	403	#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
	404	#define CONFIG_SYS_CS0_CFG 0x0002DD00
	405
	406	#define CONFIG_SYS_CS_BURST 0x00000000
	407	#define CONFIG_SYS_CS_DEADCYCLE 0x11111111
	408
	409	#if !defined(CONFIG_SYS_LOWBOOT)
	410	#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
	411	#else
	412	#define CONFIG_SYS_RESET_ADDRESS 0xff000100
	413	#endif
	414
	415	/*
	416	* USB
	417	*/
	418	#define CONFIG_USB_OHCI_NEW
	419	#define CONFIG_SYS_OHCI_BE_CONTROLLER
	420	#define CONFIG_USB_STORAGE
421
422	#define CONFIG_USB_CLOCK 0x00013333
423	#define CONFIG_USB_CONFIG 0x00002000
424
425	#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
426	#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
427	#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
428	#define CONFIG_SYS_USB_OHCI_CPU_INIT
429
430	/*
431	* IDE/ATA
432	*/
433	#define CONFIG_IDE_RESET
434	#define CONFIG_IDE_PREINIT
435
436	#define CONFIG_SYS_ATA_CS_ON_I2C2
437	#define CONFIG_SYS_IDE_MAXBUS 1
438	#define CONFIG_SYS_IDE_MAXDEVICE 1
439
440	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
441	#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
442	#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
443	#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
444	#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
445	#define CONFIG_SYS_ATA_STRIDE 4
446
447	#define CONFIG_ATAPI 1
448	#define CONFIG_LBA48 1
449
450	#endif /* __CONFIG_H */