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3ef5ebeb LV |
1 | /* |
2 | * (C) Copyright 2013 | |
3 | * Texas Instruments Incorporated. | |
4 | * Lokesh Vutla <lokeshvutla@ti.com> | |
5 | * | |
6 | * Configuration settings for the TI DRA7XX board. | |
7 | * See omap5_common.h for omap5 common settings. | |
8 | * | |
3765b3e7 | 9 | * SPDX-License-Identifier: GPL-2.0+ |
3ef5ebeb LV |
10 | */ |
11 | ||
12 | #ifndef __CONFIG_DRA7XX_EVM_H | |
13 | #define __CONFIG_DRA7XX_EVM_H | |
14 | ||
a8017574 | 15 | #define CONFIG_DRA7XX |
3ef5ebeb | 16 | |
d3d33daf LV |
17 | /* MMC ENV related defines */ |
18 | #define CONFIG_ENV_IS_IN_MMC | |
19 | #define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */ | |
20 | #define CONFIG_ENV_OFFSET 0xE0000 | |
21 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) | |
22 | #define CONFIG_SYS_REDUNDAND_ENVIRONMENT | |
23 | #define CONFIG_CMD_SAVEENV | |
3ef5ebeb | 24 | |
a13cbf5f | 25 | #if (CONFIG_CONS_INDEX == 1) |
a8017574 | 26 | #define CONSOLEDEV "ttyO0" |
a13cbf5f MS |
27 | #elif (CONFIG_CONS_INDEX == 3) |
28 | #define CONSOLEDEV "ttyO2" | |
29 | #endif | |
30 | #define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ | |
31 | #define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ | |
32 | #define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ | |
378bd1fb | 33 | #define CONFIG_BAUDRATE 115200 |
97405d84 LV |
34 | |
35 | #define CONFIG_SYS_OMAP_ABE_SYSCK | |
45dbbf29 | 36 | |
a8017574 | 37 | #include <configs/omap5_common.h> |
45dbbf29 | 38 | |
c9be62ca | 39 | /* CPSW Ethernet */ |
457bb505 | 40 | #define CONFIG_CMD_NET /* 'bootp' and 'tftp' */ |
c9be62ca | 41 | #define CONFIG_CMD_DHCP |
457bb505 | 42 | #define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */ |
c9be62ca M |
43 | #define CONFIG_BOOTP_DNS2 |
44 | #define CONFIG_BOOTP_SEND_HOSTNAME | |
45 | #define CONFIG_BOOTP_GATEWAY | |
46 | #define CONFIG_BOOTP_SUBNETMASK | |
457bb505 TR |
47 | #define CONFIG_NET_RETRY_COUNT 10 |
48 | #define CONFIG_CMD_PING | |
49 | #define CONFIG_CMD_MII | |
50 | #define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */ | |
51 | #define CONFIG_MII /* Required in net/eth.c */ | |
52 | #define CONFIG_PHY_GIGE /* per-board part of CPSW */ | |
c9be62ca M |
53 | #define CONFIG_PHYLIB |
54 | #define CONFIG_PHY_ADDR 2 | |
55 | ||
247cdf04 MP |
56 | /* SPI */ |
57 | #undef CONFIG_OMAP3_SPI | |
58 | #define CONFIG_TI_QSPI | |
59 | #define CONFIG_SPI_FLASH | |
60 | #define CONFIG_SPI_FLASH_SPANSION | |
61 | #define CONFIG_CMD_SF | |
62 | #define CONFIG_CMD_SPI | |
2c57b03b | 63 | #define CONFIG_SPI_FLASH_BAR |
247cdf04 MP |
64 | #define CONFIG_TI_SPI_MMAP |
65 | #define CONFIG_SF_DEFAULT_SPEED 48000000 | |
66 | #define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3 | |
67 | ||
68 | /* SPI SPL */ | |
69 | #define CONFIG_SPL_SPI_SUPPORT | |
70 | #define CONFIG_SPL_SPI_LOAD | |
71 | #define CONFIG_SPL_SPI_FLASH_SUPPORT | |
72 | #define CONFIG_SPL_SPI_BUS 0 | |
73 | #define CONFIG_SPL_SPI_CS 0 | |
74 | #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 | |
75 | ||
834e91af DM |
76 | /* USB xHCI HOST */ |
77 | #define CONFIG_CMD_USB | |
78 | #define CONFIG_USB_HOST | |
79 | #define CONFIG_USB_XHCI | |
80 | #define CONFIG_USB_XHCI_OMAP | |
81 | #define CONFIG_USB_STORAGE | |
82 | #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 | |
83 | ||
84 | #define CONFIG_OMAP_USB_PHY | |
85 | #define CONFIG_OMAP_USB2PHY2_HOST | |
86 | ||
21914ee6 RQ |
87 | /* SATA */ |
88 | #define CONFIG_BOARD_LATE_INIT | |
89 | #define CONFIG_CMD_SCSI | |
90 | #define CONFIG_LIBATA | |
91 | #define CONFIG_SCSI_AHCI | |
92 | #define CONFIG_SCSI_AHCI_PLAT | |
93 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 | |
94 | #define CONFIG_SYS_SCSI_MAX_LUN 1 | |
95 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ | |
96 | CONFIG_SYS_SCSI_MAX_LUN) | |
97 | ||
3ef5ebeb | 98 | #endif /* __CONFIG_DRA7XX_EVM_H */ |