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76dd9b6a RS |
1 | /* |
2 | * Copyright (C) 2013 Samsung Electronics | |
3 | * | |
4 | * Configuration settings for the SAMSUNG EXYNOS5 board. | |
5 | * | |
6 | * SPDX-License-Identifier: GPL-2.0+ | |
7 | */ | |
8 | ||
4c7bb1d2 SG |
9 | #ifndef __CONFIG_EXYNOS5_COMMON_H |
10 | #define __CONFIG_EXYNOS5_COMMON_H | |
76dd9b6a | 11 | |
5ea01ab1 SG |
12 | #define CONFIG_EXYNOS5 /* Exynos5 Family */ |
13 | ||
14 | #include "exynos-common.h" | |
15 | ||
16 | #define CONFIG_SYS_CACHELINE_SIZE 64 | |
76dd9b6a RS |
17 | #define CONFIG_EXYNOS_SPL |
18 | ||
f44ef7d6 | 19 | #ifdef FTRACE |
76dd9b6a RS |
20 | #define CONFIG_TRACE |
21 | #define CONFIG_CMD_TRACE | |
22 | #define CONFIG_TRACE_BUFFER_SIZE (16 << 20) | |
23 | #define CONFIG_TRACE_EARLY_SIZE (8 << 20) | |
24 | #define CONFIG_TRACE_EARLY | |
25 | #define CONFIG_TRACE_EARLY_ADDR 0x50000000 | |
f44ef7d6 | 26 | #endif |
76dd9b6a RS |
27 | |
28 | /* Enable ACE acceleration for SHA1 and SHA256 */ | |
29 | #define CONFIG_EXYNOS_ACE_SHA | |
30 | #define CONFIG_SHA_HW_ACCEL | |
31 | ||
76dd9b6a RS |
32 | /* Power Down Modes */ |
33 | #define S5P_CHECK_SLEEP 0x00000BAD | |
34 | #define S5P_CHECK_DIDLE 0xBAD00000 | |
35 | #define S5P_CHECK_LPA 0xABAD0000 | |
36 | ||
37 | /* Offset for inform registers */ | |
38 | #define INFORM0_OFFSET 0x800 | |
39 | #define INFORM1_OFFSET 0x804 | |
40 | #define INFORM2_OFFSET 0x808 | |
41 | #define INFORM3_OFFSET 0x80c | |
42 | ||
76dd9b6a RS |
43 | /* select serial console configuration */ |
44 | #define CONFIG_BAUDRATE 115200 | |
45 | #define EXYNOS5_DEFAULT_UART_OFFSET 0x010000 | |
46 | #define CONFIG_SILENT_CONSOLE | |
5ea01ab1 SG |
47 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV |
48 | #define CONFIG_CONSOLE_MUX | |
76dd9b6a | 49 | |
76dd9b6a RS |
50 | #define CONFIG_CMD_HASH |
51 | ||
76dd9b6a RS |
52 | /* Thermal Management Unit */ |
53 | #define CONFIG_EXYNOS_TMU | |
54 | #define CONFIG_CMD_DTT | |
55 | #define CONFIG_TMU_CMD_DTT | |
56 | ||
57 | /* TPM */ | |
58 | #define CONFIG_TPM | |
59 | #define CONFIG_CMD_TPM | |
60 | #define CONFIG_TPM_TIS_I2C | |
61 | #define CONFIG_TPM_TIS_I2C_BUS_NUMBER 3 | |
62 | #define CONFIG_TPM_TIS_I2C_SLAVE_ADDR 0x20 | |
63 | ||
64 | /* MMC SPL */ | |
76dd9b6a | 65 | #define COPY_BL2_FNPTR_ADDR 0x02020030 |
5ea01ab1 | 66 | #define CONFIG_SUPPORT_EMMC_BOOT |
76dd9b6a RS |
67 | |
68 | #define CONFIG_SPL_LIBCOMMON_SUPPORT | |
69 | #define CONFIG_SPL_GPIO_SUPPORT | |
d4061aa0 SG |
70 | #define CONFIG_SPL_SERIAL_SUPPORT |
71 | #define CONFIG_SPL_LIBGENERIC_SUPPORT | |
76dd9b6a RS |
72 | |
73 | /* specific .lds file */ | |
74 | #define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds" | |
76dd9b6a | 75 | |
76dd9b6a | 76 | /* Boot Argument Buffer Size */ |
76dd9b6a RS |
77 | /* memtest works on */ |
78 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE | |
79 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000) | |
80 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) | |
81 | ||
82 | #define CONFIG_RD_LVL | |
83 | ||
76dd9b6a RS |
84 | #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE |
85 | #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE | |
86 | #define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) | |
87 | #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE | |
88 | #define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) | |
89 | #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE | |
90 | #define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) | |
91 | #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE | |
92 | #define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) | |
93 | #define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE | |
94 | #define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) | |
95 | #define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE | |
96 | #define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) | |
97 | #define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE | |
98 | #define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) | |
99 | #define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE | |
100 | ||
101 | #define CONFIG_SYS_MONITOR_BASE 0x00000000 | |
102 | ||
76dd9b6a RS |
103 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
104 | ||
105 | #define CONFIG_SECURE_BL1_ONLY | |
106 | ||
107 | /* Secure FW size configuration */ | |
108 | #ifdef CONFIG_SECURE_BL1_ONLY | |
109 | #define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */ | |
110 | #else | |
111 | #define CONFIG_SEC_FW_SIZE 0 | |
112 | #endif | |
113 | ||
114 | /* Configuration of BL1, BL2, ENV Blocks on mmc */ | |
115 | #define CONFIG_RES_BLOCK_SIZE (512) | |
116 | #define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ | |
117 | #define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */ | |
118 | #define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ | |
119 | ||
120 | #define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE) | |
121 | #define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE) | |
fa253157 | 122 | |
76dd9b6a RS |
123 | /* U-boot copy size from boot Media to DRAM.*/ |
124 | #define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512) | |
125 | #define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512) | |
126 | ||
76dd9b6a RS |
127 | #define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058 |
128 | #define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE) | |
129 | ||
76dd9b6a | 130 | /* I2C */ |
76dd9b6a | 131 | #define CONFIG_CMD_I2C |
76dd9b6a | 132 | #define CONFIG_SYS_I2C_S3C24X0 |
189d8016 | 133 | #define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */ |
76dd9b6a RS |
134 | #define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0 |
135 | #define CONFIG_I2C_EDID | |
136 | ||
137 | /* SPI */ | |
76dd9b6a RS |
138 | #ifdef CONFIG_SPI_FLASH |
139 | #define CONFIG_EXYNOS_SPI | |
140 | #define CONFIG_CMD_SF | |
141 | #define CONFIG_CMD_SPI | |
142 | #define CONFIG_SPI_FLASH_WINBOND | |
143 | #define CONFIG_SPI_FLASH_GIGADEVICE | |
144 | #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 | |
145 | #define CONFIG_SF_DEFAULT_SPEED 50000000 | |
76dd9b6a RS |
146 | #endif |
147 | ||
148 | #ifdef CONFIG_ENV_IS_IN_SPI_FLASH | |
149 | #define CONFIG_ENV_SPI_MODE SPI_MODE_0 | |
150 | #define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE | |
151 | #define CONFIG_ENV_SPI_BUS 1 | |
152 | #define CONFIG_ENV_SPI_MAX_HZ 50000000 | |
153 | #endif | |
154 | ||
76dd9b6a RS |
155 | /* Ethernet Controllor Driver */ |
156 | #ifdef CONFIG_CMD_NET | |
157 | #define CONFIG_SMC911X | |
158 | #define CONFIG_SMC911X_BASE 0x5000000 | |
159 | #define CONFIG_SMC911X_16_BIT | |
160 | #define CONFIG_ENV_SROM_BANK 1 | |
161 | #endif /*CONFIG_CMD_NET*/ | |
162 | ||
76dd9b6a RS |
163 | /* SHA hashing */ |
164 | #define CONFIG_CMD_HASH | |
165 | #define CONFIG_HASH_VERIFY | |
166 | #define CONFIG_SHA1 | |
167 | #define CONFIG_SHA256 | |
168 | ||
169 | /* Enable Time Command */ | |
170 | #define CONFIG_CMD_TIME | |
171 | ||
9b97b727 AS |
172 | #define CONFIG_CMD_GPIO |
173 | ||
66223787 SS |
174 | /* USB */ |
175 | #define CONFIG_CMD_USB | |
176 | #define CONFIG_USB_STORAGE | |
552d60cc | 177 | #define CONFIG_USB_XHCI_DWC3 |
66223787 SS |
178 | #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 |
179 | #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 | |
180 | ||
181 | #define CONFIG_USB_HOST_ETHER | |
182 | #define CONFIG_USB_ETHER_ASIX | |
183 | #define CONFIG_USB_ETHER_SMSC95XX | |
184 | ||
582693b2 AS |
185 | /* USB boot mode */ |
186 | #define CONFIG_USB_BOOTING | |
187 | #define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070 | |
188 | #define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002 | |
189 | #define EXYNOS_IRAM_SECONDARY_BASE 0x02020018 | |
190 | ||
5ea01ab1 SG |
191 | /* Enable FIT support and comparison */ |
192 | #define CONFIG_FIT | |
193 | #define CONFIG_FIT_BEST_MATCH | |
194 | ||
e6825e03 IC |
195 | #define BOOT_TARGET_DEVICES(func) \ |
196 | func(MMC, mmc, 1) \ | |
197 | func(MMC, mmc, 0) \ | |
198 | func(PXE, pxe, na) \ | |
199 | func(DHCP, dhcp, na) | |
200 | ||
201 | #include <config_distro_bootcmd.h> | |
202 | ||
203 | #ifndef MEM_LAYOUT_ENV_SETTINGS | |
204 | /* 2GB RAM, bootm size of 256M, load scripts after that */ | |
205 | #define MEM_LAYOUT_ENV_SETTINGS \ | |
206 | "bootm_size=0x10000000\0" \ | |
207 | "kernel_addr_r=0x42000000\0" \ | |
208 | "fdt_addr_r=0x43000000\0" \ | |
209 | "ramdisk_addr_r=0x43300000\0" \ | |
210 | "scriptaddr=0x50000000\0" \ | |
211 | "pxefile_addr_r=0x51000000\0" | |
212 | #endif | |
213 | ||
214 | #ifndef EXYNOS_DEVICE_SETTINGS | |
215 | #define EXYNOS_DEVICE_SETTINGS \ | |
216 | "stdin=serial\0" \ | |
217 | "stdout=serial\0" \ | |
218 | "stderr=serial\0" | |
219 | #endif | |
220 | ||
221 | #ifndef EXYNOS_FDTFILE_SETTING | |
222 | #define EXYNOS_FDTFILE_SETTING | |
223 | #endif | |
224 | ||
225 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
226 | EXYNOS_DEVICE_SETTINGS \ | |
227 | EXYNOS_FDTFILE_SETTING \ | |
228 | MEM_LAYOUT_ENV_SETTINGS \ | |
229 | BOOTENV | |
230 | ||
4c7bb1d2 | 231 | #endif /* __CONFIG_EXYNOS5_COMMON_H */ |