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76dd9b6a RS |
1 | /* |
2 | * Copyright (C) 2013 Samsung Electronics | |
3 | * | |
4 | * Configuration settings for the SAMSUNG EXYNOS5 board. | |
5 | * | |
6 | * SPDX-License-Identifier: GPL-2.0+ | |
7 | */ | |
8 | ||
4c7bb1d2 SG |
9 | #ifndef __CONFIG_EXYNOS5_COMMON_H |
10 | #define __CONFIG_EXYNOS5_COMMON_H | |
76dd9b6a | 11 | |
5ea01ab1 SG |
12 | #define CONFIG_EXYNOS5 /* Exynos5 Family */ |
13 | ||
14 | #include "exynos-common.h" | |
15 | ||
76dd9b6a RS |
16 | #define CONFIG_EXYNOS_SPL |
17 | ||
f44ef7d6 | 18 | #ifdef FTRACE |
76dd9b6a | 19 | #define CONFIG_TRACE |
76dd9b6a RS |
20 | #define CONFIG_TRACE_BUFFER_SIZE (16 << 20) |
21 | #define CONFIG_TRACE_EARLY_SIZE (8 << 20) | |
22 | #define CONFIG_TRACE_EARLY | |
23 | #define CONFIG_TRACE_EARLY_ADDR 0x50000000 | |
f44ef7d6 | 24 | #endif |
76dd9b6a RS |
25 | |
26 | /* Enable ACE acceleration for SHA1 and SHA256 */ | |
27 | #define CONFIG_EXYNOS_ACE_SHA | |
76dd9b6a | 28 | |
76dd9b6a RS |
29 | /* Power Down Modes */ |
30 | #define S5P_CHECK_SLEEP 0x00000BAD | |
31 | #define S5P_CHECK_DIDLE 0xBAD00000 | |
32 | #define S5P_CHECK_LPA 0xABAD0000 | |
33 | ||
34 | /* Offset for inform registers */ | |
35 | #define INFORM0_OFFSET 0x800 | |
36 | #define INFORM1_OFFSET 0x804 | |
37 | #define INFORM2_OFFSET 0x808 | |
38 | #define INFORM3_OFFSET 0x80c | |
39 | ||
76dd9b6a | 40 | /* select serial console configuration */ |
76dd9b6a | 41 | #define EXYNOS5_DEFAULT_UART_OFFSET 0x010000 |
76dd9b6a | 42 | |
76dd9b6a RS |
43 | /* Thermal Management Unit */ |
44 | #define CONFIG_EXYNOS_TMU | |
76dd9b6a | 45 | |
76dd9b6a | 46 | /* MMC SPL */ |
76dd9b6a | 47 | #define COPY_BL2_FNPTR_ADDR 0x02020030 |
5ea01ab1 | 48 | #define CONFIG_SUPPORT_EMMC_BOOT |
76dd9b6a | 49 | |
76dd9b6a | 50 | /* specific .lds file */ |
76dd9b6a | 51 | |
76dd9b6a | 52 | /* Boot Argument Buffer Size */ |
76dd9b6a RS |
53 | /* memtest works on */ |
54 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE | |
55 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000) | |
56 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) | |
57 | ||
58 | #define CONFIG_RD_LVL | |
59 | ||
76dd9b6a RS |
60 | #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE |
61 | #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE | |
62 | #define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) | |
63 | #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE | |
64 | #define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) | |
65 | #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE | |
66 | #define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) | |
67 | #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE | |
68 | #define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) | |
69 | #define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE | |
70 | #define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) | |
71 | #define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE | |
72 | #define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) | |
73 | #define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE | |
74 | #define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) | |
75 | #define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE | |
76 | ||
77 | #define CONFIG_SYS_MONITOR_BASE 0x00000000 | |
78 | ||
76dd9b6a RS |
79 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
80 | ||
81 | #define CONFIG_SECURE_BL1_ONLY | |
82 | ||
83 | /* Secure FW size configuration */ | |
84 | #ifdef CONFIG_SECURE_BL1_ONLY | |
85 | #define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */ | |
86 | #else | |
87 | #define CONFIG_SEC_FW_SIZE 0 | |
88 | #endif | |
89 | ||
90 | /* Configuration of BL1, BL2, ENV Blocks on mmc */ | |
91 | #define CONFIG_RES_BLOCK_SIZE (512) | |
92 | #define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ | |
93 | #define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */ | |
94 | #define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ | |
95 | ||
96 | #define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE) | |
97 | #define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE) | |
fa253157 | 98 | |
a187559e | 99 | /* U-Boot copy size from boot Media to DRAM.*/ |
76dd9b6a RS |
100 | #define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512) |
101 | #define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512) | |
102 | ||
76dd9b6a RS |
103 | #define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058 |
104 | #define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE) | |
105 | ||
76dd9b6a | 106 | /* I2C */ |
76dd9b6a | 107 | #define CONFIG_SYS_I2C_S3C24X0 |
189d8016 | 108 | #define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */ |
76dd9b6a | 109 | #define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0 |
76dd9b6a RS |
110 | |
111 | /* SPI */ | |
76dd9b6a | 112 | #ifdef CONFIG_SPI_FLASH |
76dd9b6a RS |
113 | #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 |
114 | #define CONFIG_SF_DEFAULT_SPEED 50000000 | |
76dd9b6a RS |
115 | #endif |
116 | ||
117 | #ifdef CONFIG_ENV_IS_IN_SPI_FLASH | |
118 | #define CONFIG_ENV_SPI_MODE SPI_MODE_0 | |
119 | #define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE | |
120 | #define CONFIG_ENV_SPI_BUS 1 | |
121 | #define CONFIG_ENV_SPI_MAX_HZ 50000000 | |
122 | #endif | |
123 | ||
76dd9b6a RS |
124 | /* Ethernet Controllor Driver */ |
125 | #ifdef CONFIG_CMD_NET | |
76dd9b6a RS |
126 | #define CONFIG_ENV_SROM_BANK 1 |
127 | #endif /*CONFIG_CMD_NET*/ | |
128 | ||
76dd9b6a | 129 | /* Enable Time Command */ |
76dd9b6a | 130 | |
66223787 | 131 | /* USB */ |
66223787 | 132 | |
582693b2 AS |
133 | /* USB boot mode */ |
134 | #define CONFIG_USB_BOOTING | |
135 | #define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070 | |
136 | #define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002 | |
137 | #define EXYNOS_IRAM_SECONDARY_BASE 0x02020018 | |
138 | ||
e6825e03 IC |
139 | #define BOOT_TARGET_DEVICES(func) \ |
140 | func(MMC, mmc, 1) \ | |
141 | func(MMC, mmc, 0) \ | |
142 | func(PXE, pxe, na) \ | |
143 | func(DHCP, dhcp, na) | |
144 | ||
145 | #include <config_distro_bootcmd.h> | |
146 | ||
147 | #ifndef MEM_LAYOUT_ENV_SETTINGS | |
148 | /* 2GB RAM, bootm size of 256M, load scripts after that */ | |
149 | #define MEM_LAYOUT_ENV_SETTINGS \ | |
150 | "bootm_size=0x10000000\0" \ | |
151 | "kernel_addr_r=0x42000000\0" \ | |
152 | "fdt_addr_r=0x43000000\0" \ | |
153 | "ramdisk_addr_r=0x43300000\0" \ | |
154 | "scriptaddr=0x50000000\0" \ | |
155 | "pxefile_addr_r=0x51000000\0" | |
156 | #endif | |
157 | ||
158 | #ifndef EXYNOS_DEVICE_SETTINGS | |
159 | #define EXYNOS_DEVICE_SETTINGS \ | |
160 | "stdin=serial\0" \ | |
161 | "stdout=serial\0" \ | |
162 | "stderr=serial\0" | |
163 | #endif | |
164 | ||
165 | #ifndef EXYNOS_FDTFILE_SETTING | |
166 | #define EXYNOS_FDTFILE_SETTING | |
167 | #endif | |
168 | ||
169 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
170 | EXYNOS_DEVICE_SETTINGS \ | |
171 | EXYNOS_FDTFILE_SETTING \ | |
172 | MEM_LAYOUT_ENV_SETTINGS \ | |
173 | BOOTENV | |
174 | ||
4c7bb1d2 | 175 | #endif /* __CONFIG_EXYNOS5_COMMON_H */ |