]>
Commit | Line | Data |
---|---|---|
ad7a1785 AB |
1 | /* |
2 | * Copyright (C) 2011 | |
3 | * Corscience GmbH & Co.KG, Andreas Bießmann <biessmann@corscience.de> | |
4 | * | |
5 | * Configuration settings for the grasshopper (ICnova AP7000) board | |
6 | * | |
1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
ad7a1785 AB |
8 | */ |
9 | #ifndef __GRASSHOPPER_CONFIG_H | |
10 | #define __GRASSHOPPER_CONFIG_H | |
11 | ||
12 | #include <asm/arch/hardware.h> | |
13 | ||
14 | #define CONFIG_AVR32 | |
15 | #define CONFIG_AT32AP | |
16 | #define CONFIG_AT32AP7000 | |
17 | ||
18 | /* | |
19 | * Timer clock frequency. We're using the CPU-internal COUNT register | |
20 | * for this, so this is equivalent to the CPU core clock frequency | |
21 | */ | |
22 | #define CONFIG_SYS_HZ 1000 | |
23 | ||
24 | /* | |
25 | * Set up the PLL to run at 140 MHz, the CPU to run at the PLL | |
26 | * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the | |
27 | * PLL frequency. | |
28 | * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz | |
29 | */ | |
30 | #define CONFIG_PLL | |
31 | #define CONFIG_SYS_POWER_MANAGER | |
32 | #define CONFIG_SYS_OSC0_HZ 20000000 | |
33 | #define CONFIG_SYS_PLL0_DIV 1 | |
34 | #define CONFIG_SYS_PLL0_MUL 7 | |
35 | #define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16 | |
36 | /* | |
37 | * Set the CPU running at: | |
38 | * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz | |
39 | */ | |
40 | #define CONFIG_SYS_CLKDIV_CPU 0 | |
41 | /* | |
42 | * Set the HSB running at: | |
43 | * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz | |
44 | */ | |
45 | #define CONFIG_SYS_CLKDIV_HSB 1 | |
46 | /* | |
47 | * Set the PBA running at: | |
48 | * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz | |
49 | */ | |
50 | #define CONFIG_SYS_CLKDIV_PBA 2 | |
51 | /* | |
52 | * Set the PBB running at: | |
53 | * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz | |
54 | */ | |
55 | #define CONFIG_SYS_CLKDIV_PBB 1 | |
56 | ||
57 | /* Reserve VM regions for SDRAM and NOR flash */ | |
58 | #define CONFIG_SYS_NR_VM_REGIONS 2 | |
59 | ||
60 | /* | |
61 | * The PLLOPT register controls the PLL like this: | |
62 | * icp = PLLOPT<2> | |
63 | * ivco = PLLOPT<1:0> | |
64 | * | |
65 | * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). | |
66 | */ | |
67 | #define CONFIG_SYS_PLL0_OPT 0x04 | |
68 | ||
69 | #define CONFIG_USART_BASE ATMEL_BASE_USART1 | |
70 | #define CONFIG_USART_ID 1 | |
71 | ||
72 | /* User serviceable stuff */ | |
73 | #define CONFIG_CMDLINE_TAG | |
74 | #define CONFIG_SETUP_MEMORY_TAGS | |
75 | #define CONFIG_INITRD_TAG | |
76 | ||
77 | #define CONFIG_STACKSIZE (2048) | |
78 | ||
79 | #define CONFIG_BAUDRATE 115200 | |
80 | ||
81 | /* | |
82 | * Only interrupt autoboot if <space> is pressed. Otherwise, garbage | |
83 | * data on the serial line may interrupt the boot sequence. | |
84 | */ | |
85 | #define CONFIG_BOOTDELAY 1 | |
86 | #define CONFIG_AUTOBOOT | |
87 | #define CONFIG_AUTOBOOT_KEYED | |
88 | #define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d" \ | |
89 | " seconds\n", bootdelay | |
90 | #define CONFIG_AUTOBOOT_DELAY_STR "d" | |
91 | #define CONFIG_AUTOBOOT_STOP_STR " " | |
92 | ||
93 | /* | |
94 | * After booting the board for the first time, new ethernet addresses | |
95 | * should be generated and assigned to the environment variables | |
96 | * "ethaddr". This is normally done during production. | |
97 | */ | |
98 | #define CONFIG_OVERWRITE_ETHADDR_ONCE | |
ad7a1785 AB |
99 | |
100 | /* | |
101 | * BOOTP options | |
102 | */ | |
103 | #define CONFIG_BOOTP_SUBNETMASK | |
104 | #define CONFIG_BOOTP_GATEWAY | |
105 | ||
106 | /* | |
107 | * Command line configuration. | |
108 | */ | |
109 | #include <config_cmd_default.h> | |
110 | ||
111 | /* remove unneeded commands */ | |
112 | #undef CONFIG_CMD_FPGA | |
113 | #undef CONFIG_CMD_SETGETDCR | |
114 | ||
115 | /* add useful commands */ | |
116 | #define CONFIG_CMD_ASKENV | |
117 | #define CONFIG_CMD_DHCP | |
118 | #define CONFIG_CMD_JFFS2 | |
119 | #define CONFIG_CMD_PING | |
120 | #define CONFIG_CMD_REGINFO | |
121 | ||
122 | #define CONFIG_SYS_HUSH_PARSER | |
123 | #define CONFIG_AUTO_COMPLETE | |
ad7a1785 AB |
124 | #define CONFIG_CMDLINE_EDITING |
125 | ||
126 | #define CONFIG_ATMEL_USART | |
127 | #define CONFIG_MACB | |
128 | #define CONFIG_PORTMUX_PIO | |
129 | #define CONFIG_SYS_NR_PIOS 5 | |
130 | #define CONFIG_SYS_HSDRAMC | |
131 | ||
132 | #define CONFIG_SYS_DCACHE_LINESZ 32 | |
133 | #define CONFIG_SYS_ICACHE_LINESZ 32 | |
134 | ||
135 | #define CONFIG_NR_DRAM_BANKS 1 | |
136 | ||
137 | #define CONFIG_SYS_FLASH_CFI | |
138 | #define CONFIG_FLASH_CFI_DRIVER | |
139 | ||
140 | #define CONFIG_SYS_FLASH_BASE 0x00000000 | |
141 | #define CONFIG_SYS_FLASH_SIZE 0x800000 | |
142 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
143 | #define CONFIG_SYS_MAX_FLASH_SECT 135 | |
144 | ||
145 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
146 | #define CONFIG_SYS_TEXT_BASE 0x00000000 | |
147 | ||
148 | #define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE | |
149 | #define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE | |
150 | #define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE | |
151 | ||
152 | #define CONFIG_ENV_IS_IN_FLASH | |
153 | /* place u-boot env in flash sector after u-boot */ | |
154 | #define CONFIG_ENV_SIZE 0x10000 | |
155 | #define CONFIG_ENV_ADDR 0x20000 | |
156 | ||
157 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + \ | |
158 | CONFIG_SYS_INTRAM_SIZE) | |
159 | ||
160 | #define CONFIG_SYS_MALLOC_LEN (256*1024) | |
161 | #define CONFIG_SYS_DMA_ALLOC_LEN (16384) | |
162 | ||
163 | /* Allow 4MB for the kernel run-time image */ | |
164 | #define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) | |
165 | #define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024) | |
166 | ||
167 | /* Other configuration settings that shouldn't have to change all that often */ | |
168 | #define CONFIG_SYS_PROMPT "U-Boot> " | |
169 | #define CONFIG_SYS_CBSIZE 256 | |
170 | #define CONFIG_SYS_MAXARGS 16 | |
171 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
172 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
173 | #define CONFIG_SYS_LONGHELP | |
174 | ||
175 | #define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE | |
176 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x700000) | |
ad7a1785 AB |
177 | |
178 | #endif /* __GRASSHOPPER_CONFIG_H */ | |
179 | /* vim: set ts=8 noet: */ |