[people/ms/u-boot.git] / include / configs / hmi1001.h

/*
 * (C) Copyright 2003-2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU		*/
#define CONFIG_MPC5200		1	/* (more precisely an MPC5200 CPU)	*/
#define CONFIG_HMI1001		1	/* HMI1001 board			*/

#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz		*/

#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM		0x02	/* Software reboot			*/

#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs			*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
#endif

#define CONFIG_BOARD_EARLY_INIT_R

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1	*/
#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps	*/
#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

/* Partitions */
#define CONFIG_DOS_PARTITION

/*
 * Supported commands
 */
#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
				CFG_CMD_DATE	| \
				CFG_CMD_DISPLAY	| \
				CFG_CMD_DHCP	| \
				CFG_CMD_EEPROM	| \
				CFG_CMD_I2C	| \
				CFG_CMD_IDE	| \
				CFG_CMD_NFS	| \
				CFG_CMD_PCI	| \
				CFG_CMD_SNTP	)

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

#define	CONFIG_TIMESTAMP	1	/* Print image info with timestamp */

#if (TEXT_BASE == 0xFFF00000) /* Boot low */
#   define CFG_LOWBOOT		1
#endif

/*
 * Autobooting
 */
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */

#define CONFIG_PREBOOT	"echo;" \
	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=$(serverip):$(rootpath)\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs $(bootargs) "				\
		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
		":$(hostname):$(netdev):off panic=1\0"			\
	"flash_nfs=run nfsargs addip;"					\
		"bootm $(kernel_addr)\0"				\
	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"	\
	"rootpath=/opt/eldk/ppc_82xx\0"					\
	""

#define CONFIG_BOOTCOMMAND	"run net_nfs"

#define CONFIG_MISC_INIT_R	1

/*
 * IPB Bus clocking configuration.
 */
#undef CFG_IPBSPEED_133		/* define for 133MHz speed */

/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
#define CFG_I2C_MODULE		2	/* Select I2C module #1 or #2 */

#define CFG_I2C_SPEED		100000 /* 100 kHz */
#define CFG_I2C_SLAVE		0x7F

/*
 * EEPROM configuration
 */
#define CFG_I2C_EEPROM_ADDR		0x58
#define CFG_I2C_EEPROM_ADDR_LEN		1
#define CFG_EEPROM_PAGE_WRITE_BITS	4
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10

/*
 * RTC configuration
 */
#define CONFIG_RTC_PCF8563
#define CFG_I2C_RTC_ADDR		0x51

/*
 * Flash configuration
 */
#define CFG_FLASH_BASE		0xFF800000

#define CFG_FLASH_SIZE		0x00800000 /* 8 MByte */
#define CFG_MAX_FLASH_SECT	67	/* max num of sects on one chip */

#define CFG_ENV_ADDR		(TEXT_BASE+0x40000) /* second sector */
#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks
					   (= chip selects) */
#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/

#define CFG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_CFI_AMD_RESET

/*
 * Environment settings
 */
#define CFG_ENV_IS_IN_FLASH	1
#define CFG_ENV_SIZE		0x4000
#define CFG_ENV_SECT_SIZE	0x20000
#define CFG_ENV_OFFSET_REDUND   (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)

/*
 * Memory map
 */
#define CFG_MBAR		0xF0000000
#define CFG_SDRAM_BASE		0x00000000
#define CFG_DEFAULT_MBAR	0x80000000
#define CFG_DISPLAY_BASE	0x80600000
#define CFG_STATUS1_BASE	0x80600200
#define CFG_STATUS2_BASE	0x80600300

/* Settings for XLB = 132 MHz */
#define SDRAM_DDR	 1
#define SDRAM_MODE      0x018D0000
#define SDRAM_EMODE     0x40090000
#define SDRAM_CONTROL   0x714f0f00
#define SDRAM_CONFIG1   0x73722930
#define SDRAM_CONFIG2   0x47770000
#define SDRAM_TAPDELAY  0x10000000

/* Use ON-Chip SRAM until RAM will be available */
#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
#ifdef CONFIG_POST
/* preserve space for the post_word at end of on-chip SRAM */
#define CFG_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
#else
#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE
#endif


#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

#define CFG_MONITOR_BASE    TEXT_BASE
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#   define CFG_RAMBOOT		1
#endif

#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
#define CFG_MALLOC_LEN		(512 << 10)	/* Reserve 128 kB for malloc()	*/
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*
 * Ethernet configuration
 */
#define CONFIG_MPC5xxx_FEC	1
#define CONFIG_PHY_ADDR		0x00

/*
 * GPIO configuration
 */
#define CFG_GPS_PORT_CONFIG	0x01051004

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory	    */
#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
#else
#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS		16	/* max number of command args	*/
#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/

/* Enable an alternate, more extensive memory test */
#define CFG_ALT_MEMTEST

#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/

#define CFG_LOAD_ADDR		0x100000	/* default load address */

#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */

/*
 * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
 * which is normally part of the default commands (CFV_CMD_DFL)
 */
#define CONFIG_LOOPW

/*
 * Various low-level settings
 */
#if defined(CONFIG_MPC5200)
#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
#define CFG_HID0_FINAL		HID0_ICE
#else
#define CFG_HID0_INIT		0
#define CFG_HID0_FINAL		0
#endif

#define CFG_BOOTCS_START	CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
#define CFG_BOOTCS_CFG		0x0004FB00
#define CFG_CS0_START		CFG_FLASH_BASE
#define CFG_CS0_SIZE		CFG_FLASH_SIZE

/* 8Mbit SRAM @0x80100000 */
#define CFG_CS1_START		0x80100000
#define CFG_CS1_SIZE		0x00100000
#define CFG_CS1_CFG		0x19B00

/* FRAM 32Kbyte @0x80700000 */
#define CFG_CS2_START		0x80700000
#define CFG_CS2_SIZE		0x00008000
#define CFG_CS2_CFG		0x19800

/* Display H1, Status Inputs, EPLD @0x80600000 */
#define CFG_CS3_START		0x80600000
#define CFG_CS3_SIZE		0x00100000
#define CFG_CS3_CFG		0x00019800

#define CFG_CS_BURST		0x00000000
#define CFG_CS_DEADCYCLE	0x33333333

/*-----------------------------------------------------------------------
 * IDE/ATA stuff Supports IDE harddisk
 *-----------------------------------------------------------------------
 */

#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/

#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CFG_IDE_MAXDEVICE	2	/* max. 2 drives per IDE bus	*/

#define CONFIG_IDE_PREINIT	1

#define CFG_ATA_IDE0_OFFSET	0x0000

#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA

/* Offset for data I/O			*/
#define CFG_ATA_DATA_OFFSET	(0x0060)

/* Offset for normal register accesses	*/
#define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)

/* Offset for alternate registers	*/
#define CFG_ATA_ALT_OFFSET	(0x005C)

/* Interval between registers                                                */
#define CFG_ATA_STRIDE          4

#define CONFIG_ATAPI            1

#define CONFIG_VIDEO_SMI_LYNXEM
#define CONFIG_CFB_CONSOLE
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_VIDEO_LOGO

/*
 * PCI Mapping:
 * 0x40000000 - 0x4fffffff - PCI Memory
 * 0x50000000 - 0x50ffffff - PCI IO Space
 */
#define CONFIG_PCI		1
#define CONFIG_PCI_PNP		1
#define CONFIG_PCI_SCAN_SHOW	1

#define CONFIG_PCI_MEM_BUS	0x40000000
#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE	0x10000000

#define CONFIG_PCI_IO_BUS	0x50000000
#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE	0x01000000

#define CFG_ISA_IO		CONFIG_PCI_IO_BUS

/*---------------------------------------------------------------------*/
/* Display addresses						       */
/*---------------------------------------------------------------------*/

#define CFG_DISP_CHR_RAM	(CFG_DISPLAY_BASE + 0x38)
#define CFG_DISP_CWORD		(CFG_DISPLAY_BASE + 0x30)

#endif /* __CONFIG_H */
Commit	Line	Data
a87589da WD	1	/*
	2	* (C) Copyright 2003-2005
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#ifndef __CONFIG_H
	25	#define __CONFIG_H
	26
	27	/*
	28	* High Level Configuration Options
	29	* (easy to change)
	30	*/
	31
	32	#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
	33	#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
	34	#define CONFIG_HMI1001 1 /* HMI1001 board */
	35
	36	#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
	37
	38	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	39	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	40
	41	#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
	42	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	43	# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	44	#endif
	45
	46	#define CONFIG_BOARD_EARLY_INIT_R
	47
	48	/*
	49	* Serial console configuration
	50	*/
	51	#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
	52	#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
	53	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
	54
08abe158 WD	55	/* Partitions */
	56	#define CONFIG_DOS_PARTITION
	57
a87589da WD	58	/*
	59	* Supported commands
	60	*/
	61	#define CONFIG_COMMANDS (CONFIG_CMD_DFL \| \
342717f7	62	CFG_CMD_DATE \| \
9f96ae44	63	CFG_CMD_DISPLAY \| \
a87589da	64	CFG_CMD_DHCP \| \
342717f7 WD	65	CFG_CMD_EEPROM \| \
342717f7 WD	66	CFG_CMD_I2C \| \
08abe158	67	CFG_CMD_IDE \| \
a87589da	68	CFG_CMD_NFS \| \
98128f38	69	CFG_CMD_PCI \| \
9f96ae44	70	CFG_CMD_SNTP )
a87589da WD	71
	72	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
	73	#include <cmd_confdefs.h>
	74
	75	#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
	76
	77	#if (TEXT_BASE == 0xFFF00000) /* Boot low */
	78	# define CFG_LOWBOOT 1
	79	#endif
	80
	81	/*
	82	* Autobooting
	83	*/
	84	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	85
	86	#define CONFIG_PREBOOT "echo;" \
	87	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	88	"echo"
	89
	90	#undef CONFIG_BOOTARGS
	91
	92	#define CONFIG_EXTRA_ENV_SETTINGS \
	93	"netdev=eth0\0" \
	94	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	95	"nfsroot=$(serverip):$(rootpath)\0" \
	96	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	97	"addip=setenv bootargs $(bootargs) " \
	98	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
	99	":$(hostname):$(netdev):off panic=1\0" \
	100	"flash_nfs=run nfsargs addip;" \
	101	"bootm $(kernel_addr)\0" \
	102	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
	103	"rootpath=/opt/eldk/ppc_82xx\0" \
	104	""
	105
	106	#define CONFIG_BOOTCOMMAND "run net_nfs"
	107
9f96ae44 WD	108	#define CONFIG_MISC_INIT_R 1
9f96ae44 WD	109
a87589da WD	110	/*
	111	* IPB Bus clocking configuration.
	112	*/
	113	#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
	114
342717f7 WD	115	/*
	116	* I2C configuration
	117	*/
	118	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
	119	#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
	120
	121	#define CFG_I2C_SPEED 100000 /* 100 kHz */
	122	#define CFG_I2C_SLAVE 0x7F
	123
	124	/*
	125	* EEPROM configuration
	126	*/
	127	#define CFG_I2C_EEPROM_ADDR 0x58
	128	#define CFG_I2C_EEPROM_ADDR_LEN 1
	129	#define CFG_EEPROM_PAGE_WRITE_BITS 4
	130	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
	131
	132	/*
	133	* RTC configuration
	134	*/
	135	#define CONFIG_RTC_PCF8563
	136	#define CFG_I2C_RTC_ADDR 0x51
	137
a87589da WD	138	/*
	139	* Flash configuration
	140	*/
	141	#define CFG_FLASH_BASE 0xFF800000
	142
	143	#define CFG_FLASH_SIZE 0x00800000 /* 8 MByte */
	144	#define CFG_MAX_FLASH_SECT 67 /* max num of sects on one chip */
	145
	146	#define CFG_ENV_ADDR (TEXT_BASE+0x40000) /* second sector */
	147	#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
	148	(= chip selects) */
	149	#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
	150	#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
	151
	152	#define CFG_FLASH_CFI_DRIVER
	153	#define CFG_FLASH_CFI
	154	#define CFG_FLASH_EMPTY_INFO
	155	#define CFG_FLASH_CFI_AMD_RESET
a87589da WD	156
	157	/*
	158	* Environment settings
	159	*/
	160	#define CFG_ENV_IS_IN_FLASH 1
	161	#define CFG_ENV_SIZE 0x4000
	162	#define CFG_ENV_SECT_SIZE 0x20000
024447b1 WD	163	#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
024447b1 WD	164	#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
a87589da WD	165
	166	/*
	167	* Memory map
	168	*/
	169	#define CFG_MBAR 0xF0000000
	170	#define CFG_SDRAM_BASE 0x00000000
	171	#define CFG_DEFAULT_MBAR 0x80000000
9f96ae44 WD	172	#define CFG_DISPLAY_BASE 0x80600000
	173	#define CFG_STATUS1_BASE 0x80600200
	174	#define CFG_STATUS2_BASE 0x80600300
a87589da WD	175
	176	/* Settings for XLB = 132 MHz */
	177	#define SDRAM_DDR 1
	178	#define SDRAM_MODE 0x018D0000
	179	#define SDRAM_EMODE 0x40090000
	180	#define SDRAM_CONTROL 0x714f0f00
	181	#define SDRAM_CONFIG1 0x73722930
	182	#define SDRAM_CONFIG2 0x47770000
	183	#define SDRAM_TAPDELAY 0x10000000
	184
	185	/* Use ON-Chip SRAM until RAM will be available */
	186	#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
	187	#ifdef CONFIG_POST
	188	/* preserve space for the post_word at end of on-chip SRAM */
	189	#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
	190	#else
	191	#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
	192	#endif
	193
	194
	195	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	196	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	197	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	198
	199	#define CFG_MONITOR_BASE TEXT_BASE
	200	#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
	201	# define CFG_RAMBOOT 1
	202	#endif
	203
	204	#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
342717f7	205	#define CFG_MALLOC_LEN (512 << 10) /* Reserve 128 kB for malloc() */
a87589da WD	206	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	207
	208	/*
	209	* Ethernet configuration
	210	*/
	211	#define CONFIG_MPC5xxx_FEC 1
	212	#define CONFIG_PHY_ADDR 0x00
	213
	214	/*
	215	* GPIO configuration
	216	*/
	217	#define CFG_GPS_PORT_CONFIG 0x01051004
	218
a87589da WD	219	/*
	220	* Miscellaneous configurable options
	221	*/
	222	#define CFG_LONGHELP /* undef to save memory */
	223	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	224	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	225	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	226	#else
	227	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	228	#endif
	229	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	230	#define CFG_MAXARGS 16 /* max number of command args */
	231	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	232
	233	/* Enable an alternate, more extensive memory test */
	234	#define CFG_ALT_MEMTEST
	235
	236	#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
	237	#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
	238
	239	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	240
	241	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	242
	243	/*
	244	* Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
	245	* which is normally part of the default commands (CFV_CMD_DFL)
	246	*/
	247	#define CONFIG_LOOPW
	248
	249	/*
	250	* Various low-level settings
	251	*/
	252	#if defined(CONFIG_MPC5200)
	253	#define CFG_HID0_INIT HID0_ICE \| HID0_ICFI
	254	#define CFG_HID0_FINAL HID0_ICE
	255	#else
	256	#define CFG_HID0_INIT 0
	257	#define CFG_HID0_FINAL 0
	258	#endif
	259
	260	#define CFG_BOOTCS_START CFG_FLASH_BASE
	261	#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
	262	#define CFG_BOOTCS_CFG 0x0004FB00
	263	#define CFG_CS0_START CFG_FLASH_BASE
	264	#define CFG_CS0_SIZE CFG_FLASH_SIZE
	265
	266	/* 8Mbit SRAM @0x80100000 */
	267	#define CFG_CS1_START 0x80100000
	268	#define CFG_CS1_SIZE 0x00100000
	269	#define CFG_CS1_CFG 0x19B00
	270
	271	/* FRAM 32Kbyte @0x80700000 */
	272	#define CFG_CS2_START 0x80700000
	273	#define CFG_CS2_SIZE 0x00008000
	274	#define CFG_CS2_CFG 0x19800
	275
	276	/* Display H1, Status Inputs, EPLD @0x80600000 */
	277	#define CFG_CS3_START 0x80600000
9f96ae44	278	#define CFG_CS3_SIZE 0x00100000
f7fbf269	279	#define CFG_CS3_CFG 0x00019800
a87589da WD	280
	281	#define CFG_CS_BURST 0x00000000
	282	#define CFG_CS_DEADCYCLE 0x33333333
	283
08abe158 WD	284	/*-----------------------------------------------------------------------
	285	* IDE/ATA stuff Supports IDE harddisk
	286	*-----------------------------------------------------------------------
	287	*/
	288
	289	#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
	290
	291	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
	292	#undef CONFIG_IDE_LED /* LED for ide not supported */
	293
	294	#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
	295	#define CFG_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
	296
9d3338d2 WD	297	#define CONFIG_IDE_PREINIT 1
9d3338d2 WD	298
08abe158 WD	299	#define CFG_ATA_IDE0_OFFSET 0x0000
	300
	301	#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
	302
	303	/* Offset for data I/O */
	304	#define CFG_ATA_DATA_OFFSET (0x0060)
	305
	306	/* Offset for normal register accesses */
	307	#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
	308
	309	/* Offset for alternate registers */
	310	#define CFG_ATA_ALT_OFFSET (0x005C)
	311
	312	/* Interval between registers */
	313	#define CFG_ATA_STRIDE 4
	314
	315	#define CONFIG_ATAPI 1
	316
ccd9d3d6 WD	317	#define CONFIG_VIDEO_SMI_LYNXEM
	318	#define CONFIG_CFB_CONSOLE
	319	#define CONFIG_VGA_AS_SINGLE_DEVICE
	320	#define CONFIG_VIDEO_LOGO
	321
98128f38 WD	322	/*
	323	* PCI Mapping:
	324	* 0x40000000 - 0x4fffffff - PCI Memory
	325	* 0x50000000 - 0x50ffffff - PCI IO Space
	326	*/
	327	#define CONFIG_PCI 1
	328	#define CONFIG_PCI_PNP 1
	329	#define CONFIG_PCI_SCAN_SHOW 1
	330
	331	#define CONFIG_PCI_MEM_BUS 0x40000000
	332	#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
	333	#define CONFIG_PCI_MEM_SIZE 0x10000000
	334
	335	#define CONFIG_PCI_IO_BUS 0x50000000
	336	#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
	337	#define CONFIG_PCI_IO_SIZE 0x01000000
	338
ccd9d3d6 WD	339	#define CFG_ISA_IO CONFIG_PCI_IO_BUS
ccd9d3d6 WD	340
9f96ae44 WD	341	/---------------------------------------------------------------------/
	342	/* Display addresses */
	343	/---------------------------------------------------------------------/
	344
	345	#define CFG_DISP_CHR_RAM (CFG_DISPLAY_BASE + 0x38)
	346	#define CFG_DISP_CWORD (CFG_DISPLAY_BASE + 0x30)
	347
a87589da	348	#endif /* __CONFIG_H */