[people/ms/u-boot.git] / include / configs / hmi1001.h

/*
 * (C) Copyright 2003-2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU		*/
#define CONFIG_MPC5200		1	/* (more precisely an MPC5200 CPU)	*/
#define CONFIG_HMI1001		1	/* HMI1001 board			*/

#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz		*/

#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM		0x02	/* Software reboot			*/

#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs			*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
#endif

#define CONFIG_BOARD_EARLY_INIT_R

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1	*/
#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps	*/
#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

/*
 * Supported commands
 */
#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
				CFG_CMD_DHCP	| \
				CFG_CMD_NFS	| \
				CFG_CMD_SNTP)

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

#define	CONFIG_TIMESTAMP	1	/* Print image info with timestamp */

#if (TEXT_BASE == 0xFFF00000) /* Boot low */
#   define CFG_LOWBOOT		1
#endif

/*
 * Autobooting
 */
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */

#define CONFIG_PREBOOT	"echo;" \
	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=$(serverip):$(rootpath)\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs $(bootargs) "				\
		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
		":$(hostname):$(netdev):off panic=1\0"			\
	"flash_nfs=run nfsargs addip;"					\
		"bootm $(kernel_addr)\0"				\
	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"	\
	"rootpath=/opt/eldk/ppc_82xx\0"					\
	""

#define CONFIG_BOOTCOMMAND	"run net_nfs"

/*
 * IPB Bus clocking configuration.
 */
#undef CFG_IPBSPEED_133		/* define for 133MHz speed */

/*
 * Flash configuration
 */
#define CFG_FLASH_BASE		0xFF800000

#define CFG_FLASH_SIZE		0x00800000 /* 8 MByte */
#define CFG_MAX_FLASH_SECT	67	/* max num of sects on one chip */

#define CFG_ENV_ADDR		(TEXT_BASE+0x40000) /* second sector */
#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks
					   (= chip selects) */
#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/

#define CFG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_CFI_AMD_RESET
#define CFG_FLASH_PROTECTION

/*
 * Environment settings
 */
#define CFG_ENV_IS_IN_FLASH	1
#define CFG_ENV_SIZE		0x4000
#define CFG_ENV_SECT_SIZE	0x20000

/*
 * Memory map
 */
#define CFG_MBAR		0xF0000000
#define CFG_SDRAM_BASE		0x00000000
#define CFG_DEFAULT_MBAR	0x80000000

/* Settings for XLB = 132 MHz */
#define SDRAM_DDR	 1
#define SDRAM_MODE      0x018D0000
#define SDRAM_EMODE     0x40090000
#define SDRAM_CONTROL   0x714f0f00
#define SDRAM_CONFIG1   0x73722930
#define SDRAM_CONFIG2   0x47770000
#define SDRAM_TAPDELAY  0x10000000

/* Use ON-Chip SRAM until RAM will be available */
#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
#ifdef CONFIG_POST
/* preserve space for the post_word at end of on-chip SRAM */
#define CFG_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
#else
#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE
#endif


#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

#define CFG_MONITOR_BASE    TEXT_BASE
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#   define CFG_RAMBOOT		1
#endif

#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*
 * Ethernet configuration
 */
#define CONFIG_MPC5xxx_FEC	1
#define CONFIG_PHY_ADDR		0x00

/*
 * GPIO configuration
 */
#define CFG_GPS_PORT_CONFIG	0x01051004

/*
 * RTC configuration
 */
#define CONFIG_RTC_MPC5200	1	/* use internal MPC5200 RTC */

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory	    */
#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
#else
#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS		16	/* max number of command args	*/
#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/

/* Enable an alternate, more extensive memory test */
#define CFG_ALT_MEMTEST

#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/

#define CFG_LOAD_ADDR		0x100000	/* default load address */

#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */

/*
 * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
 * which is normally part of the default commands (CFV_CMD_DFL)
 */
#define CONFIG_LOOPW

/*
 * Various low-level settings
 */
#if defined(CONFIG_MPC5200)
#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
#define CFG_HID0_FINAL		HID0_ICE
#else
#define CFG_HID0_INIT		0
#define CFG_HID0_FINAL		0
#endif

#define CFG_BOOTCS_START	CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
#define CFG_BOOTCS_CFG		0x0004FB00
#define CFG_CS0_START		CFG_FLASH_BASE
#define CFG_CS0_SIZE		CFG_FLASH_SIZE

/* 8Mbit SRAM @0x80100000 */
#define CFG_CS1_START		0x80100000
#define CFG_CS1_SIZE		0x00100000
#define CFG_CS1_CFG		0x19B00

/* FRAM 32Kbyte @0x80700000 */
#define CFG_CS2_START		0x80700000
#define CFG_CS2_SIZE		0x00008000
#define CFG_CS2_CFG		0x19800

/* Display H1, Status Inputs, EPLD @0x80600000 */
#define CFG_CS3_START		0x80600000
#define CFG_CS3_SIZE		0x00000210
#define CFG_CS3_CFG		0x9800

#define CFG_CS_BURST		0x00000000
#define CFG_CS_DEADCYCLE	0x33333333

#endif /* __CONFIG_H */
Commit	Line	Data
a87589da WD	1	/*
	2	* (C) Copyright 2003-2005
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#ifndef __CONFIG_H
	25	#define __CONFIG_H
	26
	27	/*
	28	* High Level Configuration Options
	29	* (easy to change)
	30	*/
	31
	32	#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
	33	#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
	34	#define CONFIG_HMI1001 1 /* HMI1001 board */
	35
	36	#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
	37
	38	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	39	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	40
	41	#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
	42	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	43	# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	44	#endif
	45
	46	#define CONFIG_BOARD_EARLY_INIT_R
	47
	48	/*
	49	* Serial console configuration
	50	*/
	51	#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
	52	#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
	53	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
	54
	55	/*
	56	* Supported commands
	57	*/
	58	#define CONFIG_COMMANDS (CONFIG_CMD_DFL \| \
	59	CFG_CMD_DHCP \| \
	60	CFG_CMD_NFS \| \
	61	CFG_CMD_SNTP)
	62
	63	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
	64	#include <cmd_confdefs.h>
65
66	#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
67
68	#if (TEXT_BASE == 0xFFF00000) /* Boot low */
69	# define CFG_LOWBOOT 1
70	#endif
71
72	/*
73	* Autobooting
74	*/
75	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
76
77	#define CONFIG_PREBOOT "echo;" \
78	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
79	"echo"
80
81	#undef CONFIG_BOOTARGS
82
83	#define CONFIG_EXTRA_ENV_SETTINGS \
84	"netdev=eth0\0" \
85	"nfsargs=setenv bootargs root=/dev/nfs rw " \
86	"nfsroot=$(serverip):$(rootpath)\0" \
87	"ramargs=setenv bootargs root=/dev/ram rw\0" \
88	"addip=setenv bootargs $(bootargs) " \
89	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
90	":$(hostname):$(netdev):off panic=1\0" \
91	"flash_nfs=run nfsargs addip;" \
92	"bootm $(kernel_addr)\0" \
93	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
94	"rootpath=/opt/eldk/ppc_82xx\0" \
95	""
96
97	#define CONFIG_BOOTCOMMAND "run net_nfs"
98
99	/*
100	* IPB Bus clocking configuration.
101	*/
102	#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
103
104	/*
105	* Flash configuration
106	*/
107	#define CFG_FLASH_BASE 0xFF800000
108
109	#define CFG_FLASH_SIZE 0x00800000 /* 8 MByte */
110	#define CFG_MAX_FLASH_SECT 67 /* max num of sects on one chip */
111
112	#define CFG_ENV_ADDR (TEXT_BASE+0x40000) /* second sector */
113	#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
114	(= chip selects) */
115	#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
116	#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
117
118	#define CFG_FLASH_CFI_DRIVER
119	#define CFG_FLASH_CFI
120	#define CFG_FLASH_EMPTY_INFO
121	#define CFG_FLASH_CFI_AMD_RESET
122	#define CFG_FLASH_PROTECTION
123
124	/*
125	* Environment settings
126	*/
127	#define CFG_ENV_IS_IN_FLASH 1
128	#define CFG_ENV_SIZE 0x4000
129	#define CFG_ENV_SECT_SIZE 0x20000
130
131	/*
132	* Memory map
133	*/
134	#define CFG_MBAR 0xF0000000
135	#define CFG_SDRAM_BASE 0x00000000
136	#define CFG_DEFAULT_MBAR 0x80000000
137
138	/* Settings for XLB = 132 MHz */
139	#define SDRAM_DDR 1
140	#define SDRAM_MODE 0x018D0000
141	#define SDRAM_EMODE 0x40090000
142	#define SDRAM_CONTROL 0x714f0f00
143	#define SDRAM_CONFIG1 0x73722930
144	#define SDRAM_CONFIG2 0x47770000
145	#define SDRAM_TAPDELAY 0x10000000
146
147	/* Use ON-Chip SRAM until RAM will be available */
148	#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
149	#ifdef CONFIG_POST
150	/* preserve space for the post_word at end of on-chip SRAM */
151	#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
152	#else
153	#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
154	#endif
155
156
157	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
158	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
159	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
160
161	#define CFG_MONITOR_BASE TEXT_BASE
162	#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
163	# define CFG_RAMBOOT 1
164	#endif
165
166	#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
167	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
168	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
169
170	/*
171	* Ethernet configuration
172	*/
173	#define CONFIG_MPC5xxx_FEC 1
174	#define CONFIG_PHY_ADDR 0x00
175
176	/*
177	* GPIO configuration
178	*/
179	#define CFG_GPS_PORT_CONFIG 0x01051004
180
181	/*
182	* RTC configuration
183	*/
184	#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
185
186	/*
187	* Miscellaneous configurable options
188	*/
189	#define CFG_LONGHELP /* undef to save memory */
190	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
191	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
192	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
193	#else
194	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
195	#endif
196	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
197	#define CFG_MAXARGS 16 /* max number of command args */
198	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
199
200	/* Enable an alternate, more extensive memory test */
201	#define CFG_ALT_MEMTEST
202
203	#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
204	#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
205
206	#define CFG_LOAD_ADDR 0x100000 /* default load address */
207
208	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
209
210	/*
211	* Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
212	* which is normally part of the default commands (CFV_CMD_DFL)
213	*/
214	#define CONFIG_LOOPW
215
216	/*
217	* Various low-level settings
218	*/
219	#if defined(CONFIG_MPC5200)
220	#define CFG_HID0_INIT HID0_ICE \| HID0_ICFI
221	#define CFG_HID0_FINAL HID0_ICE
222	#else
223	#define CFG_HID0_INIT 0
224	#define CFG_HID0_FINAL 0
225	#endif
226
227	#define CFG_BOOTCS_START CFG_FLASH_BASE
228	#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
229	#define CFG_BOOTCS_CFG 0x0004FB00
230	#define CFG_CS0_START CFG_FLASH_BASE
231	#define CFG_CS0_SIZE CFG_FLASH_SIZE
232
233	/* 8Mbit SRAM @0x80100000 */
234	#define CFG_CS1_START 0x80100000
235	#define CFG_CS1_SIZE 0x00100000
236	#define CFG_CS1_CFG 0x19B00
237
238	/* FRAM 32Kbyte @0x80700000 */
239	#define CFG_CS2_START 0x80700000
240	#define CFG_CS2_SIZE 0x00008000
241	#define CFG_CS2_CFG 0x19800
242
243	/* Display H1, Status Inputs, EPLD @0x80600000 */
244	#define CFG_CS3_START 0x80600000
245	#define CFG_CS3_SIZE 0x00000210
246	#define CFG_CS3_CFG 0x9800
247
248	#define CFG_CS_BURST 0x00000000
249	#define CFG_CS_DEADCYCLE 0x33333333
250
251	#endif /* __CONFIG_H */