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1/*
2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27/*
28 * High Level Configuration Options
29 * (easy to change)
30 */
31
32#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
33#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
34#define CONFIG_HMI1001 1 /* HMI1001 board */
35
36#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
37
38#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
39#define BOOTFLAG_WARM 0x02 /* Software reboot */
40
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41#define CONFIG_BOARD_EARLY_INIT_R
42
43/*
44 * Serial console configuration
45 */
46#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
47#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
48#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
49
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50/* Partitions */
51#define CONFIG_DOS_PARTITION
52
48d5d102 53
a87589da 54/*
48d5d102 55 * Command line configuration.
a87589da 56 */
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57#include <config_cmd_default.h>
58
59#define CONFIG_CMD_DATE
60#define CONFIG_CMD_DISPLAY
61#define CONFIG_CMD_DHCP
62#define CONFIG_CMD_EEPROM
63#define CONFIG_CMD_I2C
64#define CONFIG_CMD_IDE
65#define CONFIG_CMD_NFS
66#define CONFIG_CMD_PCI
67#define CONFIG_CMD_SNTP
68
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69
70#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
71
72#if (TEXT_BASE == 0xFFF00000) /* Boot low */
73# define CFG_LOWBOOT 1
74#endif
75
76/*
77 * Autobooting
78 */
79#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
80
81#define CONFIG_PREBOOT "echo;" \
82 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
83 "echo"
84
85#undef CONFIG_BOOTARGS
86
87#define CONFIG_EXTRA_ENV_SETTINGS \
88 "netdev=eth0\0" \
89 "nfsargs=setenv bootargs root=/dev/nfs rw " \
fe126d8b 90 "nfsroot=${serverip}:${rootpath}\0" \
a87589da 91 "ramargs=setenv bootargs root=/dev/ram rw\0" \
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92 "addip=setenv bootargs ${bootargs} " \
93 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
94 ":${hostname}:${netdev}:off panic=1\0" \
a87589da 95 "flash_nfs=run nfsargs addip;" \
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96 "bootm ${kernel_addr}\0" \
97 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
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98 "rootpath=/opt/eldk/ppc_82xx\0" \
99 ""
100
101#define CONFIG_BOOTCOMMAND "run net_nfs"
102
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103#define CONFIG_MISC_INIT_R 1
104
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105/*
106 * IPB Bus clocking configuration.
107 */
c99512d6 108#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
a87589da 109
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110/*
111 * I2C configuration
112 */
113#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
114#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
115
116#define CFG_I2C_SPEED 100000 /* 100 kHz */
117#define CFG_I2C_SLAVE 0x7F
118
119/*
120 * EEPROM configuration
121 */
122#define CFG_I2C_EEPROM_ADDR 0x58
123#define CFG_I2C_EEPROM_ADDR_LEN 1
124#define CFG_EEPROM_PAGE_WRITE_BITS 4
125#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
126
127/*
128 * RTC configuration
129 */
130#define CONFIG_RTC_PCF8563
131#define CFG_I2C_RTC_ADDR 0x51
132
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133/*
134 * Flash configuration
135 */
136#define CFG_FLASH_BASE 0xFF800000
137
138#define CFG_FLASH_SIZE 0x00800000 /* 8 MByte */
139#define CFG_MAX_FLASH_SECT 67 /* max num of sects on one chip */
140
141#define CFG_ENV_ADDR (TEXT_BASE+0x40000) /* second sector */
142#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
143 (= chip selects) */
144#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
145#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
146
147#define CFG_FLASH_CFI_DRIVER
148#define CFG_FLASH_CFI
149#define CFG_FLASH_EMPTY_INFO
150#define CFG_FLASH_CFI_AMD_RESET
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151
152/*
153 * Environment settings
154 */
155#define CFG_ENV_IS_IN_FLASH 1
156#define CFG_ENV_SIZE 0x4000
157#define CFG_ENV_SECT_SIZE 0x20000
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158#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
159#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
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160
161/*
162 * Memory map
163 */
164#define CFG_MBAR 0xF0000000
165#define CFG_SDRAM_BASE 0x00000000
166#define CFG_DEFAULT_MBAR 0x80000000
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167#define CFG_DISPLAY_BASE 0x80600000
168#define CFG_STATUS1_BASE 0x80600200
169#define CFG_STATUS2_BASE 0x80600300
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170
171/* Settings for XLB = 132 MHz */
172#define SDRAM_DDR 1
173#define SDRAM_MODE 0x018D0000
174#define SDRAM_EMODE 0x40090000
175#define SDRAM_CONTROL 0x714f0f00
176#define SDRAM_CONFIG1 0x73722930
177#define SDRAM_CONFIG2 0x47770000
178#define SDRAM_TAPDELAY 0x10000000
179
180/* Use ON-Chip SRAM until RAM will be available */
181#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
182#ifdef CONFIG_POST
183/* preserve space for the post_word at end of on-chip SRAM */
184#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
185#else
186#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
187#endif
188
189
190#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
191#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
192#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
193
194#define CFG_MONITOR_BASE TEXT_BASE
195#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
196# define CFG_RAMBOOT 1
197#endif
198
199#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
342717f7 200#define CFG_MALLOC_LEN (512 << 10) /* Reserve 128 kB for malloc() */
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201#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
202
203/*
204 * Ethernet configuration
205 */
206#define CONFIG_MPC5xxx_FEC 1
207#define CONFIG_PHY_ADDR 0x00
8d7e2732 208#define CONFIG_MII 1 /* MII PHY management */
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209
210/*
211 * GPIO configuration
212 */
213#define CFG_GPS_PORT_CONFIG 0x01051004
214
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215/*
216 * Miscellaneous configurable options
217 */
218#define CFG_LONGHELP /* undef to save memory */
219#define CFG_PROMPT "=> " /* Monitor Command Prompt */
48d5d102 220#if defined(CONFIG_CMD_KGDB)
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221#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
222#else
223#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
224#endif
225#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
226#define CFG_MAXARGS 16 /* max number of command args */
227#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
228
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229#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
230#if defined(CONFIG_CMD_KGDB)
231# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
232#endif
233
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234/* Enable an alternate, more extensive memory test */
235#define CFG_ALT_MEMTEST
236
237#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
238#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
239
240#define CFG_LOAD_ADDR 0x100000 /* default load address */
241
242#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
243
244/*
245 * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
246 * which is normally part of the default commands (CFV_CMD_DFL)
247 */
248#define CONFIG_LOOPW
249
250/*
251 * Various low-level settings
252 */
253#if defined(CONFIG_MPC5200)
254#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
255#define CFG_HID0_FINAL HID0_ICE
256#else
257#define CFG_HID0_INIT 0
258#define CFG_HID0_FINAL 0
259#endif
260
261#define CFG_BOOTCS_START CFG_FLASH_BASE
262#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
263#define CFG_BOOTCS_CFG 0x0004FB00
264#define CFG_CS0_START CFG_FLASH_BASE
265#define CFG_CS0_SIZE CFG_FLASH_SIZE
266
267/* 8Mbit SRAM @0x80100000 */
268#define CFG_CS1_START 0x80100000
269#define CFG_CS1_SIZE 0x00100000
270#define CFG_CS1_CFG 0x19B00
271
272/* FRAM 32Kbyte @0x80700000 */
273#define CFG_CS2_START 0x80700000
274#define CFG_CS2_SIZE 0x00008000
275#define CFG_CS2_CFG 0x19800
276
277/* Display H1, Status Inputs, EPLD @0x80600000 */
278#define CFG_CS3_START 0x80600000
9f96ae44 279#define CFG_CS3_SIZE 0x00100000
f7fbf269 280#define CFG_CS3_CFG 0x00019800
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281
282#define CFG_CS_BURST 0x00000000
283#define CFG_CS_DEADCYCLE 0x33333333
284
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285/*-----------------------------------------------------------------------
286 * IDE/ATA stuff Supports IDE harddisk
287 *-----------------------------------------------------------------------
288 */
289
290#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
291
292#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
293#undef CONFIG_IDE_LED /* LED for ide not supported */
294
295#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
296#define CFG_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
297
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298#define CONFIG_IDE_PREINIT 1
299
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300#define CFG_ATA_IDE0_OFFSET 0x0000
301
302#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
303
304/* Offset for data I/O */
305#define CFG_ATA_DATA_OFFSET (0x0060)
306
307/* Offset for normal register accesses */
308#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
309
310/* Offset for alternate registers */
311#define CFG_ATA_ALT_OFFSET (0x005C)
312
313/* Interval between registers */
314#define CFG_ATA_STRIDE 4
315
316#define CONFIG_ATAPI 1
317
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318#define CONFIG_VIDEO_SMI_LYNXEM
319#define CONFIG_CFB_CONSOLE
320#define CONFIG_VGA_AS_SINGLE_DEVICE
321#define CONFIG_VIDEO_LOGO
322
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323/*
324 * PCI Mapping:
325 * 0x40000000 - 0x4fffffff - PCI Memory
326 * 0x50000000 - 0x50ffffff - PCI IO Space
327 */
328#define CONFIG_PCI 1
329#define CONFIG_PCI_PNP 1
330#define CONFIG_PCI_SCAN_SHOW 1
331
332#define CONFIG_PCI_MEM_BUS 0x40000000
333#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
334#define CONFIG_PCI_MEM_SIZE 0x10000000
335
336#define CONFIG_PCI_IO_BUS 0x50000000
337#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
338#define CONFIG_PCI_IO_SIZE 0x01000000
339
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340#define CFG_ISA_IO CONFIG_PCI_IO_BUS
341
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342/*---------------------------------------------------------------------*/
343/* Display addresses */
344/*---------------------------------------------------------------------*/
345
346#define CFG_DISP_CHR_RAM (CFG_DISPLAY_BASE + 0x38)
347#define CFG_DISP_CWORD (CFG_DISPLAY_BASE + 0x30)
348
a87589da 349#endif /* __CONFIG_H */