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8966f337 WD |
1 | /* |
2 | * (C) Copyright 2000 | |
3 | * Murray Jensen <Murray.Jensen@cmst.csiro.au> | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * Config header file for Hymod board | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
31 | /* | |
32 | * High Level Configuration Options | |
33 | * (easy to change) | |
34 | */ | |
35 | ||
36 | #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ | |
37 | #define CONFIG_HYMOD 1 /* ...on a Hymod board */ | |
9c4c5ae3 | 38 | #define CONFIG_CPM2 1 /* Has a CPM2 */ |
8966f337 | 39 | |
c837dcb1 WD |
40 | #define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ |
41 | ||
8966f337 WD |
42 | #define CONFIG_BOARD_POSTCLK_INIT /* have board_postclk_init() function */ |
43 | ||
44 | /* | |
45 | * select serial console configuration | |
46 | * | |
47 | * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then | |
48 | * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 | |
49 | * for SCC). | |
50 | * | |
51 | * if CONFIG_CONS_NONE is defined, then the serial console routines must | |
52 | * defined elsewhere (for example, on the cogent platform, there are serial | |
53 | * ports on the motherboard which are used for the serial console - see | |
54 | * cogent/cma101/serial.[ch]). | |
55 | */ | |
56 | #undef CONFIG_CONS_ON_SMC /* define if console on SMC */ | |
57 | #define CONFIG_CONS_ON_SCC /* define if console on SCC */ | |
58 | #undef CONFIG_CONS_NONE /* define if console on something else*/ | |
59 | #define CONFIG_CONS_INDEX 1 /* which serial channel for console */ | |
60 | #define CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ | |
61 | #define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */ | |
62 | #define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/ | |
63 | ||
64 | /* | |
65 | * select ethernet configuration | |
66 | * | |
67 | * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then | |
68 | * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 | |
69 | * for FCC) | |
70 | * | |
71 | * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be | |
639221c7 | 72 | * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. |
8966f337 WD |
73 | */ |
74 | #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ | |
75 | #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ | |
76 | #undef CONFIG_ETHER_NONE /* define if ether on something else */ | |
77 | #define CONFIG_ETHER_INDEX 1 /* which channel for ether */ | |
6dd652fa WD |
78 | #define CONFIG_ETHER_LOOPBACK_TEST /* add ether external loopback test */ |
79 | ||
80 | #ifdef CONFIG_ETHER_ON_FCC | |
8966f337 WD |
81 | |
82 | #if (CONFIG_ETHER_INDEX == 1) | |
83 | ||
84 | /* | |
85 | * - Rx-CLK is CLK10 | |
86 | * - Tx-CLK is CLK11 | |
87 | * - RAM for BD/Buffers is on the 60x Bus (see 28-13) | |
88 | * - Enable Full Duplex in FSMR | |
89 | */ | |
6d0f6bcf JCPV |
90 | # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) |
91 | # define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK11) | |
92 | # define CONFIG_SYS_CPMFCR_RAMTYPE 0 | |
93 | # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) | |
8966f337 | 94 | |
6dd652fa | 95 | # define MDIO_PORT 0 /* Port A */ |
be225442 LCM |
96 | # define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ |
97 | (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) | |
98 | # define MDC_DECLARE MDIO_DECLARE | |
99 | ||
6dd652fa WD |
100 | # define MDIO_DATA_PINMASK 0x00040000 /* Pin 13 */ |
101 | # define MDIO_CLCK_PINMASK 0x00080000 /* Pin 12 */ | |
102 | ||
8966f337 WD |
103 | #elif (CONFIG_ETHER_INDEX == 2) |
104 | ||
105 | /* | |
106 | * - Rx-CLK is CLK13 | |
107 | * - Tx-CLK is CLK14 | |
108 | * - RAM for BD/Buffers is on the 60x Bus (see 28-13) | |
109 | * - Enable Full Duplex in FSMR | |
110 | */ | |
6d0f6bcf JCPV |
111 | # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) |
112 | # define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) | |
113 | # define CONFIG_SYS_CPMFCR_RAMTYPE 0 | |
114 | # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) | |
8966f337 | 115 | |
6dd652fa | 116 | # define MDIO_PORT 0 /* Port A */ |
be225442 LCM |
117 | # define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ |
118 | (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) | |
119 | # define MDC_DECLARE MDIO_DECLARE | |
120 | ||
6dd652fa WD |
121 | # define MDIO_DATA_PINMASK 0x00000040 /* Pin 25 */ |
122 | # define MDIO_CLCK_PINMASK 0x00000080 /* Pin 24 */ | |
123 | ||
8966f337 WD |
124 | #elif (CONFIG_ETHER_INDEX == 3) |
125 | ||
126 | /* | |
127 | * - Rx-CLK is CLK15 | |
128 | * - Tx-CLK is CLK16 | |
129 | * - RAM for BD/Buffers is on the 60x Bus (see 28-13) | |
130 | * - Enable Full Duplex in FSMR | |
131 | */ | |
6d0f6bcf JCPV |
132 | # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK) |
133 | # define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16) | |
134 | # define CONFIG_SYS_CPMFCR_RAMTYPE 0 | |
135 | # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) | |
8966f337 | 136 | |
6dd652fa | 137 | # define MDIO_PORT 0 /* Port A */ |
be225442 LCM |
138 | # define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ |
139 | (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) | |
140 | # define MDC_DECLARE MDIO_DECLARE | |
141 | ||
6dd652fa WD |
142 | # define MDIO_DATA_PINMASK 0x00000100 /* Pin 23 */ |
143 | # define MDIO_CLCK_PINMASK 0x00000200 /* Pin 22 */ | |
144 | ||
8966f337 WD |
145 | #endif /* CONFIG_ETHER_INDEX */ |
146 | ||
6dd652fa WD |
147 | #define CONFIG_MII /* MII PHY management */ |
148 | #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ | |
149 | ||
150 | #define MDIO_ACTIVE (iop->pdir |= MDIO_DATA_PINMASK) | |
151 | #define MDIO_TRISTATE (iop->pdir &= ~MDIO_DATA_PINMASK) | |
152 | #define MDIO_READ ((iop->pdat & MDIO_DATA_PINMASK) != 0) | |
153 | ||
154 | #define MDIO(bit) if(bit) iop->pdat |= MDIO_DATA_PINMASK; \ | |
155 | else iop->pdat &= ~MDIO_DATA_PINMASK | |
156 | ||
157 | #define MDC(bit) if(bit) iop->pdat |= MDIO_CLCK_PINMASK; \ | |
158 | else iop->pdat &= ~MDIO_CLCK_PINMASK | |
159 | ||
160 | #define MIIDELAY udelay(1) | |
161 | ||
162 | #endif /* CONFIG_ETHER_ON_FCC */ | |
163 | ||
8966f337 WD |
164 | |
165 | /* other options */ | |
166 | #define CONFIG_HARD_I2C 1 /* To enable I2C hardware support */ | |
6dd652fa | 167 | #define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */ |
8966f337 WD |
168 | |
169 | /* system clock rate (CLKIN) - equal to the 60x and local bus speed */ | |
170 | #ifdef DEBUG | |
171 | #define CONFIG_8260_CLKIN 33333333 /* in Hz */ | |
172 | #else | |
173 | #define CONFIG_8260_CLKIN 66666666 /* in Hz */ | |
174 | #endif | |
175 | ||
176 | #if defined(CONFIG_CONS_USE_EXTC) | |
177 | #define CONFIG_BAUDRATE 115200 | |
178 | #else | |
6dd652fa | 179 | #define CONFIG_BAUDRATE 9600 |
8966f337 WD |
180 | #endif |
181 | ||
182 | /* default ip addresses - these will be overridden */ | |
183 | #define CONFIG_IPADDR 192.168.1.1 /* hymod "boot" address */ | |
184 | #define CONFIG_SERVERIP 192.168.1.254 /* hymod "server" address */ | |
185 | ||
6dd652fa WD |
186 | #define CONFIG_LAST_STAGE_INIT |
187 | ||
7f5c0157 JL |
188 | /* |
189 | * BOOTP options | |
190 | */ | |
191 | #define CONFIG_BOOTP_BOOTFILESIZE | |
192 | #define CONFIG_BOOTP_BOOTPATH | |
193 | #define CONFIG_BOOTP_GATEWAY | |
194 | #define CONFIG_BOOTP_HOSTNAME | |
195 | ||
196 | ||
48d5d102 JL |
197 | /* |
198 | * Command line configuration. | |
199 | */ | |
4e620410 JCPV |
200 | #include <config_cmd_default.h> |
201 | ||
202 | #define CONFIG_CMD_ASKENV | |
203 | #define CONFIG_CMD_BSP | |
204 | #define CONFIG_CMD_CACHE | |
205 | #define CONFIG_CMD_CDP | |
206 | #define CONFIG_CMD_DATE | |
207 | #define CONFIG_CMD_DHCP | |
208 | #define CONFIG_CMD_DIAG | |
209 | #define CONFIG_CMD_DTT | |
210 | #define CONFIG_CMD_EEPROM | |
211 | #define CONFIG_CMD_ELF | |
212 | #define CONFIG_CMD_FAT | |
213 | #define CONFIG_CMD_I2C | |
214 | #define CONFIG_CMD_IMMAP | |
215 | #define CONFIG_CMD_IRQ | |
216 | #define CONFIG_CMD_KGDB | |
217 | #define CONFIG_CMD_MII | |
218 | #define CONFIG_CMD_PING | |
219 | #define CONFIG_CMD_PORTIO | |
220 | #define CONFIG_CMD_REGINFO | |
221 | #define CONFIG_CMD_SAVES | |
222 | #define CONFIG_CMD_SDRAM | |
223 | #define CONFIG_CMD_SNTP | |
224 | ||
48d5d102 | 225 | #undef CONFIG_CMD_FPGA |
48d5d102 JL |
226 | #undef CONFIG_CMD_XIMG |
227 | ||
8966f337 WD |
228 | #ifdef DEBUG |
229 | #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ | |
6dd652fa WD |
230 | #else |
231 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
232 | #define CONFIG_BOOT_RETRY_TIME 30 /* retry autoboot after 30 secs */ | |
233 | #define CONFIG_BOOT_RETRY_MIN 1 /* can go down to 1 second timeout */ | |
234 | /* Be selective on what keys can delay or stop the autoboot process | |
235 | * To stop use: " " | |
236 | */ | |
237 | #define CONFIG_AUTOBOOT_KEYED | |
238 | #define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, " \ | |
f2302d44 | 239 | "press <SPACE> to stop\n", bootdelay |
6dd652fa WD |
240 | #define CONFIG_AUTOBOOT_STOP_STR " " |
241 | #undef CONFIG_AUTOBOOT_DELAY_STR | |
242 | #define DEBUG_BOOTKEYS 0 | |
8966f337 WD |
243 | #endif |
244 | ||
48d5d102 | 245 | #if defined(CONFIG_CMD_KGDB) |
8966f337 WD |
246 | #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ |
247 | #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ | |
248 | #undef CONFIG_KGDB_NONE /* define if kgdb on something else */ | |
249 | #define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */ | |
250 | #define CONFIG_KGDB_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ | |
251 | #define CONFIG_KGDB_EXTC_RATE 3686400 /* serial ext clk rate in Hz */ | |
252 | #define CONFIG_KGDB_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/ | |
253 | # if defined(CONFIG_KGDB_USE_EXTC) | |
592c5cab | 254 | #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ |
8966f337 | 255 | # else |
6dd652fa | 256 | #define CONFIG_KGDB_BAUDRATE 9600 /* speed to run kgdb serial port at */ |
8966f337 WD |
257 | # endif |
258 | #endif | |
259 | ||
260 | #undef CONFIG_WATCHDOG /* disable platform specific watchdog */ | |
261 | ||
262 | #define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */ | |
263 | ||
264 | /* | |
265 | * Hymod specific configurable options | |
266 | */ | |
6d0f6bcf | 267 | #undef CONFIG_SYS_HYMOD_DBLEDS /* walk mezz board LEDs */ |
8966f337 WD |
268 | |
269 | /* | |
270 | * Miscellaneous configurable options | |
271 | */ | |
6d0f6bcf JCPV |
272 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
273 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
48d5d102 | 274 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 275 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
8966f337 | 276 | #else |
6d0f6bcf | 277 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
8966f337 | 278 | #endif |
6d0f6bcf JCPV |
279 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
280 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
281 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
8966f337 | 282 | |
6d0f6bcf JCPV |
283 | #define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ |
284 | #define CONFIG_SYS_MEMTEST_END 0x03c00000 /* 4 ... 60 MB in DRAM */ | |
8966f337 | 285 | |
6d0f6bcf | 286 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
8966f337 | 287 | |
6d0f6bcf | 288 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
8966f337 | 289 | |
6d0f6bcf | 290 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
8966f337 | 291 | |
6d0f6bcf JCPV |
292 | #define CONFIG_SYS_I2C_SPEED 50000 |
293 | #define CONFIG_SYS_I2C_SLAVE 0x7e | |
8966f337 WD |
294 | |
295 | /* these are for the ST M24C02 2kbit serial i2c eeprom */ | |
6d0f6bcf JCPV |
296 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */ |
297 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ | |
6dd652fa | 298 | /* mask of address bits that overflow into the "EEPROM chip address" */ |
6d0f6bcf | 299 | #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 |
6dd652fa | 300 | |
6d0f6bcf JCPV |
301 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16 byte write page size */ |
302 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ | |
6dd652fa | 303 | |
6d0f6bcf | 304 | #define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* hymod has two eeproms */ |
6dd652fa | 305 | |
6d0f6bcf | 306 | #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* philips PCF8563 RTC address */ |
8966f337 | 307 | |
6dd652fa WD |
308 | /* |
309 | * standard dtt sensor configuration - bottom bit will determine local or | |
310 | * remote sensor of the ADM1021, the rest determines index into | |
6d0f6bcf | 311 | * CONFIG_SYS_DTT_ADM1021 array below. |
6dd652fa WD |
312 | * |
313 | * On HYMOD board, the remote sensor should be connected to the MPC8260 | |
314 | * temperature diode thingy, but an errata said this didn't work and | |
315 | * should be disabled - so it isn't connected. | |
316 | */ | |
317 | #if 0 | |
318 | #define CONFIG_DTT_SENSORS { 0, 1 } | |
319 | #else | |
320 | #define CONFIG_DTT_SENSORS { 0 } | |
321 | #endif | |
322 | ||
323 | /* | |
324 | * ADM1021 temp sensor configuration (see dtt/adm1021.c for details). | |
325 | * there will be one entry in this array for each two (dummy) sensors in | |
326 | * CONFIG_DTT_SENSORS. | |
327 | * | |
328 | * For HYMOD board: | |
329 | * - only one ADM1021 | |
330 | * - i2c addr 0x2a (both ADD0 and ADD1 are N/C) | |
331 | * - conversion rate 0x02 = 0.25 conversions/second | |
332 | * - ALERT ouput disabled | |
333 | * - local temp sensor enabled, min set to 0 deg, max set to 85 deg | |
334 | * - remote temp sensor disabled (see comment for CONFIG_DTT_SENSORS above) | |
335 | */ | |
6d0f6bcf | 336 | #define CONFIG_SYS_DTT_ADM1021 { { 0x2a, 0x02, 0, 1, 0, 85, 0, } } |
6dd652fa | 337 | |
8966f337 WD |
338 | /* |
339 | * Low Level Configuration Settings | |
340 | * (address mappings, register initial values, etc.) | |
341 | * You should know what you are doing if you make changes here. | |
342 | */ | |
343 | ||
344 | /*----------------------------------------------------------------------- | |
345 | * Hard Reset Configuration Words | |
346 | * | |
6d0f6bcf | 347 | * if you change bits in the HRCW, you must also change the CONFIG_SYS_* |
8966f337 | 348 | * defines for the various registers affected by the HRCW e.g. changing |
6d0f6bcf | 349 | * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. |
8966f337 WD |
350 | */ |
351 | #ifdef DEBUG | |
6d0f6bcf | 352 | #define CONFIG_SYS_HRCW_MASTER (HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\ |
8966f337 WD |
353 | HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\ |
354 | HRCW_MODCK_H0010) | |
355 | #else | |
6d0f6bcf | 356 | #define CONFIG_SYS_HRCW_MASTER (HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\ |
8966f337 WD |
357 | HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\ |
358 | HRCW_MODCK_H0101) | |
359 | #endif | |
360 | /* no slaves so just duplicate the master hrcw */ | |
6d0f6bcf JCPV |
361 | #define CONFIG_SYS_HRCW_SLAVE1 CONFIG_SYS_HRCW_MASTER |
362 | #define CONFIG_SYS_HRCW_SLAVE2 CONFIG_SYS_HRCW_MASTER | |
363 | #define CONFIG_SYS_HRCW_SLAVE3 CONFIG_SYS_HRCW_MASTER | |
364 | #define CONFIG_SYS_HRCW_SLAVE4 CONFIG_SYS_HRCW_MASTER | |
365 | #define CONFIG_SYS_HRCW_SLAVE5 CONFIG_SYS_HRCW_MASTER | |
366 | #define CONFIG_SYS_HRCW_SLAVE6 CONFIG_SYS_HRCW_MASTER | |
367 | #define CONFIG_SYS_HRCW_SLAVE7 CONFIG_SYS_HRCW_MASTER | |
8966f337 WD |
368 | |
369 | /*----------------------------------------------------------------------- | |
370 | * Internal Memory Mapped Register | |
371 | */ | |
6d0f6bcf | 372 | #define CONFIG_SYS_IMMR 0xF0000000 |
8966f337 WD |
373 | |
374 | /*----------------------------------------------------------------------- | |
375 | * Definitions for initial stack pointer and data area (in DPRAM) | |
376 | */ | |
6d0f6bcf JCPV |
377 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
378 | #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ | |
379 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ | |
380 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
381 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
8966f337 WD |
382 | |
383 | /*----------------------------------------------------------------------- | |
384 | * Start addresses for the final memory configuration | |
385 | * (Set up by the startup code) | |
6d0f6bcf | 386 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
8966f337 | 387 | */ |
6d0f6bcf JCPV |
388 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
389 | #define CONFIG_SYS_FLASH_BASE TEXT_BASE | |
390 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE | |
391 | #define CONFIG_SYS_FPGA_BASE 0x80000000 | |
8966f337 | 392 | /* |
6d0f6bcf | 393 | * unfortunately, CONFIG_SYS_MONITOR_LEN must include the |
8966f337 WD |
394 | * (very large i.e. 256kB) environment flash sector |
395 | */ | |
6d0f6bcf JCPV |
396 | #define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor*/ |
397 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ | |
8966f337 WD |
398 | |
399 | /* | |
400 | * For booting Linux, the board info and command line data | |
401 | * have to be in the first 8 MB of memory, since this is | |
402 | * the maximum mapped by the Linux kernel during initialization. | |
403 | */ | |
6d0f6bcf | 404 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/ |
8966f337 WD |
405 | |
406 | /*----------------------------------------------------------------------- | |
407 | * FLASH organization | |
408 | */ | |
6d0f6bcf JCPV |
409 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */ |
410 | #define CONFIG_SYS_MAX_FLASH_SECT 67 /* max num of sects on one chip */ | |
8966f337 | 411 | |
6d0f6bcf JCPV |
412 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */ |
413 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ | |
8966f337 | 414 | |
5a1aceb0 | 415 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
416 | #define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ |
417 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* see README - env sect real size */ | |
6d0f6bcf JCPV |
418 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) |
419 | #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ | |
8966f337 WD |
420 | |
421 | /*----------------------------------------------------------------------- | |
422 | * Cache Configuration | |
423 | */ | |
6d0f6bcf | 424 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ |
48d5d102 | 425 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 426 | #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value*/ |
8966f337 WD |
427 | #endif |
428 | ||
429 | /*----------------------------------------------------------------------- | |
430 | * HIDx - Hardware Implementation-dependent Registers 2-11 | |
431 | *----------------------------------------------------------------------- | |
432 | * HID0 also contains cache control - initially enable both caches and | |
433 | * invalidate contents, then the final state leaves only the instruction | |
434 | * cache enabled. Note that Power-On and Hard reset invalidate the caches, | |
435 | * but Soft reset does not. | |
436 | * | |
437 | * HID1 has only read-only information - nothing to set. | |
438 | */ | |
6d0f6bcf | 439 | #define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ |
8966f337 WD |
440 | HID0_IFEM|HID0_ABE) |
441 | #ifdef DEBUG | |
6d0f6bcf | 442 | #define CONFIG_SYS_HID0_FINAL 0 |
8966f337 | 443 | #else |
6d0f6bcf | 444 | #define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE) |
8966f337 | 445 | #endif |
6d0f6bcf | 446 | #define CONFIG_SYS_HID2 0 |
8966f337 WD |
447 | |
448 | /*----------------------------------------------------------------------- | |
449 | * RMR - Reset Mode Register 5-5 | |
450 | *----------------------------------------------------------------------- | |
451 | * turn on Checkstop Reset Enable | |
452 | */ | |
453 | #ifdef DEBUG | |
6d0f6bcf | 454 | #define CONFIG_SYS_RMR 0 |
8966f337 | 455 | #else |
6d0f6bcf | 456 | #define CONFIG_SYS_RMR RMR_CSRE |
8966f337 WD |
457 | #endif |
458 | ||
459 | /*----------------------------------------------------------------------- | |
460 | * BCR - Bus Configuration 4-25 | |
461 | *----------------------------------------------------------------------- | |
462 | */ | |
6d0f6bcf | 463 | #define CONFIG_SYS_BCR (BCR_ETM) |
8966f337 WD |
464 | |
465 | /*----------------------------------------------------------------------- | |
466 | * SIUMCR - SIU Module Configuration 4-31 | |
467 | *----------------------------------------------------------------------- | |
468 | */ | |
6d0f6bcf | 469 | #define CONFIG_SYS_SIUMCR (SIUMCR_DPPC10|SIUMCR_L2CPC01|\ |
8966f337 WD |
470 | SIUMCR_APPC10|SIUMCR_MMR11) |
471 | ||
472 | /*----------------------------------------------------------------------- | |
473 | * SYPCR - System Protection Control 4-35 | |
474 | * SYPCR can only be written once after reset! | |
475 | *----------------------------------------------------------------------- | |
476 | * Watchdog & Bus Monitor Timer max, 60x & Local Bus Monitor enable | |
477 | */ | |
478 | #if defined(CONFIG_WATCHDOG) | |
6d0f6bcf | 479 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ |
8966f337 WD |
480 | SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) |
481 | #else | |
6d0f6bcf | 482 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ |
8966f337 WD |
483 | SYPCR_SWRI|SYPCR_SWP) |
484 | #endif /* CONFIG_WATCHDOG */ | |
485 | ||
486 | /*----------------------------------------------------------------------- | |
487 | * TMCNTSC - Time Counter Status and Control 4-40 | |
488 | *----------------------------------------------------------------------- | |
489 | * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, | |
490 | * and enable Time Counter | |
491 | */ | |
6d0f6bcf | 492 | #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) |
8966f337 WD |
493 | |
494 | /*----------------------------------------------------------------------- | |
495 | * PISCR - Periodic Interrupt Status and Control 4-42 | |
496 | *----------------------------------------------------------------------- | |
497 | * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable | |
498 | * Periodic timer | |
499 | */ | |
6d0f6bcf | 500 | #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) |
8966f337 WD |
501 | |
502 | /*----------------------------------------------------------------------- | |
503 | * SCCR - System Clock Control 9-8 | |
504 | *----------------------------------------------------------------------- | |
505 | * Ensure DFBRG is Divide by 16 | |
506 | */ | |
6d0f6bcf | 507 | #define CONFIG_SYS_SCCR (SCCR_DFBRG01) |
8966f337 WD |
508 | |
509 | /*----------------------------------------------------------------------- | |
510 | * RCCR - RISC Controller Configuration 13-7 | |
511 | *----------------------------------------------------------------------- | |
512 | */ | |
6d0f6bcf | 513 | #define CONFIG_SYS_RCCR 0 |
8966f337 WD |
514 | |
515 | /* | |
516 | * Init Memory Controller: | |
517 | * | |
518 | * Bank Bus Machine PortSz Device | |
519 | * ---- --- ------- ------ ------ | |
520 | * 0 60x GPCM 32 bit FLASH | |
521 | * 1 60x GPCM 32 bit FLASH (same as 0 - unused for now) | |
522 | * 2 60x SDRAM 64 bit SDRAM | |
523 | * 3 Local UPMC 8 bit Main Xilinx configuration | |
524 | * 4 Local GPCM 32 bit Main Xilinx register mode | |
525 | * 5 Local UPMB 32 bit Main Xilinx port mode | |
526 | * 6 Local UPMC 8 bit Mezz Xilinx configuration | |
527 | */ | |
528 | ||
529 | /* | |
530 | * Bank 0 - FLASH | |
531 | * | |
532 | * Quotes from the HYMOD IO Board Reference manual: | |
533 | * | |
534 | * "The flash memory is two Intel StrataFlash chips, each configured for | |
535 | * 16 bit operation and connected to give a 32 bit wide port." | |
536 | * | |
537 | * "The chip select logic is configured to respond to both *CS0 and *CS1. | |
538 | * Therefore the FLASH memory will be mapped to both bank 0 and bank 1. | |
539 | * It is suggested that bank 0 be read-only and bank 1 be read/write. The | |
540 | * FLASH will then appear as ROM during boot." | |
541 | * | |
542 | * Initially, we are only going to use bank 0 in read/write mode. | |
543 | */ | |
544 | ||
545 | /* 32 bit, read-write, GPCM on 60x bus */ | |
6d0f6bcf | 546 | #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE&BRx_BA_MSK)|\ |
8966f337 WD |
547 | BRx_PS_32|BRx_MS_GPCM_P|BRx_V) |
548 | /* up to 32 Mb */ | |
6d0f6bcf | 549 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(32)|ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK) |
8966f337 WD |
550 | |
551 | /* | |
552 | * Bank 2 - SDRAM | |
553 | * | |
554 | * Quotes from the HYMOD IO Board Reference manual: | |
555 | * | |
556 | * "The main memory is implemented using TC59SM716FTL-10 SDRAM and has a | |
557 | * fixed size of 64 Mbytes. The Toshiba TC59SM716FTL-10 is a CMOS synchronous | |
558 | * dynamic random access memory organised as 4 banks by 4096 rows by 512 | |
559 | * columns by 16 bits. Four chips provide a 64-bit port on the 60x bus." | |
560 | * | |
561 | * "The locations in SDRAM are accessed using multiplexed address pins to | |
562 | * specify row and column. The pins also act to specify commands. The state | |
563 | * of the inputs *RAS, *CAS and *WE defines the required action. The a10/AP | |
564 | * pin may function as a row address or as the AUTO PRECHARGE control line, | |
565 | * depending on the cycle type. The 60x bus SDRAM machine allows the MPC8260 | |
566 | * address lines to be configured to the required multiplexing scheme." | |
567 | */ | |
568 | ||
6d0f6bcf | 569 | #define CONFIG_SYS_SDRAM_SIZE 64 |
8966f337 WD |
570 | |
571 | /* 64 bit, read-write, SDRAM on 60x bus */ | |
6d0f6bcf | 572 | #define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE&BRx_BA_MSK)|\ |
8966f337 WD |
573 | BRx_PS_64|BRx_MS_SDRAM_P|BRx_V) |
574 | /* 64 Mb, 4 int banks per dev, row start addr bit = A6, 12 row addr lines */ | |
6d0f6bcf | 575 | #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM_SIZE)|\ |
8966f337 WD |
576 | ORxS_BPD_4|ORxS_ROWST_PBI1_A6|ORxS_NUMR_12) |
577 | ||
578 | /* | |
579 | * The 60x Bus SDRAM Mode Register (PDSMR) is set as follows: | |
580 | * | |
581 | * Page Based Interleaving, Refresh Enable, Address Multiplexing where A5 | |
582 | * is output on A16 pin (A6 on A17, and so on), use address pins A14-A16 | |
583 | * as bank select, A7 is output on SDA10 during an ACTIVATE command, | |
584 | * earliest timing for ACTIVATE command after REFRESH command is 6 clocks, | |
585 | * earliest timing for ACTIVATE or REFRESH command after PRECHARGE command | |
586 | * is 2 clocks, earliest timing for READ/WRITE command after ACTIVATE | |
587 | * command is 2 clocks, earliest timing for PRECHARGE after last data | |
588 | * was read is 1 clock, earliest timing for PRECHARGE after last data | |
589 | * was written is 1 clock, CAS Latency is 2. | |
590 | */ | |
591 | ||
6d0f6bcf | 592 | #define CONFIG_SYS_PSDMR (PSDMR_PBI|PSDMR_SDAM_A16_IS_A5|\ |
8966f337 WD |
593 | PSDMR_BSMA_A14_A16|PSDMR_SDA10_PBI1_A7|\ |
594 | PSDMR_RFRC_6_CLK|PSDMR_PRETOACT_2W|\ | |
595 | PSDMR_ACTTORW_2W|PSDMR_LDOTOPRE_1C|\ | |
596 | PSDMR_WRC_1C|PSDMR_CL_2) | |
597 | ||
598 | /* | |
599 | * The 60x bus-assigned SDRAM Refresh Timer (PSRT) (10-31) and the Refresh | |
600 | * Timers Prescale (PTP) value in the Memory Refresh Timer Prescaler Register | |
601 | * (MPTPR) (10-32) must also be set up (it used to be called the Periodic Timer | |
602 | * Prescaler, hence the P instead of the R). The refresh timer period is given | |
603 | * by (note that there was a change in the 8260 UM Errata): | |
604 | * | |
605 | * TimerPeriod = (PSRT + 1) / Fmptc | |
606 | * | |
607 | * where Fmptc is the BusClock divided by PTP. i.e. | |
608 | * | |
609 | * TimerPeriod = (PSRT + 1) / (BusClock / PTP) | |
610 | * | |
611 | * or | |
612 | * | |
613 | * TImerPeriod = (PTP * (PSRT + 1)) / BusClock | |
614 | * | |
615 | * The requirement for the Toshiba TC59SM716FTL-10 is that there must be | |
616 | * 4K refresh cycles every 64 ms. i.e. one refresh cycle every 64000/4096 | |
617 | * = 15.625 usecs. | |
618 | * | |
619 | * So PTP * (PSRT + 1) <= 15.625 * BusClock. At 66.666MHz, PSRT=31 and PTP=32 | |
620 | * appear to be reasonable. | |
621 | */ | |
622 | ||
623 | #ifdef DEBUG | |
6d0f6bcf JCPV |
624 | #define CONFIG_SYS_PSRT 39 |
625 | #define CONFIG_SYS_MPTPR MPTPR_PTP_DIV8 | |
8966f337 | 626 | #else |
6d0f6bcf JCPV |
627 | #define CONFIG_SYS_PSRT 31 |
628 | #define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32 | |
8966f337 WD |
629 | #endif |
630 | ||
631 | /* | |
632 | * Banks 3,4,5 and 6 - FPGA access | |
633 | * | |
634 | * Quotes from the HYMOD IO Board Reference manual: | |
635 | * | |
636 | * "The IO Board is fitted with a Xilinx XCV300E main FPGA. Provision is made | |
637 | * for configuring an optional FPGA on the mezzanine interface. | |
638 | * | |
639 | * Access to the FPGAs may be divided into several catagories: | |
640 | * | |
641 | * 1. Configuration | |
642 | * 2. Register mode access | |
643 | * 3. Port mode access | |
644 | * | |
645 | * The main FPGA is supported for modes 1, 2 and 3. The mezzanine FPGA can be | |
646 | * configured only (mode 1). Consequently there are four access types. | |
647 | * | |
648 | * To improve interface performance and simplify software design, the four | |
649 | * possible access types are separately mapped to different memory banks. | |
650 | * | |
651 | * All are accessed using the local bus." | |
652 | * | |
653 | * Device Mode Memory Bank Machine Port Size Access | |
654 | * | |
655 | * Main Configuration 3 UPMC 8bit R/W | |
656 | * Main Register 4 GPCM 32bit R/W | |
657 | * Main Port 5 UPMB 32bit R/W | |
658 | * Mezzanine Configuration 6 UPMC 8bit W/O | |
659 | * | |
660 | * "Note that mezzanine mode 1 access is write-only." | |
661 | */ | |
662 | ||
663 | /* all the bank sizes must be a power of two, greater or equal to 32768 */ | |
6d0f6bcf | 664 | #define FPGA_MAIN_CFG_BASE (CONFIG_SYS_FPGA_BASE) |
8966f337 WD |
665 | #define FPGA_MAIN_CFG_SIZE 32768 |
666 | #define FPGA_MAIN_REG_BASE (FPGA_MAIN_CFG_BASE + FPGA_MAIN_CFG_SIZE) | |
667 | #define FPGA_MAIN_REG_SIZE 32768 | |
668 | #define FPGA_MAIN_PORT_BASE (FPGA_MAIN_REG_BASE + FPGA_MAIN_REG_SIZE) | |
669 | #define FPGA_MAIN_PORT_SIZE 32768 | |
670 | #define FPGA_MEZZ_CFG_BASE (FPGA_MAIN_PORT_BASE + FPGA_MAIN_PORT_SIZE) | |
671 | #define FPGA_MEZZ_CFG_SIZE 32768 | |
672 | ||
673 | /* 8 bit, read-write, UPMC */ | |
6d0f6bcf | 674 | #define CONFIG_SYS_BR3_PRELIM (FPGA_MAIN_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V) |
8966f337 | 675 | /* up to 32Kbyte, burst inhibit */ |
6d0f6bcf | 676 | #define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(FPGA_MAIN_CFG_SIZE)|ORxU_BI) |
8966f337 WD |
677 | |
678 | /* 32 bit, read-write, GPCM */ | |
6d0f6bcf | 679 | #define CONFIG_SYS_BR4_PRELIM (FPGA_MAIN_REG_BASE|BRx_PS_32|BRx_MS_GPCM_L|BRx_V) |
8966f337 | 680 | /* up to 32Kbyte */ |
6d0f6bcf | 681 | #define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(FPGA_MAIN_REG_SIZE)) |
8966f337 WD |
682 | |
683 | /* 32 bit, read-write, UPMB */ | |
6d0f6bcf | 684 | #define CONFIG_SYS_BR5_PRELIM (FPGA_MAIN_PORT_BASE|BRx_PS_32|BRx_MS_UPMB|BRx_V) |
8966f337 | 685 | /* up to 32Kbyte */ |
6d0f6bcf | 686 | #define CONFIG_SYS_OR5_PRELIM (P2SZ_TO_AM(FPGA_MAIN_PORT_SIZE)|ORxU_BI) |
8966f337 WD |
687 | |
688 | /* 8 bit, write-only, UPMC */ | |
6d0f6bcf | 689 | #define CONFIG_SYS_BR6_PRELIM (FPGA_MEZZ_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V) |
8966f337 | 690 | /* up to 32Kbyte, burst inhibit */ |
6d0f6bcf | 691 | #define CONFIG_SYS_OR6_PRELIM (P2SZ_TO_AM(FPGA_MEZZ_CFG_SIZE)|ORxU_BI) |
8966f337 WD |
692 | |
693 | /*----------------------------------------------------------------------- | |
694 | * MBMR - Machine B Mode 10-27 | |
695 | *----------------------------------------------------------------------- | |
696 | */ | |
6d0f6bcf | 697 | #define CONFIG_SYS_MBMR (MxMR_BSEL|MxMR_OP_NORM) /* XXX - needs more */ |
8966f337 WD |
698 | |
699 | /*----------------------------------------------------------------------- | |
700 | * MCMR - Machine C Mode 10-27 | |
701 | *----------------------------------------------------------------------- | |
702 | */ | |
6d0f6bcf | 703 | #define CONFIG_SYS_MCMR (MxMR_BSEL|MxMR_DSx_2_CYCL) /* XXX - needs more */ |
8966f337 WD |
704 | |
705 | /* | |
706 | * FPGA I/O Port/Bit information | |
707 | */ | |
708 | ||
709 | #define FPGA_MAIN_PROG_PORT IOPIN_PORTA | |
710 | #define FPGA_MAIN_PROG_PIN 4 /* PA4 */ | |
711 | #define FPGA_MAIN_INIT_PORT IOPIN_PORTA | |
712 | #define FPGA_MAIN_INIT_PIN 5 /* PA5 */ | |
713 | #define FPGA_MAIN_DONE_PORT IOPIN_PORTA | |
714 | #define FPGA_MAIN_DONE_PIN 6 /* PA6 */ | |
715 | ||
716 | #define FPGA_MEZZ_PROG_PORT IOPIN_PORTA | |
717 | #define FPGA_MEZZ_PROG_PIN 0 /* PA0 */ | |
718 | #define FPGA_MEZZ_INIT_PORT IOPIN_PORTA | |
719 | #define FPGA_MEZZ_INIT_PIN 1 /* PA1 */ | |
720 | #define FPGA_MEZZ_DONE_PORT IOPIN_PORTA | |
721 | #define FPGA_MEZZ_DONE_PIN 2 /* PA2 */ | |
722 | #define FPGA_MEZZ_ENABLE_PORT IOPIN_PORTA | |
723 | #define FPGA_MEZZ_ENABLE_PIN 3 /* PA3 */ | |
724 | ||
6dd652fa WD |
725 | /* |
726 | * FPGA Interrupt configuration | |
727 | */ | |
728 | #define FPGA_MAIN_IRQ SIU_INT_IRQ2 | |
729 | ||
8966f337 WD |
730 | /* |
731 | * Internal Definitions | |
732 | * | |
733 | * Boot Flags | |
734 | */ | |
735 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ | |
736 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
737 | ||
700a0c64 WD |
738 | /* |
739 | * JFFS2 partitions | |
740 | * | |
741 | */ | |
742 | /* No command line, one static partition, whole device */ | |
68d7d651 | 743 | #undef CONFIG_CMD_MTDPARTS |
700a0c64 WD |
744 | #define CONFIG_JFFS2_DEV "nor0" |
745 | #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF | |
746 | #define CONFIG_JFFS2_PART_OFFSET 0x00000000 | |
747 | ||
748 | /* mtdparts command line support */ | |
749 | /* | |
68d7d651 | 750 | #define CONFIG_CMD_MTDPARTS |
700a0c64 WD |
751 | #define MTDIDS_DEFAULT "" |
752 | #define MTDPARTS_DEFAULT "" | |
753 | */ | |
754 | ||
8966f337 | 755 | #endif /* __CONFIG_H */ |