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029faf3e SR |
1 | /* |
2 | * (C) Copyright 2009-2010 | |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
029faf3e SR |
6 | */ |
7 | ||
8 | /* | |
9 | * icon.h - configuration for Mosaixtech ICON (440SPe) | |
10 | */ | |
11 | ||
12 | #ifndef __CONFIG_H | |
13 | #define __CONFIG_H | |
14 | ||
15 | /* | |
16 | * High Level Configuration Options | |
17 | */ | |
18 | #define CONFIG_ICON 1 /* Board is icon */ | |
029faf3e SR |
19 | #define CONFIG_440 1 /* ... PPC440 family */ |
20 | #define CONFIG_440SPE 1 /* Specifc SPe support */ | |
2ae18241 WD |
21 | |
22 | #define CONFIG_SYS_TEXT_BASE 0xFFFA0000 | |
23 | ||
029faf3e SR |
24 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ |
25 | #define CONFIG_SYS_4xx_RESET_TYPE 0x2 /* use chip reset on this board */ | |
26 | ||
27 | /* | |
28 | * Include common defines/options for all AMCC eval boards | |
29 | */ | |
30 | #define CONFIG_HOSTNAME icon | |
31 | #include "amcc-common.h" | |
32 | ||
029faf3e SR |
33 | #define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r */ |
34 | ||
35 | /* | |
36 | * Base addresses -- Note these are effective addresses where the | |
37 | * actual resources get mapped (not physical addresses) | |
38 | */ | |
39 | #define CONFIG_SYS_FLASH_BASE 0xfc000000 /* later mapped to this addr */ | |
029faf3e SR |
40 | #define CONFIG_SYS_ISRAM_BASE 0x90000000 /* internal SRAM */ |
41 | ||
42 | #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */ | |
43 | #define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ | |
44 | #define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE | |
45 | ||
46 | #define CONFIG_SYS_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */ | |
47 | #define CONFIG_SYS_PCIE_MEMSIZE 0x08000000 /* incr for PCIe port */ | |
48 | #define CONFIG_SYS_PCIE_BASE 0xe0000000 /* PCIe UTL regs */ | |
49 | ||
50 | #define CONFIG_SYS_PCIE0_CFGBASE 0xc0000000 | |
51 | #define CONFIG_SYS_PCIE1_CFGBASE 0xc1000000 | |
52 | #define CONFIG_SYS_PCIE2_CFGBASE 0xc2000000 | |
53 | #define CONFIG_SYS_PCIE0_XCFGBASE 0xc3000000 | |
54 | #define CONFIG_SYS_PCIE1_XCFGBASE 0xc3001000 | |
55 | #define CONFIG_SYS_PCIE2_XCFGBASE 0xc3002000 | |
56 | ||
57 | /* base address of inbound PCIe window */ | |
58 | #define CONFIG_SYS_PCIE_INBOUND_BASE 0x0000000000000000ULL | |
59 | ||
60 | /* System RAM mapped to PCI space */ | |
61 | #define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE | |
62 | #define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE | |
63 | #define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024) | |
64 | ||
65 | #define CONFIG_SYS_ACE_BASE 0xfb000000 /* Xilinx ACE CF */ | |
66 | #define CONFIG_SYS_ACE_BASE_PHYS_H 0x4 | |
67 | #define CONFIG_SYS_ACE_BASE_PHYS_L 0xfe000000 | |
68 | ||
69 | #define CONFIG_SYS_FLASH_SIZE (64 << 20) | |
70 | #define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space */ | |
71 | #define CONFIG_SYS_FLASH_BASE_PHYS_H 0x4 | |
72 | #define CONFIG_SYS_FLASH_BASE_PHYS_L 0xEC000000 | |
73 | #define CONFIG_SYS_FLASH_BASE_PHYS (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) | \ | |
74 | (u64)CONFIG_SYS_FLASH_BASE_PHYS_L) | |
75 | ||
76 | /* | |
77 | * Initial RAM & stack pointer (placed in internal SRAM) | |
78 | */ | |
79 | #define CONFIG_SYS_TEMP_STACK_OCM 1 | |
80 | #define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE | |
81 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Init RAM */ | |
553f0982 | 82 | #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* size of used area */ |
029faf3e | 83 | |
553f0982 | 84 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ |
25ddd1fb | 85 | GENERATED_GBL_DATA_SIZE) |
800eb096 | 86 | #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) |
029faf3e SR |
87 | |
88 | /* | |
89 | * Serial Port | |
90 | */ | |
550650dd | 91 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
029faf3e SR |
92 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK |
93 | ||
94 | /* | |
95 | * DDR2 SDRAM | |
96 | */ | |
97 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ | |
98 | #define SPD_EEPROM_ADDRESS { 0x51 } /* SPD I2C SPD addresses */ | |
99 | #define CONFIG_DDR_ECC /* with ECC support */ | |
100 | #define CONFIG_DDR_RQDC_FIXED 0x80000038 /* fixed value for RQDC */ | |
101 | ||
102 | /* | |
103 | * I2C | |
104 | */ | |
880540de | 105 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000 |
029faf3e | 106 | |
029faf3e SR |
107 | #define CONFIG_SYS_SPD_BUS_NUM 0 /* The I2C bus for SPD */ |
108 | ||
029faf3e SR |
109 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 |
110 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
111 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
112 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
113 | ||
114 | /* I2C bootstrap EEPROM */ | |
115 | #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x50 | |
116 | #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0 | |
117 | #define CONFIG_4xx_CONFIG_BLOCKSIZE 8 | |
118 | ||
119 | /* I2C RTC */ | |
120 | #define CONFIG_RTC_M41T11 | |
121 | #define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */ | |
122 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
123 | #define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with linux */ | |
124 | ||
86caca1c AG |
125 | /* |
126 | * Video options | |
127 | */ | |
86caca1c AG |
128 | |
129 | #ifdef CONFIG_VIDEO | |
130 | #define CONFIG_VIDEO_SM501 | |
131 | #define CONFIG_VIDEO_SM501_32BPP | |
132 | #define CONFIG_VIDEO_SM501_PCI | |
133 | #define VIDEO_FB_LITTLE_ENDIAN | |
86caca1c | 134 | #define CONFIG_VIDEO_LOGO |
86caca1c AG |
135 | #define CONFIG_VIDEO_BMP_RLE8 |
136 | #define CONFIG_SPLASH_SCREEN | |
137 | #define CFG_CONSOLE_IS_IN_ENV | |
138 | #endif | |
139 | ||
029faf3e SR |
140 | /* |
141 | * Environment | |
142 | */ | |
143 | #define CONFIG_ENV_IS_IN_FLASH 1 /* Environment uses flash */ | |
144 | ||
145 | /* | |
146 | * Default environment variables | |
147 | */ | |
148 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
149 | CONFIG_AMCC_DEF_ENV \ | |
150 | CONFIG_AMCC_DEF_ENV_POWERPC \ | |
151 | CONFIG_AMCC_DEF_ENV_NOR_UPD \ | |
152 | "kernel_addr=fc000000\0" \ | |
153 | "fdt_addr=fc1e0000\0" \ | |
154 | "ramdisk_addr=fc200000\0" \ | |
155 | "pciconfighost=1\0" \ | |
156 | "pcie_mode=RP:RP:RP\0" \ | |
157 | "" | |
158 | ||
159 | /* | |
160 | * Commands additional to the ones defined in amcc-common.h | |
161 | */ | |
162 | #define CONFIG_CMD_CHIP_CONFIG | |
163 | #define CONFIG_CMD_DATE | |
029faf3e SR |
164 | #define CONFIG_CMD_PCI |
165 | #define CONFIG_CMD_SDRAM | |
86caca1c AG |
166 | #ifdef CONFIG_VIDEO |
167 | #define CONFIG_CMD_BMP | |
168 | #endif | |
029faf3e SR |
169 | |
170 | #define CONFIG_IBM_EMAC4_V4 /* 440SPe has this EMAC version */ | |
171 | #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ | |
172 | #define CONFIG_HAS_ETH0 | |
173 | #define CONFIG_PHY_RESET /* reset phy upon startup */ | |
174 | #define CONFIG_PHY_RESET_DELAY 1000 | |
175 | #define CONFIG_CIS8201_PHY /* Enable RGMII mode for Cicada phy */ | |
176 | #define CONFIG_PHY_GIGE /* Include GbE speed/duplex det. */ | |
177 | ||
178 | /* | |
179 | * FLASH related | |
180 | */ | |
181 | #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ | |
182 | #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ | |
183 | #define CONFIG_SYS_FLASH_CFI_AMD_RESET /* Use AMD (Spansion) reset cmd */ | |
184 | #define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* use status poll method */ | |
185 | ||
186 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
187 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of banks */ | |
188 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors*/ | |
189 | ||
190 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ | |
191 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ | |
192 | ||
193 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */ | |
194 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector */ | |
195 | ||
196 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ | |
197 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) | |
198 | #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Env Sector */ | |
199 | ||
200 | /* Address and size of Redundant Environment Sector */ | |
201 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE) | |
202 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
203 | ||
204 | /* | |
205 | * PCI stuff | |
206 | */ | |
207 | /* General PCI */ | |
842033e6 | 208 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
029faf3e SR |
209 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
210 | #define CONFIG_PCI_CONFIG_HOST_BRIDGE | |
211 | #define CONFIG_PCI_BOOTDELAY 1000 /* enable pci bootdelay variable*/ | |
212 | ||
213 | /* Board-specific PCI */ | |
214 | #define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */ | |
215 | #undef CONFIG_SYS_PCI_MASTER_INIT | |
216 | ||
217 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ | |
218 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ | |
219 | ||
220 | /* | |
221 | * Xilinx System ACE support | |
222 | */ | |
223 | #define CONFIG_SYSTEMACE /* Enable SystemACE support */ | |
224 | #define CONFIG_SYS_SYSTEMACE_WIDTH 16 /* Data bus width is 16 */ | |
225 | #define CONFIG_SYS_SYSTEMACE_BASE CONFIG_SYS_ACE_BASE | |
029faf3e SR |
226 | |
227 | /* | |
228 | * External Bus Controller (EBC) Setup | |
229 | */ | |
230 | ||
231 | /* Memory Bank 0 (Flash) initialization */ | |
232 | #define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \ | |
233 | EBC_BXAP_TWT_ENCODE(7) | \ | |
234 | EBC_BXAP_BCE_DISABLE | \ | |
235 | EBC_BXAP_BCT_2TRANS | \ | |
236 | EBC_BXAP_CSN_ENCODE(0) | \ | |
237 | EBC_BXAP_OEN_ENCODE(0) | \ | |
238 | EBC_BXAP_WBN_ENCODE(0) | \ | |
239 | EBC_BXAP_WBF_ENCODE(0) | \ | |
240 | EBC_BXAP_TH_ENCODE(0) | \ | |
241 | EBC_BXAP_RE_DISABLED | \ | |
242 | EBC_BXAP_SOR_DELAYED | \ | |
243 | EBC_BXAP_BEM_WRITEONLY | \ | |
244 | EBC_BXAP_PEN_DISABLED) | |
245 | #define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \ | |
246 | EBC_BXCR_BS_64MB | \ | |
247 | EBC_BXCR_BU_RW | \ | |
248 | EBC_BXCR_BW_16BIT) | |
249 | ||
250 | /* Memory Bank 1 (Xilinx System ACE controller) initialization */ | |
251 | #define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \ | |
252 | EBC_BXAP_TWT_ENCODE(4) | \ | |
253 | EBC_BXAP_BCE_DISABLE | \ | |
254 | EBC_BXAP_BCT_2TRANS | \ | |
255 | EBC_BXAP_CSN_ENCODE(0) | \ | |
256 | EBC_BXAP_OEN_ENCODE(0) | \ | |
257 | EBC_BXAP_WBN_ENCODE(0) | \ | |
258 | EBC_BXAP_WBF_ENCODE(0) | \ | |
259 | EBC_BXAP_TH_ENCODE(0) | \ | |
260 | EBC_BXAP_RE_DISABLED | \ | |
261 | EBC_BXAP_SOR_NONDELAYED | \ | |
262 | EBC_BXAP_BEM_WRITEONLY | \ | |
263 | EBC_BXAP_PEN_DISABLED) | |
264 | #define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_ACE_BASE_PHYS_L) | \ | |
265 | EBC_BXCR_BS_1MB | \ | |
266 | EBC_BXCR_BU_RW | \ | |
267 | EBC_BXCR_BW_16BIT) | |
268 | ||
269 | /* | |
270 | * Initialize EBC CONFIG - | |
271 | * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC | |
272 | * default value : 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000 | |
273 | */ | |
274 | #define CONFIG_SYS_EBC_CFG (EBC_CFG_LE_UNLOCK | \ | |
275 | EBC_CFG_PTD_ENABLE | \ | |
276 | EBC_CFG_RTC_16PERCLK | \ | |
277 | EBC_CFG_ATC_PREVIOUS | \ | |
278 | EBC_CFG_DTC_PREVIOUS | \ | |
279 | EBC_CFG_CTC_PREVIOUS | \ | |
280 | EBC_CFG_OEO_PREVIOUS | \ | |
281 | EBC_CFG_EMC_DEFAULT | \ | |
282 | EBC_CFG_PME_DISABLE | \ | |
283 | EBC_CFG_PR_16) | |
284 | ||
285 | /* | |
286 | * GPIO Setup | |
287 | */ | |
288 | #define CONFIG_SYS_GPIO_PCIE_PRESENT0 17 | |
289 | #define CONFIG_SYS_GPIO_PCIE_PRESENT1 21 | |
290 | #define CONFIG_SYS_GPIO_PCIE_PRESENT2 23 | |
291 | #define CONFIG_SYS_GPIO_RS232_FORCEOFF 30 | |
292 | ||
293 | #define CONFIG_SYS_PFC0 (GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT0) | \ | |
294 | GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT1) | \ | |
295 | GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT2) | \ | |
296 | GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)) | |
297 | #define CONFIG_SYS_GPIO_OR GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF) | |
298 | #define CONFIG_SYS_GPIO_TCR GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF) | |
299 | #define CONFIG_SYS_GPIO_ODR 0 | |
300 | ||
301 | #endif /* __CONFIG_H */ |