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2605e90b HS |
1 | /* |
2 | * (C) Copyright 2007 | |
3 | * Heiko Schocher, DENX Software Engineering, hs@denx.de. | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
2605e90b HS |
6 | */ |
7 | ||
8 | #ifndef __CONFIG_H | |
9 | #define __CONFIG_H | |
10 | ||
11 | /* | |
12 | * High Level Configuration Options | |
13 | * (easy to change) | |
14 | */ | |
15 | ||
b2a6dfe4 | 16 | #define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ |
2605e90b HS |
17 | #define CONFIG_JUPITER 1 /* ... on Jupiter board */ |
18 | ||
2ae18241 WD |
19 | /* |
20 | * Valid values for CONFIG_SYS_TEXT_BASE are: | |
21 | * 0xFFF00000 boot high (standard configuration) | |
22 | * 0x00100000 boot from RAM (for testing only) | |
23 | */ | |
24 | #ifndef CONFIG_SYS_TEXT_BASE | |
25 | #define CONFIG_SYS_TEXT_BASE 0xFFF00000 | |
26 | #endif | |
27 | ||
6d0f6bcf | 28 | #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ |
2605e90b HS |
29 | |
30 | #define CONFIG_BOARD_EARLY_INIT_R 1 | |
31 | #define CONFIG_BOARD_EARLY_INIT_F 1 | |
32 | ||
31d82672 BB |
33 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
34 | ||
2605e90b HS |
35 | /* |
36 | * Serial console configuration | |
37 | */ | |
38 | #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ | |
39 | #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ | |
6d0f6bcf | 40 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
2605e90b HS |
41 | |
42 | /* | |
43 | * PCI Mapping: | |
44 | * 0x40000000 - 0x4fffffff - PCI Memory | |
45 | * 0x50000000 - 0x50ffffff - PCI IO Space | |
46 | */ | |
769104c9 | 47 | /*#define CONFIG_PCI */ |
2605e90b HS |
48 | |
49 | #if defined(CONFIG_PCI) | |
50 | #define CONFIG_PCI_PNP 1 | |
51 | #define CONFIG_PCI_SCAN_SHOW 1 | |
f33fca22 | 52 | #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 |
2605e90b HS |
53 | |
54 | #define CONFIG_PCI_MEM_BUS 0x40000000 | |
55 | #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS | |
56 | #define CONFIG_PCI_MEM_SIZE 0x10000000 | |
57 | ||
58 | #define CONFIG_PCI_IO_BUS 0x50000000 | |
59 | #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS | |
60 | #define CONFIG_PCI_IO_SIZE 0x01000000 | |
2605e90b HS |
61 | #endif |
62 | ||
6d0f6bcf | 63 | #define CONFIG_SYS_XLB_PIPELINING 1 |
2605e90b | 64 | |
2605e90b | 65 | #define CONFIG_MII 1 |
6d0f6bcf | 66 | #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ |
2605e90b HS |
67 | |
68 | /* Partitions */ | |
69 | #define CONFIG_MAC_PARTITION | |
70 | #define CONFIG_DOS_PARTITION | |
71 | #define CONFIG_ISO_PARTITION | |
72 | ||
73 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ | |
74 | ||
bc234c12 | 75 | |
7f5c0157 JL |
76 | /* |
77 | * BOOTP options | |
78 | */ | |
79 | #define CONFIG_BOOTP_BOOTFILESIZE | |
80 | #define CONFIG_BOOTP_BOOTPATH | |
81 | #define CONFIG_BOOTP_GATEWAY | |
82 | #define CONFIG_BOOTP_HOSTNAME | |
83 | ||
84 | ||
2605e90b | 85 | /* |
bc234c12 | 86 | * Command line configuration. |
2605e90b | 87 | */ |
bc234c12 JL |
88 | #include <config_cmd_default.h> |
89 | ||
90 | #define CONFIG_CMD_NFS | |
91 | #define CONFIG_CMD_SNTP | |
2605e90b | 92 | |
7f5c0157 JL |
93 | #if defined(CONFIG_PCI) |
94 | #define CODFIG_CMD_PCI | |
95 | #endif | |
96 | ||
2605e90b HS |
97 | |
98 | /* | |
99 | * Autobooting | |
100 | */ | |
101 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
102 | ||
103 | #define CONFIG_PREBOOT "echo;" \ | |
32bf3d14 | 104 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
2605e90b HS |
105 | "echo" |
106 | ||
107 | #undef CONFIG_BOOTARGS | |
108 | ||
109 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
110 | "netdev=eth0\0" \ | |
111 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
112 | "nfsroot=${serverip}:${rootpath}\0" \ | |
113 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
114 | "addip=setenv bootargs ${bootargs} " \ | |
115 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
116 | ":${hostname}:${netdev}:off panic=1\0" \ | |
a7090b99 | 117 | "flash_nfs=run nfsargs addip addcons;" \ |
2605e90b HS |
118 | "bootm ${kernel_addr}\0" \ |
119 | "flash_self=run ramargs addip;" \ | |
120 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ | |
a7090b99 | 121 | "addcons=setenv bootargs ${bootargs} console=${contyp}," \ |
8502e30a HS |
122 | "${baudrate}\0" \ |
123 | "contyp=ttyS0\0" \ | |
a7090b99 | 124 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcons;" \ |
8502e30a HS |
125 | "bootm\0" \ |
126 | "rootpath=/opt/eldk/ppc_6xx\0" \ | |
2605e90b HS |
127 | "bootfile=/tftpboot/jupiter/uImage\0" \ |
128 | "" | |
129 | ||
130 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
131 | ||
132 | /* | |
133 | * IPB Bus clocking configuration. | |
134 | */ | |
6d0f6bcf | 135 | #undef CONFIG_SYS_IPBSPEED_133 /* define for 133MHz speed */ |
2605e90b HS |
136 | |
137 | #if 0 | |
138 | /* pass open firmware flat tree */ | |
cf2817a8 | 139 | #define CONFIG_OF_LIBFDT 1 |
2605e90b HS |
140 | #define CONFIG_OF_BOARD_SETUP 1 |
141 | ||
2605e90b HS |
142 | #define OF_CPU "PowerPC,5200@0" |
143 | #define OF_SOC "soc5200@f0000000" | |
144 | #define OF_TBCLK (bd->bi_busfreq / 8) | |
145 | #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" | |
146 | #endif | |
147 | ||
148 | #if 0 | |
149 | /* | |
150 | * I2C configuration | |
151 | */ | |
152 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
6d0f6bcf | 153 | #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ |
2605e90b | 154 | |
6d0f6bcf JCPV |
155 | #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ |
156 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
2605e90b HS |
157 | |
158 | /* | |
159 | * EEPROM configuration | |
160 | */ | |
6d0f6bcf JCPV |
161 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ |
162 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
163 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
164 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70 | |
2605e90b HS |
165 | #endif |
166 | ||
167 | /* | |
168 | * Flash configuration | |
169 | */ | |
6d0f6bcf JCPV |
170 | #define CONFIG_SYS_FLASH_BASE 0xFF000000 |
171 | #define CONFIG_SYS_FLASH_SIZE 0x01000000 | |
2605e90b | 172 | |
6d0f6bcf | 173 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ |
2605e90b | 174 | |
14d0a02a | 175 | #define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE + 0x40000) /* third sector */ |
2605e90b | 176 | |
6d0f6bcf JCPV |
177 | #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ |
178 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ | |
2605e90b | 179 | |
6d0f6bcf | 180 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ |
2605e90b | 181 | |
00b1883a | 182 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
183 | #define CONFIG_SYS_FLASH_CFI |
184 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
185 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT | |
186 | #define CONFIG_SYS_UPDATE_FLASH_SIZE 1 | |
187 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 | |
2605e90b HS |
188 | |
189 | /* | |
190 | * Environment settings | |
191 | */ | |
5a1aceb0 | 192 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
193 | #define CONFIG_ENV_SIZE 0x20000 |
194 | #define CONFIG_ENV_SECT_SIZE 0x20000 | |
2605e90b HS |
195 | #define CONFIG_ENV_OVERWRITE 1 |
196 | ||
8502e30a | 197 | /* Address and size of Redundant Environment Sector */ |
0e8d1586 JCPV |
198 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
199 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
8502e30a | 200 | |
2605e90b HS |
201 | /* |
202 | * Memory map | |
203 | */ | |
6d0f6bcf JCPV |
204 | #define CONFIG_SYS_MBAR 0xF0000000 |
205 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
206 | #define CONFIG_SYS_DEFAULT_MBAR 0x80000000 | |
2605e90b HS |
207 | |
208 | /* Use SRAM until RAM will be available */ | |
6d0f6bcf | 209 | #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM |
553f0982 | 210 | #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ |
2605e90b HS |
211 | |
212 | ||
25ddd1fb | 213 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 214 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
2605e90b | 215 | |
14d0a02a | 216 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf JCPV |
217 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
218 | # define CONFIG_SYS_RAMBOOT 1 | |
2605e90b HS |
219 | #endif |
220 | ||
6d0f6bcf JCPV |
221 | #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
222 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
223 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
2605e90b HS |
224 | |
225 | /* | |
226 | * Ethernet configuration | |
227 | */ | |
228 | #define CONFIG_MPC5xxx_FEC 1 | |
86321fc1 | 229 | #define CONFIG_MPC5xxx_FEC_MII100 |
2605e90b | 230 | /* |
86321fc1 | 231 | * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb |
2605e90b | 232 | */ |
86321fc1 | 233 | /* #define CONFIG_MPC5xxx_FEC_MII10 */ |
2605e90b HS |
234 | #define CONFIG_PHY_ADDR 0x00 |
235 | ||
236 | /* | |
237 | * GPIO configuration | |
238 | */ | |
6d0f6bcf | 239 | #define CONFIG_SYS_GPS_PORT_CONFIG 0x10000004 |
2605e90b HS |
240 | |
241 | /* | |
242 | * Miscellaneous configurable options | |
243 | */ | |
6d0f6bcf | 244 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
8502e30a HS |
245 | |
246 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
6d0f6bcf | 247 | #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ |
bc234c12 | 248 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 249 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
2605e90b | 250 | #else |
6d0f6bcf | 251 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
2605e90b | 252 | #endif |
6d0f6bcf JCPV |
253 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
254 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
255 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
2605e90b | 256 | |
6d0f6bcf JCPV |
257 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
258 | #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ | |
259 | #define CONFIG_SYS_ALT_MEMTEST 1 | |
2605e90b | 260 | |
6d0f6bcf | 261 | #define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */ |
2605e90b | 262 | |
6d0f6bcf | 263 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
bc234c12 | 264 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 265 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
bc234c12 JL |
266 | #endif |
267 | ||
2605e90b HS |
268 | /* |
269 | * Various low-level settings | |
270 | */ | |
6d0f6bcf JCPV |
271 | #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI |
272 | #define CONFIG_SYS_HID0_FINAL HID0_ICE | |
2605e90b | 273 | |
6d0f6bcf JCPV |
274 | #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE |
275 | #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE | |
276 | #define CONFIG_SYS_BOOTCS_CFG 0x00047801 | |
277 | #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE | |
278 | #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE | |
2605e90b | 279 | |
6d0f6bcf JCPV |
280 | #define CONFIG_SYS_CS_BURST 0x00000000 |
281 | #define CONFIG_SYS_CS_DEADCYCLE 0x33333333 | |
2605e90b | 282 | |
6d0f6bcf | 283 | #define CONFIG_SYS_RESET_ADDRESS 0xff000000 |
2605e90b HS |
284 | |
285 | #endif /* __CONFIG_H */ |