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2605e90b HS |
1 | /* |
2 | * (C) Copyright 2007 | |
3 | * Heiko Schocher, DENX Software Engineering, hs@denx.de. | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
2605e90b HS |
6 | */ |
7 | ||
8 | #ifndef __CONFIG_H | |
9 | #define __CONFIG_H | |
10 | ||
11 | /* | |
12 | * High Level Configuration Options | |
13 | * (easy to change) | |
14 | */ | |
15 | ||
b2a6dfe4 | 16 | #define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ |
2605e90b | 17 | #define CONFIG_JUPITER 1 /* ... on Jupiter board */ |
50301a5a | 18 | #define CONFIG_DISPLAY_BOARDINFO |
2605e90b | 19 | |
2ae18241 WD |
20 | /* |
21 | * Valid values for CONFIG_SYS_TEXT_BASE are: | |
22 | * 0xFFF00000 boot high (standard configuration) | |
23 | * 0x00100000 boot from RAM (for testing only) | |
24 | */ | |
25 | #ifndef CONFIG_SYS_TEXT_BASE | |
26 | #define CONFIG_SYS_TEXT_BASE 0xFFF00000 | |
27 | #endif | |
28 | ||
6d0f6bcf | 29 | #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ |
2605e90b HS |
30 | |
31 | #define CONFIG_BOARD_EARLY_INIT_R 1 | |
32 | #define CONFIG_BOARD_EARLY_INIT_F 1 | |
33 | ||
31d82672 BB |
34 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
35 | ||
2605e90b HS |
36 | /* |
37 | * Serial console configuration | |
38 | */ | |
39 | #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ | |
40 | #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ | |
6d0f6bcf | 41 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
2605e90b HS |
42 | |
43 | /* | |
44 | * PCI Mapping: | |
45 | * 0x40000000 - 0x4fffffff - PCI Memory | |
46 | * 0x50000000 - 0x50ffffff - PCI IO Space | |
47 | */ | |
769104c9 | 48 | /*#define CONFIG_PCI */ |
2605e90b HS |
49 | |
50 | #if defined(CONFIG_PCI) | |
51 | #define CONFIG_PCI_PNP 1 | |
52 | #define CONFIG_PCI_SCAN_SHOW 1 | |
f33fca22 | 53 | #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 |
2605e90b HS |
54 | |
55 | #define CONFIG_PCI_MEM_BUS 0x40000000 | |
56 | #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS | |
57 | #define CONFIG_PCI_MEM_SIZE 0x10000000 | |
58 | ||
59 | #define CONFIG_PCI_IO_BUS 0x50000000 | |
60 | #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS | |
61 | #define CONFIG_PCI_IO_SIZE 0x01000000 | |
2605e90b HS |
62 | #endif |
63 | ||
6d0f6bcf | 64 | #define CONFIG_SYS_XLB_PIPELINING 1 |
2605e90b | 65 | |
2605e90b | 66 | #define CONFIG_MII 1 |
6d0f6bcf | 67 | #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ |
2605e90b HS |
68 | |
69 | /* Partitions */ | |
70 | #define CONFIG_MAC_PARTITION | |
71 | #define CONFIG_DOS_PARTITION | |
72 | #define CONFIG_ISO_PARTITION | |
73 | ||
74 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ | |
75 | ||
bc234c12 | 76 | |
7f5c0157 JL |
77 | /* |
78 | * BOOTP options | |
79 | */ | |
80 | #define CONFIG_BOOTP_BOOTFILESIZE | |
81 | #define CONFIG_BOOTP_BOOTPATH | |
82 | #define CONFIG_BOOTP_GATEWAY | |
83 | #define CONFIG_BOOTP_HOSTNAME | |
84 | ||
85 | ||
2605e90b | 86 | /* |
bc234c12 | 87 | * Command line configuration. |
2605e90b | 88 | */ |
bc234c12 | 89 | #define CONFIG_CMD_SNTP |
2605e90b | 90 | |
7f5c0157 JL |
91 | #if defined(CONFIG_PCI) |
92 | #define CODFIG_CMD_PCI | |
93 | #endif | |
94 | ||
2605e90b HS |
95 | |
96 | /* | |
97 | * Autobooting | |
98 | */ | |
99 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
100 | ||
101 | #define CONFIG_PREBOOT "echo;" \ | |
32bf3d14 | 102 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
2605e90b HS |
103 | "echo" |
104 | ||
105 | #undef CONFIG_BOOTARGS | |
106 | ||
107 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
108 | "netdev=eth0\0" \ | |
109 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
110 | "nfsroot=${serverip}:${rootpath}\0" \ | |
111 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
112 | "addip=setenv bootargs ${bootargs} " \ | |
113 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
114 | ":${hostname}:${netdev}:off panic=1\0" \ | |
a7090b99 | 115 | "flash_nfs=run nfsargs addip addcons;" \ |
2605e90b HS |
116 | "bootm ${kernel_addr}\0" \ |
117 | "flash_self=run ramargs addip;" \ | |
118 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ | |
a7090b99 | 119 | "addcons=setenv bootargs ${bootargs} console=${contyp}," \ |
8502e30a HS |
120 | "${baudrate}\0" \ |
121 | "contyp=ttyS0\0" \ | |
a7090b99 | 122 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcons;" \ |
8502e30a HS |
123 | "bootm\0" \ |
124 | "rootpath=/opt/eldk/ppc_6xx\0" \ | |
2605e90b HS |
125 | "bootfile=/tftpboot/jupiter/uImage\0" \ |
126 | "" | |
127 | ||
128 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
129 | ||
130 | /* | |
131 | * IPB Bus clocking configuration. | |
132 | */ | |
6d0f6bcf | 133 | #undef CONFIG_SYS_IPBSPEED_133 /* define for 133MHz speed */ |
2605e90b HS |
134 | |
135 | #if 0 | |
136 | /* pass open firmware flat tree */ | |
cf2817a8 | 137 | #define CONFIG_OF_LIBFDT 1 |
2605e90b HS |
138 | #define CONFIG_OF_BOARD_SETUP 1 |
139 | ||
2605e90b HS |
140 | #define OF_CPU "PowerPC,5200@0" |
141 | #define OF_SOC "soc5200@f0000000" | |
142 | #define OF_TBCLK (bd->bi_busfreq / 8) | |
143 | #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" | |
144 | #endif | |
145 | ||
146 | #if 0 | |
147 | /* | |
148 | * I2C configuration | |
149 | */ | |
150 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
6d0f6bcf | 151 | #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ |
2605e90b | 152 | |
6d0f6bcf JCPV |
153 | #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ |
154 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
2605e90b HS |
155 | |
156 | /* | |
157 | * EEPROM configuration | |
158 | */ | |
6d0f6bcf JCPV |
159 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ |
160 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
161 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
162 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70 | |
2605e90b HS |
163 | #endif |
164 | ||
165 | /* | |
166 | * Flash configuration | |
167 | */ | |
6d0f6bcf JCPV |
168 | #define CONFIG_SYS_FLASH_BASE 0xFF000000 |
169 | #define CONFIG_SYS_FLASH_SIZE 0x01000000 | |
2605e90b | 170 | |
6d0f6bcf | 171 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ |
2605e90b | 172 | |
14d0a02a | 173 | #define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE + 0x40000) /* third sector */ |
2605e90b | 174 | |
6d0f6bcf JCPV |
175 | #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ |
176 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ | |
2605e90b | 177 | |
6d0f6bcf | 178 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ |
2605e90b | 179 | |
00b1883a | 180 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
181 | #define CONFIG_SYS_FLASH_CFI |
182 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
183 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT | |
184 | #define CONFIG_SYS_UPDATE_FLASH_SIZE 1 | |
185 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 | |
2605e90b HS |
186 | |
187 | /* | |
188 | * Environment settings | |
189 | */ | |
5a1aceb0 | 190 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
191 | #define CONFIG_ENV_SIZE 0x20000 |
192 | #define CONFIG_ENV_SECT_SIZE 0x20000 | |
2605e90b HS |
193 | #define CONFIG_ENV_OVERWRITE 1 |
194 | ||
8502e30a | 195 | /* Address and size of Redundant Environment Sector */ |
0e8d1586 JCPV |
196 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
197 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
8502e30a | 198 | |
2605e90b HS |
199 | /* |
200 | * Memory map | |
201 | */ | |
6d0f6bcf JCPV |
202 | #define CONFIG_SYS_MBAR 0xF0000000 |
203 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
204 | #define CONFIG_SYS_DEFAULT_MBAR 0x80000000 | |
2605e90b HS |
205 | |
206 | /* Use SRAM until RAM will be available */ | |
6d0f6bcf | 207 | #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM |
553f0982 | 208 | #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ |
2605e90b HS |
209 | |
210 | ||
25ddd1fb | 211 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 212 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
2605e90b | 213 | |
14d0a02a | 214 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf JCPV |
215 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
216 | # define CONFIG_SYS_RAMBOOT 1 | |
2605e90b HS |
217 | #endif |
218 | ||
6d0f6bcf JCPV |
219 | #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
220 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
221 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
2605e90b HS |
222 | |
223 | /* | |
224 | * Ethernet configuration | |
225 | */ | |
226 | #define CONFIG_MPC5xxx_FEC 1 | |
86321fc1 | 227 | #define CONFIG_MPC5xxx_FEC_MII100 |
2605e90b | 228 | /* |
86321fc1 | 229 | * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb |
2605e90b | 230 | */ |
86321fc1 | 231 | /* #define CONFIG_MPC5xxx_FEC_MII10 */ |
2605e90b HS |
232 | #define CONFIG_PHY_ADDR 0x00 |
233 | ||
234 | /* | |
235 | * GPIO configuration | |
236 | */ | |
6d0f6bcf | 237 | #define CONFIG_SYS_GPS_PORT_CONFIG 0x10000004 |
2605e90b HS |
238 | |
239 | /* | |
240 | * Miscellaneous configurable options | |
241 | */ | |
6d0f6bcf | 242 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
8502e30a HS |
243 | |
244 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
6d0f6bcf | 245 | #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ |
bc234c12 | 246 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 247 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
2605e90b | 248 | #else |
6d0f6bcf | 249 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
2605e90b | 250 | #endif |
6d0f6bcf JCPV |
251 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
252 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
253 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
2605e90b | 254 | |
6d0f6bcf JCPV |
255 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
256 | #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ | |
257 | #define CONFIG_SYS_ALT_MEMTEST 1 | |
2605e90b | 258 | |
6d0f6bcf | 259 | #define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */ |
2605e90b | 260 | |
6d0f6bcf | 261 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
bc234c12 | 262 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 263 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
bc234c12 JL |
264 | #endif |
265 | ||
2605e90b HS |
266 | /* |
267 | * Various low-level settings | |
268 | */ | |
6d0f6bcf JCPV |
269 | #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI |
270 | #define CONFIG_SYS_HID0_FINAL HID0_ICE | |
2605e90b | 271 | |
6d0f6bcf JCPV |
272 | #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE |
273 | #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE | |
274 | #define CONFIG_SYS_BOOTCS_CFG 0x00047801 | |
275 | #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE | |
276 | #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE | |
2605e90b | 277 | |
6d0f6bcf JCPV |
278 | #define CONFIG_SYS_CS_BURST 0x00000000 |
279 | #define CONFIG_SYS_CS_DEADCYCLE 0x33333333 | |
2605e90b | 280 | |
6d0f6bcf | 281 | #define CONFIG_SYS_RESET_ADDRESS 0xff000000 |
2605e90b HS |
282 | |
283 | #endif /* __CONFIG_H */ |