[people/ms/u-boot.git] / include / configs / katmai.h

/*
 * (C) Copyright 2007
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/************************************************************************
 * katmai.h - configuration for AMCC Katmai (440SPe)
 ***********************************************************************/

#ifndef __CONFIG_H
#define __CONFIG_H

/*-----------------------------------------------------------------------
 * High Level Configuration Options
 *----------------------------------------------------------------------*/
#define CONFIG_KATMAI			1	/* Board is Katmai	*/
#define CONFIG_4xx			1	/* ... PPC4xx family	*/
#define CONFIG_440			1	/* ... PPC440 family	*/
#define CONFIG_440SPE			1	/* Specifc SPe support	*/
#define CONFIG_440SPE_REVA		1	/* Support old Rev A.	*/
#define CONFIG_SYS_CLK_FREQ	33333333	/* external freq to pll	*/
#define CONFIG_SYS_4xx_RESET_TYPE	0x2	/* use chip reset on this board	*/

#define	CONFIG_SYS_TEXT_BASE	0xFFFA0000

/*
 * Enable this board for more than 2GB of SDRAM
 */
#define CONFIG_PHYS_64BIT
#define	CONFIG_VERY_BIG_RAM

/*
 * Include common defines/options for all AMCC eval boards
 */
#define CONFIG_HOSTNAME		katmai
#include "amcc-common.h"

#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_pre_init		*/
#undef  CONFIG_SHOW_BOOT_PROGRESS

/*-----------------------------------------------------------------------
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_FLASH_BASE		0xff000000	/* start of FLASH	*/
#define CONFIG_SYS_ISRAM_BASE		0x90000000	/* internal SRAM	*/

#define CONFIG_SYS_PCI_MEMBASE		0x80000000	/* mapped PCI memory	*/
#define CONFIG_SYS_PCI_BASE		0xd0000000	/* internal PCI regs	*/
#define CONFIG_SYS_PCI_TARGBASE	CONFIG_SYS_PCI_MEMBASE

#define CONFIG_SYS_PCIE_MEMBASE	0xb0000000	/* mapped PCIe memory	*/
#define CONFIG_SYS_PCIE_MEMSIZE	0x08000000	/* smallest incr for PCIe port */
#define CONFIG_SYS_PCIE_BASE		0xe0000000	/* PCIe UTL regs */

#define CONFIG_SYS_PCIE0_CFGBASE	0xc0000000
#define CONFIG_SYS_PCIE1_CFGBASE	0xc1000000
#define CONFIG_SYS_PCIE2_CFGBASE	0xc2000000
#define CONFIG_SYS_PCIE0_XCFGBASE	0xc3000000
#define CONFIG_SYS_PCIE1_XCFGBASE	0xc3001000
#define CONFIG_SYS_PCIE2_XCFGBASE	0xc3002000

/* base address of inbound PCIe window */
#define CONFIG_SYS_PCIE_INBOUND_BASE	0x0000000000000000ULL

/* System RAM mapped to PCI space */
#define CONFIG_PCI_SYS_MEM_BUS	CONFIG_SYS_SDRAM_BASE
#define CONFIG_PCI_SYS_MEM_PHYS	CONFIG_SYS_SDRAM_BASE
#define CONFIG_PCI_SYS_MEM_SIZE	(1024 * 1024 * 1024)

#define CONFIG_SYS_ACE_BASE		0xfe000000	/* Xilinx ACE controller - Compact Flash */

/*-----------------------------------------------------------------------
 * Initial RAM & stack pointer (placed in internal SRAM)
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_TEMP_STACK_OCM	1
#define CONFIG_SYS_OCM_DATA_ADDR	CONFIG_SYS_ISRAM_BASE
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_ISRAM_BASE	/* Initial RAM address	*/
#define CONFIG_SYS_INIT_RAM_SIZE	0x2000		/* Size of used area in RAM */

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)

/*-----------------------------------------------------------------------
 * Serial Port
 *----------------------------------------------------------------------*/
#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
#undef CONFIG_SYS_EXT_SERIAL_CLOCK

/*-----------------------------------------------------------------------
 * DDR SDRAM
 *----------------------------------------------------------------------*/
#define CONFIG_SPD_EEPROM	1	/* Use SPD EEPROM for setup	*/
#define SPD_EEPROM_ADDRESS	{0x51, 0x52}	/* SPD i2c spd addresses*/
#define CONFIG_DDR_ECC		1	/* with ECC support		*/
#define CONFIG_DDR_RQDC_FIXED	0x80000038 /* optimal value found by GDA*/
#undef  CONFIG_STRESS

/*-----------------------------------------------------------------------
 * I2C
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed and slave address	*/

#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_SPD_BUS_NUM		0	/* The I2C bus for SPD		*/

#define IIC0_BOOTPROM_ADDR	0x50
#define IIC0_ALT_BOOTPROM_ADDR	0x54

#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR	(0x50)
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10

/* I2C bootstrap EEPROM */
#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR	0x50
#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET	0
#define CONFIG_4xx_CONFIG_BLOCKSIZE		8

/* I2C RTC */
#define CONFIG_RTC_M41T11	1
#define CONFIG_SYS_RTC_BUS_NUM		1	/* The I2C bus for RTC		*/
#define CONFIG_SYS_I2C_RTC_ADDR	0x68
#define CONFIG_SYS_M41T11_BASE_YEAR	1900	/* play along with linux	*/

/* I2C DTT */
#define CONFIG_DTT_ADM1021	1	/* ADM1021 temp sensor support	*/
#define CONFIG_SYS_DTT_BUS_NUM		1	/* The I2C bus for DTT		*/
/*
 * standard dtt sensor configuration - bottom bit will determine local or
 * remote sensor of the ADM1021, the rest determines index into
 * CONFIG_SYS_DTT_ADM1021 array below.
 */
#define CONFIG_DTT_SENSORS	{ 0, 1 }

/*
 * ADM1021 temp sensor configuration (see dtt/adm1021.c for details).
 * there will be one entry in this array for each two (dummy) sensors in
 * CONFIG_DTT_SENSORS.
 *
 * For Katmai board:
 * - only one ADM1021
 * - i2c addr 0x18
 * - conversion rate 0x02 = 0.25 conversions/second
 * - ALERT ouput disabled
 * - local temp sensor enabled, min set to 0 deg, max set to 85 deg
 * - remote temp sensor enabled, min set to 0 deg, max set to 85 deg
 */
#define CONFIG_SYS_DTT_ADM1021		{ { 0x18, 0x02, 0, 1, 0, 85, 1, 0, 58} }

/*-----------------------------------------------------------------------
 * Environment
 *----------------------------------------------------------------------*/
#define	CONFIG_ENV_IS_IN_FLASH	1	/* Environment uses flash	*/

/*
 * Default environment variables
 */
#define	CONFIG_EXTRA_ENV_SETTINGS					\
	CONFIG_AMCC_DEF_ENV						\
	CONFIG_AMCC_DEF_ENV_POWERPC					\
	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
	"kernel_addr=ff000000\0"					\
	"fdt_addr=ff1e0000\0"						\
	"ramdisk_addr=ff200000\0"					\
	"pciconfighost=1\0"						\
	"pcie_mode=RP:RP:RP\0"						\
	""

/*
 * Commands additional to the ones defined in amcc-common.h
 */
#define CONFIG_CMD_CHIP_CONFIG
#define CONFIG_CMD_DATE
#define CONFIG_CMD_ECCTEST
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_PCI
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_SNTP

#define	CONFIG_IBM_EMAC4_V4	1	/* 440SPe has this EMAC version	*/
#define CONFIG_PHY_ADDR		1	/* PHY address, See schematics	*/
#define CONFIG_HAS_ETH0
#define CONFIG_PHY_RESET        1	/* reset phy upon startup	*/
#define CONFIG_PHY_RESET_DELAY	1000
#define CONFIG_CIS8201_PHY	1	/* Enable 'special' RGMII mode for Cicada phy */
#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */

/*-----------------------------------------------------------------------
 * FLASH related
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/

#define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
#define CONFIG_SYS_MAX_FLASH_BANKS     1		    /* number of banks	    */
#define CONFIG_SYS_MAX_FLASH_SECT	1024		    /* sectors per device   */

#undef	CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CONFIG_ENV_SECT_SIZE	0x20000 /* size of one complete sector	*/
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
/* General PCI */
#define CONFIG_PCI			/* include pci support		*/
#define CONFIG_PCI_PNP		1	/* do pci plug-and-play		*/
#define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup	*/
#define CONFIG_PCI_CONFIG_HOST_BRIDGE

/* Board-specific PCI */
#define CONFIG_SYS_PCI_TARGET_INIT		/* let board init pci target    */
#undef	CONFIG_SYS_PCI_MASTER_INIT

#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014	/* IBM				*/
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever			*/
/* #define CONFIG_SYS_PCI_SUBSYS_ID	CONFIG_SYS_PCI_SUBSYS_DEVICEID */

/*
 *  NETWORK Support (PCI):
 */
/* Support for Intel 82557/82559/82559ER chips. */
#define CONFIG_EEPRO100

/*-----------------------------------------------------------------------
 * Xilinx System ACE support
 *----------------------------------------------------------------------*/
#define CONFIG_SYSTEMACE	1	/* Enable SystemACE support	*/
#define CONFIG_SYS_SYSTEMACE_WIDTH	16	/* Data bus width is 16		*/
#define CONFIG_SYS_SYSTEMACE_BASE	CONFIG_SYS_ACE_BASE
#define CONFIG_DOS_PARTITION	1

/*-----------------------------------------------------------------------
 * External Bus Controller (EBC) Setup
 *----------------------------------------------------------------------*/

/* Memory Bank 0 (Flash) initialization					*/
#define CONFIG_SYS_EBC_PB0AP		(EBC_BXAP_BME_DISABLED      |		\
				 EBC_BXAP_TWT_ENCODE(7)     |		\
				 EBC_BXAP_BCE_DISABLE       |		\
				 EBC_BXAP_BCT_2TRANS        |		\
				 EBC_BXAP_CSN_ENCODE(0)     |		\
				 EBC_BXAP_OEN_ENCODE(0)     |		\
				 EBC_BXAP_WBN_ENCODE(0)     |		\
				 EBC_BXAP_WBF_ENCODE(0)     |		\
				 EBC_BXAP_TH_ENCODE(0)      |		\
				 EBC_BXAP_RE_DISABLED       |		\
				 EBC_BXAP_SOR_DELAYED       |		\
				 EBC_BXAP_BEM_WRITEONLY     |		\
				 EBC_BXAP_PEN_DISABLED)
#define CONFIG_SYS_EBC_PB0CR		(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |	\
				 EBC_BXCR_BS_16MB                    |	\
				 EBC_BXCR_BU_RW                      |	\
				 EBC_BXCR_BW_16BIT)

/* Memory Bank 1 (Xilinx System ACE controller) initialization		*/
#define CONFIG_SYS_EBC_PB1AP		(EBC_BXAP_BME_DISABLED      |		\
				 EBC_BXAP_TWT_ENCODE(4)     |		\
				 EBC_BXAP_BCE_DISABLE       |		\
				 EBC_BXAP_BCT_2TRANS        |		\
				 EBC_BXAP_CSN_ENCODE(0)     |		\
				 EBC_BXAP_OEN_ENCODE(0)     |		\
				 EBC_BXAP_WBN_ENCODE(0)     |		\
				 EBC_BXAP_WBF_ENCODE(0)     |		\
				 EBC_BXAP_TH_ENCODE(0)      |		\
				 EBC_BXAP_RE_DISABLED       |		\
				 EBC_BXAP_SOR_NONDELAYED    |		\
				 EBC_BXAP_BEM_WRITEONLY     |		\
				 EBC_BXAP_PEN_DISABLED)
#define CONFIG_SYS_EBC_PB1CR		(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_ACE_BASE)  |	\
				 EBC_BXCR_BS_1MB                    |	\
				 EBC_BXCR_BU_RW                     |	\
				 EBC_BXCR_BW_16BIT)

/*-------------------------------------------------------------------------
 * Initialize EBC CONFIG -
 * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
 * default value : 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
 *-------------------------------------------------------------------------*/
#define CONFIG_SYS_EBC_CFG		(EBC_CFG_LE_UNLOCK    |	\
				 EBC_CFG_PTD_ENABLE   |	\
				 EBC_CFG_RTC_16PERCLK | \
				 EBC_CFG_ATC_PREVIOUS | \
				 EBC_CFG_DTC_PREVIOUS | \
				 EBC_CFG_CTC_PREVIOUS | \
				 EBC_CFG_OEO_PREVIOUS | \
				 EBC_CFG_EMC_DEFAULT  |	\
				 EBC_CFG_PME_DISABLE  |	\
				 EBC_CFG_PR_16)

/*-----------------------------------------------------------------------
 * GPIO Setup
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_GPIO_PCIE_PRESENT0	17
#define CONFIG_SYS_GPIO_PCIE_PRESENT1	21
#define CONFIG_SYS_GPIO_PCIE_PRESENT2	23
#define CONFIG_SYS_GPIO_RS232_FORCEOFF	30

#define CONFIG_SYS_PFC0		(GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT0) | \
				 GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT1) | \
				 GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT2) | \
				 GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF))
#define CONFIG_SYS_GPIO_OR		GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
#define CONFIG_SYS_GPIO_TCR		GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
#define CONFIG_SYS_GPIO_ODR		0

#endif	/* __CONFIG_H */
Commit	Line	Data
4745acaa SR	1	/*
	2	* (C) Copyright 2007
	3	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	4	*
	5	* (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	/************************************************************************
	27	* katmai.h - configuration for AMCC Katmai (440SPe)
	28	***********************************************************************/
	29
	30	#ifndef __CONFIG_H
	31	#define __CONFIG_H
83b4cfa3	32
4745acaa SR	33	/*-----------------------------------------------------------------------
	34	* High Level Configuration Options
	35	----------------------------------------------------------------------/
	36	#define CONFIG_KATMAI 1 /* Board is Katmai */
	37	#define CONFIG_4xx 1 /* ... PPC4xx family */
	38	#define CONFIG_440 1 /* ... PPC440 family */
	39	#define CONFIG_440SPE 1 /* Specifc SPe support */
2a72e9ed	40	#define CONFIG_440SPE_REVA 1 /* Support old Rev A. */
4745acaa	41	#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
6d0f6bcf	42	#define CONFIG_SYS_4xx_RESET_TYPE 0x2 /* use chip reset on this board */
490f2040	43
2ae18241 WD	44	#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
2ae18241 WD	45
5d812b8b SR	46	/*
	47	* Enable this board for more than 2GB of SDRAM
	48	*/
	49	#define CONFIG_PHYS_64BIT
	50	#define CONFIG_VERY_BIG_RAM
5d812b8b	51
490f2040 SR	52	/*
	53	* Include common defines/options for all AMCC eval boards
	54	*/
	55	#define CONFIG_HOSTNAME katmai
	56	#include "amcc-common.h"
4745acaa SR	57
4745acaa SR	58	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
4745acaa SR	59	#undef CONFIG_SHOW_BOOT_PROGRESS
	60
	61	/*-----------------------------------------------------------------------
	62	* Base addresses -- Note these are effective addresses where the
	63	* actual resources get mapped (not physical addresses)
	64	----------------------------------------------------------------------/
6d0f6bcf	65	#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH */
6d0f6bcf	66	#define CONFIG_SYS_ISRAM_BASE 0x90000000 /* internal SRAM */
4745acaa	67
6d0f6bcf JCPV	68	#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
	69	#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
	70	#define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
4745acaa	71
6d0f6bcf JCPV	72	#define CONFIG_SYS_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */
	73	#define CONFIG_SYS_PCIE_MEMSIZE 0x08000000 /* smallest incr for PCIe port */
	74	#define CONFIG_SYS_PCIE_BASE 0xe0000000 /* PCIe UTL regs */
4745acaa	75
6d0f6bcf JCPV	76	#define CONFIG_SYS_PCIE0_CFGBASE 0xc0000000
	77	#define CONFIG_SYS_PCIE1_CFGBASE 0xc1000000
	78	#define CONFIG_SYS_PCIE2_CFGBASE 0xc2000000
	79	#define CONFIG_SYS_PCIE0_XCFGBASE 0xc3000000
	80	#define CONFIG_SYS_PCIE1_XCFGBASE 0xc3001000
	81	#define CONFIG_SYS_PCIE2_XCFGBASE 0xc3002000
4745acaa	82
97923770	83	/* base address of inbound PCIe window */
6d0f6bcf	84	#define CONFIG_SYS_PCIE_INBOUND_BASE 0x0000000000000000ULL
97923770	85
4745acaa	86	/* System RAM mapped to PCI space */
6d0f6bcf JCPV	87	#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
6d0f6bcf JCPV	88	#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
4745acaa SR	89	#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
4745acaa SR	90
6d0f6bcf	91	#define CONFIG_SYS_ACE_BASE 0xfe000000 /* Xilinx ACE controller - Compact Flash */
4745acaa SR	92
	93	/*-----------------------------------------------------------------------
	94	* Initial RAM & stack pointer (placed in internal SRAM)
	95	----------------------------------------------------------------------/
6d0f6bcf JCPV	96	#define CONFIG_SYS_TEMP_STACK_OCM 1
	97	#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
	98	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
553f0982	99	#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
4745acaa	100
25ddd1fb	101	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
800eb096	102	#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
4745acaa SR	103
	104	/*-----------------------------------------------------------------------
	105	* Serial Port
	106	----------------------------------------------------------------------/
550650dd	107	#define CONFIG_CONS_INDEX 1 /* Use UART0 */
6d0f6bcf	108	#undef CONFIG_SYS_EXT_SERIAL_CLOCK
4745acaa SR	109
	110	/*-----------------------------------------------------------------------
	111	* DDR SDRAM
	112	----------------------------------------------------------------------/
	113	#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
ba58e4c9	114	#define SPD_EEPROM_ADDRESS {0x51, 0x52} /* SPD i2c spd addresses*/
2721a68a	115	#define CONFIG_DDR_ECC 1 /* with ECC support */
845c6c95	116	#define CONFIG_DDR_RQDC_FIXED 0x80000038 /* optimal value found by GDA*/
4745acaa	117	#undef CONFIG_STRESS
4745acaa SR	118
	119	/*-----------------------------------------------------------------------
	120	* I2C
	121	----------------------------------------------------------------------/
6d0f6bcf	122	#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
4745acaa SR	123
4745acaa SR	124	#define CONFIG_I2C_MULTI_BUS
6d0f6bcf	125	#define CONFIG_SYS_SPD_BUS_NUM 0 /* The I2C bus for SPD */
4745acaa SR	126
	127	#define IIC0_BOOTPROM_ADDR 0x50
	128	#define IIC0_ALT_BOOTPROM_ADDR 0x54
	129
6d0f6bcf JCPV	130	#define CONFIG_SYS_I2C_MULTI_EEPROMS
	131	#define CONFIG_SYS_I2C_EEPROM_ADDR (0x50)
	132	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	133	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	134	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
4745acaa	135
efe12bce SR	136	/* I2C bootstrap EEPROM */
	137	#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x50
	138	#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
	139	#define CONFIG_4xx_CONFIG_BLOCKSIZE 8
	140
4745acaa SR	141	/* I2C RTC */
4745acaa SR	142	#define CONFIG_RTC_M41T11 1
6d0f6bcf JCPV	143	#define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */
	144	#define CONFIG_SYS_I2C_RTC_ADDR 0x68
	145	#define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with linux */
4745acaa SR	146
	147	/* I2C DTT */
	148	#define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */
6d0f6bcf	149	#define CONFIG_SYS_DTT_BUS_NUM 1 /* The I2C bus for DTT */
4745acaa SR	150	/*
	151	* standard dtt sensor configuration - bottom bit will determine local or
	152	* remote sensor of the ADM1021, the rest determines index into
6d0f6bcf	153	* CONFIG_SYS_DTT_ADM1021 array below.
4745acaa SR	154	*/
	155	#define CONFIG_DTT_SENSORS { 0, 1 }
	156
	157	/*
	158	* ADM1021 temp sensor configuration (see dtt/adm1021.c for details).
	159	* there will be one entry in this array for each two (dummy) sensors in
	160	* CONFIG_DTT_SENSORS.
	161	*
	162	* For Katmai board:
	163	* - only one ADM1021
	164	* - i2c addr 0x18
	165	* - conversion rate 0x02 = 0.25 conversions/second
	166	* - ALERT ouput disabled
	167	* - local temp sensor enabled, min set to 0 deg, max set to 85 deg
	168	* - remote temp sensor enabled, min set to 0 deg, max set to 85 deg
	169	*/
6d0f6bcf	170	#define CONFIG_SYS_DTT_ADM1021 { { 0x18, 0x02, 0, 1, 0, 85, 1, 0, 58} }
4745acaa SR	171
	172	/*-----------------------------------------------------------------------
	173	* Environment
	174	----------------------------------------------------------------------/
5a1aceb0	175	#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment uses flash */
4745acaa	176
490f2040 SR	177	/*
	178	* Default environment variables
	179	*/
4745acaa	180	#define CONFIG_EXTRA_ENV_SETTINGS \
490f2040 SR	181	CONFIG_AMCC_DEF_ENV \
490f2040 SR	182	CONFIG_AMCC_DEF_ENV_POWERPC \
490f2040	183	CONFIG_AMCC_DEF_ENV_NOR_UPD \
fc21cd55 SR	184	"kernel_addr=ff000000\0" \
	185	"fdt_addr=ff1e0000\0" \
	186	"ramdisk_addr=ff200000\0" \
6efc1fc0	187	"pciconfighost=1\0" \
d4cb2d17	188	"pcie_mode=RP:RP:RP\0" \
4745acaa	189	""
079a136c	190
bc234c12	191	/*
490f2040	192	* Commands additional to the ones defined in amcc-common.h
bc234c12	193	*/
efe12bce	194	#define CONFIG_CMD_CHIP_CONFIG
bc234c12	195	#define CONFIG_CMD_DATE
e3722860	196	#define CONFIG_CMD_ECCTEST
efe12bce SR	197	#define CONFIG_CMD_EXT2
efe12bce SR	198	#define CONFIG_CMD_FAT
bc234c12	199	#define CONFIG_CMD_PCI
bc234c12	200	#define CONFIG_CMD_SDRAM
afe9fa59	201	#define CONFIG_CMD_SNTP
4745acaa SR	202
4745acaa SR	203	#define CONFIG_IBM_EMAC4_V4 1 /* 440SPe has this EMAC version */
4745acaa SR	204	#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
	205	#define CONFIG_HAS_ETH0
	206	#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
	207	#define CONFIG_PHY_RESET_DELAY 1000
	208	#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */
	209	#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
4745acaa SR	210
	211	/*-----------------------------------------------------------------------
	212	* FLASH related
	213	----------------------------------------------------------------------/
6d0f6bcf	214	#define CONFIG_SYS_FLASH_CFI
00b1883a	215	#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf JCPV	216	#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
6d0f6bcf JCPV	217	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
4745acaa	218
6d0f6bcf JCPV	219	#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
	220	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
	221	#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
4745acaa	222
6d0f6bcf JCPV	223	#undef CONFIG_SYS_FLASH_CHECKSUM
	224	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	225	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
4745acaa	226
0e8d1586	227	#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
6d0f6bcf	228	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
0e8d1586	229	#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
4745acaa SR	230
4745acaa SR	231	/* Address and size of Redundant Environment Sector */
0e8d1586 JCPV	232	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
0e8d1586 JCPV	233	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
4745acaa SR	234
	235	/*-----------------------------------------------------------------------
	236	* PCI stuff
	237	*-----------------------------------------------------------------------
	238	*/
	239	/* General PCI */
	240	#define CONFIG_PCI /* include pci support */
	241	#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
	242	#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
6efc1fc0	243	#define CONFIG_PCI_CONFIG_HOST_BRIDGE
4745acaa SR	244
4745acaa SR	245	/* Board-specific PCI */
6d0f6bcf JCPV	246	#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
6d0f6bcf JCPV	247	#undef CONFIG_SYS_PCI_MASTER_INIT
4745acaa	248
6d0f6bcf JCPV	249	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
	250	#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
	251	/* #define CONFIG_SYS_PCI_SUBSYS_ID CONFIG_SYS_PCI_SUBSYS_DEVICEID */
4745acaa SR	252
	253	/*
	254	* NETWORK Support (PCI):
	255	*/
	256	/* Support for Intel 82557/82559/82559ER chips. */
	257	#define CONFIG_EEPRO100
	258
	259	/*-----------------------------------------------------------------------
	260	* Xilinx System ACE support
	261	----------------------------------------------------------------------/
	262	#define CONFIG_SYSTEMACE 1 /* Enable SystemACE support */
6d0f6bcf JCPV	263	#define CONFIG_SYS_SYSTEMACE_WIDTH 16 /* Data bus width is 16 */
6d0f6bcf JCPV	264	#define CONFIG_SYS_SYSTEMACE_BASE CONFIG_SYS_ACE_BASE
4745acaa SR	265	#define CONFIG_DOS_PARTITION 1
	266
	267	/*-----------------------------------------------------------------------
	268	* External Bus Controller (EBC) Setup
	269	----------------------------------------------------------------------/
	270
	271	/* Memory Bank 0 (Flash) initialization */
6d0f6bcf	272	#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED \| \
4745acaa SR	273	EBC_BXAP_TWT_ENCODE(7) \| \
	274	EBC_BXAP_BCE_DISABLE \| \
	275	EBC_BXAP_BCT_2TRANS \| \
	276	EBC_BXAP_CSN_ENCODE(0) \| \
	277	EBC_BXAP_OEN_ENCODE(0) \| \
	278	EBC_BXAP_WBN_ENCODE(0) \| \
	279	EBC_BXAP_WBF_ENCODE(0) \| \
	280	EBC_BXAP_TH_ENCODE(0) \| \
	281	EBC_BXAP_RE_DISABLED \| \
	282	EBC_BXAP_SOR_DELAYED \| \
	283	EBC_BXAP_BEM_WRITEONLY \| \
	284	EBC_BXAP_PEN_DISABLED)
6d0f6bcf	285	#define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) \| \
4745acaa SR	286	EBC_BXCR_BS_16MB \| \
	287	EBC_BXCR_BU_RW \| \
	288	EBC_BXCR_BW_16BIT)
	289
	290	/* Memory Bank 1 (Xilinx System ACE controller) initialization */
6d0f6bcf	291	#define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED \| \
d2168626 SR	292	EBC_BXAP_TWT_ENCODE(4) \| \
	293	EBC_BXAP_BCE_DISABLE \| \
	294	EBC_BXAP_BCT_2TRANS \| \
	295	EBC_BXAP_CSN_ENCODE(0) \| \
	296	EBC_BXAP_OEN_ENCODE(0) \| \
	297	EBC_BXAP_WBN_ENCODE(0) \| \
	298	EBC_BXAP_WBF_ENCODE(0) \| \
	299	EBC_BXAP_TH_ENCODE(0) \| \
	300	EBC_BXAP_RE_DISABLED \| \
	301	EBC_BXAP_SOR_NONDELAYED \| \
	302	EBC_BXAP_BEM_WRITEONLY \| \
	303	EBC_BXAP_PEN_DISABLED)
6d0f6bcf	304	#define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_ACE_BASE) \| \
4745acaa SR	305	EBC_BXCR_BS_1MB \| \
	306	EBC_BXCR_BU_RW \| \
	307	EBC_BXCR_BW_16BIT)
	308
	309	/*-------------------------------------------------------------------------
	310	* Initialize EBC CONFIG -
	311	* Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
	312	* default value : 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
	313	-------------------------------------------------------------------------/
6d0f6bcf	314	#define CONFIG_SYS_EBC_CFG (EBC_CFG_LE_UNLOCK \| \
4745acaa SR	315	EBC_CFG_PTD_ENABLE \| \
	316	EBC_CFG_RTC_16PERCLK \| \
	317	EBC_CFG_ATC_PREVIOUS \| \
	318	EBC_CFG_DTC_PREVIOUS \| \
	319	EBC_CFG_CTC_PREVIOUS \| \
	320	EBC_CFG_OEO_PREVIOUS \| \
	321	EBC_CFG_EMC_DEFAULT \| \
	322	EBC_CFG_PME_DISABLE \| \
	323	EBC_CFG_PR_16)
	324
ba58e4c9 SR	325	/*-----------------------------------------------------------------------
	326	* GPIO Setup
	327	----------------------------------------------------------------------/
6d0f6bcf JCPV	328	#define CONFIG_SYS_GPIO_PCIE_PRESENT0 17
	329	#define CONFIG_SYS_GPIO_PCIE_PRESENT1 21
	330	#define CONFIG_SYS_GPIO_PCIE_PRESENT2 23
	331	#define CONFIG_SYS_GPIO_RS232_FORCEOFF 30
	332
	333	#define CONFIG_SYS_PFC0 (GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT0) \| \
	334	GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT1) \| \
	335	GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT2) \| \
	336	GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF))
	337	#define CONFIG_SYS_GPIO_OR GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
	338	#define CONFIG_SYS_GPIO_TCR GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
	339	#define CONFIG_SYS_GPIO_ODR 0
ba58e4c9	340
4745acaa	341	#endif /* __CONFIG_H */