projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 566806ca | 1 | /* |
| 8a24c07b GE |
2 | * Copyright (c) 2008 Nuovation System Designs, LLC |
| 3 | * Grant Erickson <gerickson@nuovations.com> | |
| 4 | * | |
| 566806ca SR |
5 | * (C) Copyright 2007 |
| 6 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
| 7 | * | |
| 8 | * See file CREDITS for list of people who contributed to this | |
| 9 | * project. | |
| 10 | * | |
| 11 | * This program is free software; you can redistribute it and/or | |
| 12 | * modify it under the terms of the GNU General Public License as | |
| 13 | * published by the Free Software Foundation; either version 2 of | |
| 14 | * the License, or (at your option) any later version. | |
| 15 | * | |
| 16 | * This program is distributed in the hope that it will be useful, | |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 19 | * GNU General Public License for more details. | |
| 20 | * | |
| 21 | * You should have received a copy of the GNU General Public License | |
| 22 | * along with this program; if not, write to the Free Software | |
| 23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 24 | * MA 02111-1307 USA | |
| 25 | */ | |
| 26 | ||
| 27 | /************************************************************************ | |
| 28 | * kilauea.h - configuration for AMCC Kilauea (405EX) | |
| 29 | ***********************************************************************/ | |
| 30 | ||
| 31 | #ifndef __CONFIG_H | |
| 32 | #define __CONFIG_H | |
| 33 | ||
| 34 | /*----------------------------------------------------------------------- | |
| 35 | * High Level Configuration Options | |
| 36 | *----------------------------------------------------------------------*/ | |
| 37 | #define CONFIG_KILAUEA 1 /* Board is Kilauea */ | |
| 38 | #define CONFIG_4xx 1 /* ... PPC4xx family */ | |
| 39 | #define CONFIG_405EX 1 /* Specifc 405EX support*/ | |
| 40 | #define CONFIG_SYS_CLK_FREQ 33333333 /* ext frequency to pll */ | |
| 41 | ||
| 490f2040 SR |
42 | /* |
| 43 | * Include common defines/options for all AMCC eval boards | |
| 44 | */ | |
| 45 | #define CONFIG_HOSTNAME kilauea | |
| 46 | #include "amcc-common.h" | |
| 47 | ||
| 566806ca SR |
48 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ |
| 49 | #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ | |
| 9998b136 | 50 | #define CONFIG_BOARD_TYPES |
| 353f2688 | 51 | #define CONFIG_BOARD_EMAC_COUNT |
| 566806ca SR |
52 | |
| 53 | /*----------------------------------------------------------------------- | |
| 54 | * Base addresses -- Note these are effective addresses where the | |
| 55 | * actual resources get mapped (not physical addresses) | |
| 56 | *----------------------------------------------------------------------*/ | |
| 6d0f6bcf JCPV |
57 | #define CONFIG_SYS_FLASH_BASE 0xFC000000 |
| 58 | #define CONFIG_SYS_NAND_ADDR 0xF8000000 | |
| 59 | #define CONFIG_SYS_FPGA_BASE 0xF0000000 | |
| 60 | #define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 /* internal peripherals*/ | |
| 566806ca SR |
61 | |
| 62 | /*----------------------------------------------------------------------- | |
| 8a24c07b GE |
63 | * Initial RAM & Stack Pointer Configuration Options |
| 64 | * | |
| 65 | * There are traditionally three options for the primordial | |
| 66 | * (i.e. initial) stack usage on the 405-series: | |
| 67 | * | |
| 68 | * 1) On-chip Memory (OCM) (i.e. SRAM) | |
| 69 | * 2) Data cache | |
| 70 | * 3) SDRAM | |
| 71 | * | |
| 72 | * For the 405EX(r), there is no OCM, so we are left with (2) or (3) | |
| 73 | * the latter of which is less than desireable since it requires | |
| 74 | * setting up the SDRAM and ECC in assembly code. | |
| 75 | * | |
| 6d0f6bcf | 76 | * To use (2), define 'CONFIG_SYS_INIT_DCACHE_CS' to be an unused chip |
| 8a24c07b | 77 | * select on the External Bus Controller (EBC) and then select a |
| 6d0f6bcf JCPV |
78 | * value for 'CONFIG_SYS_INIT_RAM_ADDR' outside of the range of valid, |
| 79 | * physical SDRAM. Otherwise, undefine 'CONFIG_SYS_INIT_DCACHE_CS' and | |
| 80 | * select a value for 'CONFIG_SYS_INIT_RAM_ADDR' within the range of valid, | |
| 8a24c07b GE |
81 | * physical SDRAM to use (3). |
| 82 | *-----------------------------------------------------------------------*/ | |
| 83 | ||
| 6d0f6bcf | 84 | #define CONFIG_SYS_INIT_DCACHE_CS 4 |
| 8a24c07b | 85 | |
| 6d0f6bcf JCPV |
86 | #if defined(CONFIG_SYS_INIT_DCACHE_CS) |
| 87 | #define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_SDRAM_BASE + ( 1 << 30)) /* 1 GiB */ | |
| 8a24c07b | 88 | #else |
| 6d0f6bcf JCPV |
89 | #define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_SDRAM_BASE + (32 << 20)) /* 32 MiB */ |
| 90 | #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */ | |
| 8a24c07b | 91 | |
| 6d0f6bcf JCPV |
92 | #define CONFIG_SYS_INIT_RAM_END (4 << 10) /* 4 KiB */ |
| 93 | #define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */ | |
| 94 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
| 566806ca | 95 | |
| 8a24c07b GE |
96 | /* |
| 97 | * If the data cache is being used for the primordial stack and global | |
| 98 | * data area, the POST word must be placed somewhere else. The General | |
| 99 | * Purpose Timer (GPT) is unused by u-boot and the kernel and preserves | |
| 100 | * its compare and mask register contents across reset, so it is used | |
| 101 | * for the POST word. | |
| 102 | */ | |
| 103 | ||
| 6d0f6bcf JCPV |
104 | #if defined(CONFIG_SYS_INIT_DCACHE_CS) |
| 105 | # define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
| 106 | # define CONFIG_SYS_POST_ALT_WORD_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6) | |
| 8a24c07b | 107 | #else |
| 6d0f6bcf JCPV |
108 | # define CONFIG_SYS_INIT_EXTRA_SIZE 16 |
| 109 | # define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_EXTRA_SIZE) | |
| 110 | # define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 4) | |
| 111 | # define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_INIT_RAM_ADDR | |
| 112 | #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */ | |
| 566806ca SR |
113 | |
| 114 | /*----------------------------------------------------------------------- | |
| 115 | * Serial Port | |
| 116 | *----------------------------------------------------------------------*/ | |
| 6d0f6bcf | 117 | #define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */ |
| 566806ca SR |
118 | /* define this if you want console on UART1 */ |
| 119 | #undef CONFIG_UART1_CONSOLE | |
| 120 | ||
| 566806ca SR |
121 | /*----------------------------------------------------------------------- |
| 122 | * Environment | |
| 123 | *----------------------------------------------------------------------*/ | |
| 124 | #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) | |
| 5a1aceb0 | 125 | #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ |
| 566806ca | 126 | #else |
| 51bfee19 | 127 | #define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ |
| 0e8d1586 | 128 | #define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */ |
| 566806ca SR |
129 | #endif |
| 130 | ||
| 131 | /*----------------------------------------------------------------------- | |
| 132 | * FLASH related | |
| 133 | *----------------------------------------------------------------------*/ | |
| 6d0f6bcf | 134 | #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ |
| 00b1883a | 135 | #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ |
| 566806ca | 136 | |
| 6d0f6bcf JCPV |
137 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} |
| 138 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
| 139 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ | |
| 566806ca | 140 | |
| 6d0f6bcf JCPV |
141 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
| 142 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
| 566806ca | 143 | |
| 6d0f6bcf JCPV |
144 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ |
| 145 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ | |
| 566806ca | 146 | |
| 5a1aceb0 | 147 | #ifdef CONFIG_ENV_IS_IN_FLASH |
| 0e8d1586 | 148 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ |
| 6d0f6bcf | 149 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) |
| 0e8d1586 | 150 | #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ |
| 566806ca SR |
151 | |
| 152 | /* Address and size of Redundant Environment Sector */ | |
| 0e8d1586 JCPV |
153 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) |
| 154 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
| 5a1aceb0 | 155 | #endif /* CONFIG_ENV_IS_IN_FLASH */ |
| 566806ca | 156 | |
| 3d6cb3b2 SR |
157 | /* |
| 158 | * IPL (Initial Program Loader, integrated inside CPU) | |
| 159 | * Will load first 4k from NAND (SPL) into cache and execute it from there. | |
| 160 | * | |
| 161 | * SPL (Secondary Program Loader) | |
| 162 | * Will load special U-Boot version (NUB) from NAND and execute it. This SPL | |
| 163 | * has to fit into 4kByte. It sets up the CPU and configures the SDRAM | |
| 164 | * controller and the NAND controller so that the special U-Boot image can be | |
| 165 | * loaded from NAND to SDRAM. | |
| 166 | * | |
| 167 | * NUB (NAND U-Boot) | |
| 168 | * This NAND U-Boot (NUB) is a special U-Boot version which can be started | |
| 169 | * from RAM. Therefore it mustn't (re-)configure the SDRAM controller. | |
| 170 | * | |
| ec724f88 SR |
171 | * On 405EX the SPL is copied to SDRAM before the NAND controller is |
| 172 | * set up. While still running from location 0xfffff000...0xffffffff the | |
| 173 | * NAND controller cannot be accessed since it is attached to CS0 too. | |
| 3d6cb3b2 | 174 | */ |
| 6d0f6bcf JCPV |
175 | #define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */ |
| 176 | #define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */ | |
| 177 | #define CONFIG_SYS_NAND_BOOT_SPL_DST 0x00800000 /* Copy SPL here */ | |
| 178 | #define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */ | |
| 179 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr */ | |
| 180 | #define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST) | |
| 3d6cb3b2 SR |
181 | |
| 182 | /* | |
| 183 | * Define the partitioning of the NAND chip (only RAM U-Boot is needed here) | |
| 184 | */ | |
| 6d0f6bcf JCPV |
185 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */ |
| 186 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */ | |
| 3d6cb3b2 SR |
187 | |
| 188 | /* | |
| 189 | * Now the NAND chip has to be defined (no autodetection used!) | |
| 190 | */ | |
| 6d0f6bcf JCPV |
191 | #define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */ |
| 192 | #define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */ | |
| 193 | #define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */ | |
| 194 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */ | |
| 195 | #define CONFIG_SYS_NAND_4_ADDR_CYCLE 1 /* Fourth addr used (>32MB) */ | |
| 196 | ||
| 197 | #define CONFIG_SYS_NAND_ECCSIZE 256 | |
| 198 | #define CONFIG_SYS_NAND_ECCBYTES 3 | |
| 199 | #define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE) | |
| 200 | #define CONFIG_SYS_NAND_OOBSIZE 16 | |
| 201 | #define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS) | |
| 202 | #define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7} | |
| 3d6cb3b2 | 203 | |
| 51bfee19 | 204 | #ifdef CONFIG_ENV_IS_IN_NAND |
| 3d6cb3b2 SR |
205 | /* |
| 206 | * For NAND booting the environment is embedded in the U-Boot image. Please take | |
| 207 | * look at the file board/amcc/sequoia/u-boot-nand.lds for details. | |
| 208 | */ | |
| 6d0f6bcf JCPV |
209 | #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE |
| 210 | #define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE) | |
| 0e8d1586 | 211 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) |
| 3d6cb3b2 SR |
212 | #endif |
| 213 | ||
| 214 | /*----------------------------------------------------------------------- | |
| 215 | * NAND FLASH | |
| 216 | *----------------------------------------------------------------------*/ | |
| 6d0f6bcf | 217 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
| 6d0f6bcf JCPV |
218 | #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS) |
| 219 | #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ | |
| 3d6cb3b2 | 220 | |
| 566806ca SR |
221 | /*----------------------------------------------------------------------- |
| 222 | * DDR SDRAM | |
| 223 | *----------------------------------------------------------------------*/ | |
| 6d0f6bcf | 224 | #define CONFIG_SYS_MBYTES_SDRAM (256) /* 256MB */ |
| 566806ca | 225 | |
| f6b6c458 AG |
226 | /* |
| 227 | * CONFIG_PPC4xx_DDR_AUTOCALIBRATION | |
| 228 | * | |
| 229 | * Note: DDR Autocalibration Method_A scans the full range of possible PPC4xx | |
| 230 | * SDRAM Controller DDR autocalibration values and takes a lot longer | |
| 231 | * to run than Method_B. | |
| 232 | * (See the Method_A and Method_B algorithm discription in the file: | |
| 233 | * cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c) | |
| 234 | * Define CONFIG_PPC4xx_DDR_METHOD_A to use DDR autocalibration Method_A | |
| 235 | * | |
| 236 | * DDR Autocalibration Method_B is the default. | |
| 237 | */ | |
| 5b34691f | 238 | #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) |
| f6b6c458 AG |
239 | #define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */ |
| 240 | #define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */ | |
| 241 | #undef CONFIG_PPC4xx_DDR_METHOD_A | |
| 5b34691f | 242 | #endif |
| f6b6c458 | 243 | |
| 6d0f6bcf | 244 | #define CONFIG_SYS_SDRAM0_MB0CF_BASE (( 0 << 20) + CONFIG_SYS_SDRAM_BASE) |
| 8a24c07b GE |
245 | |
| 246 | /* DDR1/2 SDRAM Device Control Register Data Values */ | |
| 6d0f6bcf | 247 | #define CONFIG_SYS_SDRAM0_MB0CF ((CONFIG_SYS_SDRAM0_MB0CF_BASE >> 3) | \ |
| 8a24c07b GE |
248 | SDRAM_RXBAS_SDSZ_256MB | \ |
| 249 | SDRAM_RXBAS_SDAM_MODE7 | \ | |
| 250 | SDRAM_RXBAS_SDBE_ENABLE) | |
| 6d0f6bcf JCPV |
251 | #define CONFIG_SYS_SDRAM0_MB1CF SDRAM_RXBAS_SDBE_DISABLE |
| 252 | #define CONFIG_SYS_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE | |
| 253 | #define CONFIG_SYS_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE | |
| 254 | #define CONFIG_SYS_SDRAM0_MCOPT1 (SDRAM_MCOPT1_PMU_OPEN | \ | |
| 2e205084 GE |
255 | SDRAM_MCOPT1_8_BANKS | \ |
| 256 | SDRAM_MCOPT1_DDR2_TYPE | \ | |
| 257 | SDRAM_MCOPT1_QDEP | \ | |
| 258 | SDRAM_MCOPT1_DCOO_DISABLED) | |
| 6d0f6bcf JCPV |
259 | #define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000 |
| 260 | #define CONFIG_SYS_SDRAM0_MODT0 (SDRAM_MODT_EB0W_ENABLE | \ | |
| 2e205084 | 261 | SDRAM_MODT_EB0R_ENABLE) |
| 6d0f6bcf JCPV |
262 | #define CONFIG_SYS_SDRAM0_MODT1 0x00000000 |
| 263 | #define CONFIG_SYS_SDRAM0_CODT (SDRAM_CODT_RK0R_ON | \ | |
| 2e205084 GE |
264 | SDRAM_CODT_CKLZ_36OHM | \ |
| 265 | SDRAM_CODT_DQS_1_8_V_DDR2 | \ | |
| 266 | SDRAM_CODT_IO_NMODE) | |
| 6d0f6bcf JCPV |
267 | #define CONFIG_SYS_SDRAM0_RTR SDRAM_RTR_RINT_ENCODE(1560) |
| 268 | #define CONFIG_SYS_SDRAM0_INITPLR0 (SDRAM_INITPLR_ENABLE | \ | |
| 2e205084 GE |
269 | SDRAM_INITPLR_IMWT_ENCODE(80) | \ |
| 270 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP)) | |
| 6d0f6bcf | 271 | #define CONFIG_SYS_SDRAM0_INITPLR1 (SDRAM_INITPLR_ENABLE | \ |
| 2e205084 GE |
272 | SDRAM_INITPLR_IMWT_ENCODE(3) | \ |
| 273 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \ | |
| 274 | SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \ | |
| 275 | SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL)) | |
| 6d0f6bcf | 276 | #define CONFIG_SYS_SDRAM0_INITPLR2 (SDRAM_INITPLR_ENABLE | \ |
| 2e205084 GE |
277 | SDRAM_INITPLR_IMWT_ENCODE(2) | \ |
| 278 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ | |
| 279 | SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2) | \ | |
| 280 | SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL)) | |
| 6d0f6bcf | 281 | #define CONFIG_SYS_SDRAM0_INITPLR3 (SDRAM_INITPLR_ENABLE | \ |
| 2e205084 GE |
282 | SDRAM_INITPLR_IMWT_ENCODE(2) | \ |
| 283 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ | |
| 284 | SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3) | \ | |
| 285 | SDRAM_INITPLR_IMA_ENCODE(0)) | |
| 6d0f6bcf | 286 | #define CONFIG_SYS_SDRAM0_INITPLR4 (SDRAM_INITPLR_ENABLE | \ |
| 2e205084 GE |
287 | SDRAM_INITPLR_IMWT_ENCODE(2) | \ |
| 288 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ | |
| 289 | SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \ | |
| 290 | SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_DISABLE | \ | |
| 291 | JEDEC_MA_EMR_RTT_75OHM)) | |
| 6d0f6bcf | 292 | #define CONFIG_SYS_SDRAM0_INITPLR5 (SDRAM_INITPLR_ENABLE | \ |
| 2e205084 GE |
293 | SDRAM_INITPLR_IMWT_ENCODE(2) | \ |
| 294 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ | |
| 295 | SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \ | |
| 296 | SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \ | |
| 297 | JEDEC_MA_MR_CL_DDR2_4_0_CLK | \ | |
| 298 | JEDEC_MA_MR_BLEN_4 | \ | |
| 299 | JEDEC_MA_MR_DLL_RESET)) | |
| 6d0f6bcf | 300 | #define CONFIG_SYS_SDRAM0_INITPLR6 (SDRAM_INITPLR_ENABLE | \ |
| 2e205084 GE |
301 | SDRAM_INITPLR_IMWT_ENCODE(3) | \ |
| 302 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \ | |
| 303 | SDRAM_INITPLR_IBA_ENCODE(0x0) | \ | |
| 304 | SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL)) | |
| 6d0f6bcf | 305 | #define CONFIG_SYS_SDRAM0_INITPLR7 (SDRAM_INITPLR_ENABLE | \ |
| 2e205084 GE |
306 | SDRAM_INITPLR_IMWT_ENCODE(26) | \ |
| 307 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH)) | |
| 6d0f6bcf | 308 | #define CONFIG_SYS_SDRAM0_INITPLR8 (SDRAM_INITPLR_ENABLE | \ |
| 2e205084 GE |
309 | SDRAM_INITPLR_IMWT_ENCODE(26) | \ |
| 310 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH)) | |
| 6d0f6bcf | 311 | #define CONFIG_SYS_SDRAM0_INITPLR9 (SDRAM_INITPLR_ENABLE | \ |
| 2e205084 GE |
312 | SDRAM_INITPLR_IMWT_ENCODE(26) | \ |
| 313 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH)) | |
| 6d0f6bcf | 314 | #define CONFIG_SYS_SDRAM0_INITPLR10 (SDRAM_INITPLR_ENABLE | \ |
| 2e205084 GE |
315 | SDRAM_INITPLR_IMWT_ENCODE(26) | \ |
| 316 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH)) | |
| 6d0f6bcf | 317 | #define CONFIG_SYS_SDRAM0_INITPLR11 (SDRAM_INITPLR_ENABLE | \ |
| 2e205084 GE |
318 | SDRAM_INITPLR_IMWT_ENCODE(2) | \ |
| 319 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ | |
| 320 | SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \ | |
| 321 | SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \ | |
| 322 | JEDEC_MA_MR_CL_DDR2_4_0_CLK | \ | |
| 323 | JEDEC_MA_MR_BLEN_4)) | |
| 6d0f6bcf | 324 | #define CONFIG_SYS_SDRAM0_INITPLR12 (SDRAM_INITPLR_ENABLE | \ |
| 2e205084 GE |
325 | SDRAM_INITPLR_IMWT_ENCODE(2) | \ |
| 326 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ | |
| 327 | SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \ | |
| 328 | SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER | \ | |
| 329 | JEDEC_MA_EMR_RDQS_DISABLE | \ | |
| 330 | JEDEC_MA_EMR_DQS_DISABLE | \ | |
| 331 | JEDEC_MA_EMR_RTT_DISABLED | \ | |
| 332 | JEDEC_MA_EMR_ODS_NORMAL)) | |
| 6d0f6bcf | 333 | #define CONFIG_SYS_SDRAM0_INITPLR13 (SDRAM_INITPLR_ENABLE | \ |
| 2e205084 GE |
334 | SDRAM_INITPLR_IMWT_ENCODE(2) | \ |
| 335 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ | |
| 336 | SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \ | |
| 337 | SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT | \ | |
| 338 | JEDEC_MA_EMR_RDQS_DISABLE | \ | |
| 339 | JEDEC_MA_EMR_DQS_DISABLE | \ | |
| 340 | JEDEC_MA_EMR_RTT_DISABLED | \ | |
| 341 | JEDEC_MA_EMR_ODS_NORMAL)) | |
| 6d0f6bcf JCPV |
342 | #define CONFIG_SYS_SDRAM0_INITPLR14 (SDRAM_INITPLR_DISABLE) |
| 343 | #define CONFIG_SYS_SDRAM0_INITPLR15 (SDRAM_INITPLR_DISABLE) | |
| 344 | #define CONFIG_SYS_SDRAM0_RQDC (SDRAM_RQDC_RQDE_ENABLE | \ | |
| 2e205084 | 345 | SDRAM_RQDC_RQFD_ENCODE(56)) |
| 6d0f6bcf JCPV |
346 | #define CONFIG_SYS_SDRAM0_RFDC SDRAM_RFDC_RFFD_ENCODE(521) |
| 347 | #define CONFIG_SYS_SDRAM0_RDCC (SDRAM_RDCC_RDSS_T2) | |
| 348 | #define CONFIG_SYS_SDRAM0_DLCR (SDRAM_DLCR_DCLM_AUTO | \ | |
| 2e205084 GE |
349 | SDRAM_DLCR_DLCS_CONT_DONE | \ |
| 350 | SDRAM_DLCR_DLCV_ENCODE(165)) | |
| 6d0f6bcf JCPV |
351 | #define CONFIG_SYS_SDRAM0_CLKTR (SDRAM_CLKTR_CLKP_180_DEG_ADV) |
| 352 | #define CONFIG_SYS_SDRAM0_WRDTR 0x00000000 | |
| 353 | #define CONFIG_SYS_SDRAM0_SDTR1 (SDRAM_SDTR1_LDOF_2_CLK | \ | |
| 2e205084 GE |
354 | SDRAM_SDTR1_RTW_2_CLK | \ |
| 355 | SDRAM_SDTR1_RTRO_1_CLK) | |
| 6d0f6bcf | 356 | #define CONFIG_SYS_SDRAM0_SDTR2 (SDRAM_SDTR2_RCD_3_CLK | \ |
| 2e205084 GE |
357 | SDRAM_SDTR2_WTR_2_CLK | \ |
| 358 | SDRAM_SDTR2_XSNR_32_CLK | \ | |
| 359 | SDRAM_SDTR2_WPC_4_CLK | \ | |
| 360 | SDRAM_SDTR2_RPC_2_CLK | \ | |
| 361 | SDRAM_SDTR2_RP_3_CLK | \ | |
| 362 | SDRAM_SDTR2_RRD_2_CLK) | |
| 6d0f6bcf | 363 | #define CONFIG_SYS_SDRAM0_SDTR3 (SDRAM_SDTR3_RAS_ENCODE(8) | \ |
| 2e205084 GE |
364 | SDRAM_SDTR3_RC_ENCODE(11) | \ |
| 365 | SDRAM_SDTR3_XCS | \ | |
| 366 | SDRAM_SDTR3_RFC_ENCODE(26)) | |
| 6d0f6bcf | 367 | #define CONFIG_SYS_SDRAM0_MMODE (SDRAM_MMODE_WR_DDR2_3_CYC | \ |
| 2e205084 GE |
368 | SDRAM_MMODE_DCL_DDR2_4_0_CLK | \ |
| 369 | SDRAM_MMODE_BLEN_4) | |
| 6d0f6bcf | 370 | #define CONFIG_SYS_SDRAM0_MEMODE (SDRAM_MEMODE_DQS_DISABLE | \ |
| 2e205084 | 371 | SDRAM_MEMODE_RTT_75OHM) |
| 8a24c07b | 372 | |
| 566806ca SR |
373 | /*----------------------------------------------------------------------- |
| 374 | * I2C | |
| 375 | *----------------------------------------------------------------------*/ | |
| 6d0f6bcf | 376 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
| 566806ca | 377 | |
| 6d0f6bcf JCPV |
378 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* I2C boot EEPROM (24C02BN) */ |
| 379 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ | |
| f6af8ce0 SR |
380 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 |
| 381 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
| 566806ca | 382 | |
| 4b1389e0 SR |
383 | /* I2C bootstrap EEPROM */ |
| 384 | #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52 | |
| 385 | #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0 | |
| 386 | #define CONFIG_4xx_CONFIG_BLOCKSIZE 16 | |
| 387 | ||
| 566806ca SR |
388 | /* Standard DTT sensor configuration */ |
| 389 | #define CONFIG_DTT_DS1775 1 | |
| 390 | #define CONFIG_DTT_SENSORS { 0 } | |
| 6d0f6bcf | 391 | #define CONFIG_SYS_I2C_DTT_ADDR 0x48 |
| 566806ca SR |
392 | |
| 393 | /* RTC configuration */ | |
| 394 | #define CONFIG_RTC_DS1338 1 | |
| 6d0f6bcf | 395 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
| 566806ca SR |
396 | |
| 397 | /*----------------------------------------------------------------------- | |
| 398 | * Ethernet | |
| 399 | *----------------------------------------------------------------------*/ | |
| 400 | #define CONFIG_M88E1111_PHY 1 | |
| 401 | #define CONFIG_IBM_EMAC4_V4 1 | |
| 1740c1bf | 402 | #define CONFIG_EMAC_PHY_MODE EMAC_PHY_MODE_RGMII_RGMII |
| 566806ca SR |
403 | #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ |
| 404 | ||
| 405 | #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ | |
| 406 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
| 407 | ||
| 408 | #define CONFIG_HAS_ETH0 1 | |
| 409 | ||
| 566806ca SR |
410 | #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ |
| 411 | #define CONFIG_PHY1_ADDR 2 | |
| 412 | ||
| f6b6c458 AG |
413 | /* Debug messages for the DDR autocalibration */ |
| 414 | #define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */ | |
| 415 | ||
| 490f2040 SR |
416 | /* |
| 417 | * Default environment variables | |
| 418 | */ | |
| 566806ca | 419 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 490f2040 SR |
420 | CONFIG_AMCC_DEF_ENV \ |
| 421 | CONFIG_AMCC_DEF_ENV_POWERPC \ | |
| 422 | CONFIG_AMCC_DEF_ENV_PPC_OLD \ | |
| 423 | CONFIG_AMCC_DEF_ENV_NOR_UPD \ | |
| 424 | CONFIG_AMCC_DEF_ENV_NAND_UPD \ | |
| 566806ca | 425 | "logversion=2\0" \ |
| 566806ca | 426 | "kernel_addr=fc000000\0" \ |
| 64e541f4 | 427 | "fdt_addr=fc1e0000\0" \ |
| 566806ca | 428 | "ramdisk_addr=fc200000\0" \ |
| 566806ca | 429 | "pciconfighost=1\0" \ |
| d4cb2d17 | 430 | "pcie_mode=RP:RP\0" \ |
| 566806ca | 431 | "" |
| 566806ca SR |
432 | |
| 433 | /* | |
| 490f2040 | 434 | * Commands additional to the ones defined in amcc-common.h |
| 566806ca | 435 | */ |
| 4b1389e0 | 436 | #define CONFIG_CMD_CHIP_CONFIG |
| 566806ca | 437 | #define CONFIG_CMD_DATE |
| 566806ca | 438 | #define CONFIG_CMD_LOG |
| 566806ca | 439 | #define CONFIG_CMD_NAND |
| 566806ca | 440 | #define CONFIG_CMD_PCI |
| afe9fa59 | 441 | #define CONFIG_CMD_SNTP |
| 566806ca | 442 | |
| dd7c3020 SR |
443 | /* |
| 444 | * Don't run the memory POST on the NAND-booting version. It will | |
| 445 | * overwrite part of the U-Boot image which is already loaded from NAND | |
| 446 | * to SDRAM. | |
| 447 | */ | |
| 448 | #if defined(CONFIG_NAND_U_BOOT) | |
| 449 | #define CONFIG_SYS_POST_MEMORY_ON 0 | |
| 450 | #else | |
| 451 | #define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY | |
| 452 | #endif | |
| 453 | ||
| 566806ca | 454 | /* POST support */ |
| 6d0f6bcf JCPV |
455 | #define CONFIG_POST (CONFIG_SYS_POST_CACHE | \ |
| 456 | CONFIG_SYS_POST_CPU | \ | |
| 457 | CONFIG_SYS_POST_ETHER | \ | |
| 458 | CONFIG_SYS_POST_I2C | \ | |
| dd7c3020 | 459 | CONFIG_SYS_POST_MEMORY_ON | \ |
| 6d0f6bcf | 460 | CONFIG_SYS_POST_UART) |
| 566806ca SR |
461 | |
| 462 | /* Define here the base-addresses of the UARTs to test in POST */ | |
| 6d0f6bcf | 463 | #define CONFIG_SYS_POST_UART_TABLE {UART0_BASE, UART1_BASE} |
| 566806ca SR |
464 | |
| 465 | #define CONFIG_LOGBUFFER | |
| 6d0f6bcf | 466 | #define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */ |
| 566806ca | 467 | |
| 6d0f6bcf | 468 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ |
| 566806ca | 469 | |
| 566806ca SR |
470 | /*----------------------------------------------------------------------- |
| 471 | * PCI stuff | |
| 472 | *----------------------------------------------------------------------*/ | |
| 473 | #define CONFIG_PCI /* include pci support */ | |
| 474 | #define CONFIG_PCI_PNP 1 /* do pci plug-and-play */ | |
| 475 | #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ | |
| 476 | #define CONFIG_PCI_CONFIG_HOST_BRIDGE | |
| 477 | ||
| 478 | /*----------------------------------------------------------------------- | |
| 479 | * PCIe stuff | |
| 480 | *----------------------------------------------------------------------*/ | |
| 6d0f6bcf JCPV |
481 | #define CONFIG_SYS_PCIE_MEMBASE 0x90000000 /* mapped PCIe memory */ |
| 482 | #define CONFIG_SYS_PCIE_MEMSIZE 0x08000000 /* 128 Meg, smallest incr per port */ | |
| 566806ca | 483 | |
| 6d0f6bcf JCPV |
484 | #define CONFIG_SYS_PCIE0_CFGBASE 0xa0000000 /* remote access */ |
| 485 | #define CONFIG_SYS_PCIE0_XCFGBASE 0xb0000000 /* local access */ | |
| 486 | #define CONFIG_SYS_PCIE0_CFGMASK 0xe0000001 /* 512 Meg */ | |
| 566806ca | 487 | |
| 6d0f6bcf JCPV |
488 | #define CONFIG_SYS_PCIE1_CFGBASE 0xc0000000 /* remote access */ |
| 489 | #define CONFIG_SYS_PCIE1_XCFGBASE 0xd0000000 /* local access */ | |
| 490 | #define CONFIG_SYS_PCIE1_CFGMASK 0xe0000001 /* 512 Meg */ | |
| 566806ca | 491 | |
| 6d0f6bcf JCPV |
492 | #define CONFIG_SYS_PCIE0_UTLBASE 0xef502000 |
| 493 | #define CONFIG_SYS_PCIE1_UTLBASE 0xef503000 | |
| 566806ca SR |
494 | |
| 495 | /* base address of inbound PCIe window */ | |
| 6d0f6bcf | 496 | #define CONFIG_SYS_PCIE_INBOUND_BASE 0x0000000000000000ULL |
| 566806ca | 497 | |
| 566806ca SR |
498 | /*----------------------------------------------------------------------- |
| 499 | * External Bus Controller (EBC) Setup | |
| 500 | *----------------------------------------------------------------------*/ | |
| 3d6cb3b2 SR |
501 | #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) |
| 502 | /* booting from NAND, so NAND chips select has to be on CS 0 */ | |
| 6d0f6bcf | 503 | #define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */ |
| 3d6cb3b2 SR |
504 | |
| 505 | /* Memory Bank 1 (NOR-FLASH) initialization */ | |
| 6d0f6bcf JCPV |
506 | #define CONFIG_SYS_EBC_PB1AP 0x05806500 |
| 507 | #define CONFIG_SYS_EBC_PB1CR 0xFC0DA000 /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/ | |
| 3d6cb3b2 SR |
508 | |
| 509 | /* Memory Bank 0 (NAND-FLASH) initialization */ | |
| 6d0f6bcf JCPV |
510 | #define CONFIG_SYS_EBC_PB0AP 0x018003c0 |
| 511 | #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1e000) | |
| 3d6cb3b2 | 512 | #else |
| 6d0f6bcf | 513 | #define CONFIG_SYS_NAND_CS 1 /* NAND chip connected to CSx */ |
| 566806ca SR |
514 | |
| 515 | /* Memory Bank 0 (NOR-FLASH) initialization */ | |
| 6d0f6bcf JCPV |
516 | #define CONFIG_SYS_EBC_PB0AP 0x05806500 |
| 517 | #define CONFIG_SYS_EBC_PB0CR 0xFC0DA000 /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/ | |
| 566806ca SR |
518 | |
| 519 | /* Memory Bank 1 (NAND-FLASH) initialization */ | |
| 6d0f6bcf JCPV |
520 | #define CONFIG_SYS_EBC_PB1AP 0x018003c0 |
| 521 | #define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_NAND_ADDR | 0x1e000) | |
| 3d6cb3b2 | 522 | #endif |
| 566806ca | 523 | |
| 9998b136 SR |
524 | /* Memory Bank 2 (FPGA) initialization */ |
| 525 | #define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_ENABLED | \ | |
| 526 | EBC_BXAP_FWT_ENCODE(6) | \ | |
| 527 | EBC_BXAP_BWT_ENCODE(1) | \ | |
| 528 | EBC_BXAP_BCE_DISABLE | \ | |
| 529 | EBC_BXAP_BCT_2TRANS | \ | |
| 530 | EBC_BXAP_CSN_ENCODE(0) | \ | |
| 531 | EBC_BXAP_OEN_ENCODE(0) | \ | |
| 532 | EBC_BXAP_WBN_ENCODE(3) | \ | |
| 533 | EBC_BXAP_WBF_ENCODE(1) | \ | |
| 534 | EBC_BXAP_TH_ENCODE(4) | \ | |
| 535 | EBC_BXAP_RE_DISABLED | \ | |
| 536 | EBC_BXAP_SOR_DELAYED | \ | |
| 537 | EBC_BXAP_BEM_WRITEONLY | \ | |
| 538 | EBC_BXAP_PEN_DISABLED) | |
| 539 | #define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA_BASE | 0x18000) | |
| 566806ca | 540 | |
| 6d0f6bcf | 541 | #define CONFIG_SYS_EBC_CFG 0x7FC00000 /* EBC0_CFG */ |
| 566806ca | 542 | |
| 566806ca SR |
543 | /*----------------------------------------------------------------------- |
| 544 | * GPIO Setup | |
| 545 | *----------------------------------------------------------------------*/ | |
| 6d0f6bcf | 546 | #define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ |
| 9ea61b57 SR |
547 | { \ |
| 548 | /* GPIO Core 0 */ \ | |
| 549 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO0 EBC_DATA_PAR(0) */ \ | |
| 550 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO1 EBC_DATA_PAR(1) */ \ | |
| 551 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO2 EBC_DATA_PAR(2) */ \ | |
| 552 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO3 EBC_DATA_PAR(3) */ \ | |
| 553 | {GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO4 EBC_DATA(20) USB2_DATA(4) */ \ | |
| 554 | {GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO5 EBC_DATA(21) USB2_DATA(5) */ \ | |
| 555 | {GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO6 EBC_DATA(22) USB2_DATA(6) */ \ | |
| 556 | {GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO7 EBC_DATA(23) USB2_DATA(7) */ \ | |
| 8be76090 SR |
557 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 CS(1)/NFCE(1) IRQ(7) */ \ |
| 558 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 CS(2)/NFCE(2) IRQ(8) */ \ | |
| 559 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 CS(3)/NFCE(3) IRQ(9) */ \ | |
| 9ea61b57 SR |
560 | {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 IRQ(6) */ \ |
| 561 | {GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO12 EBC_DATA(16) USB2_DATA(0) */ \ | |
| 562 | {GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO13 EBC_DATA(17) USB2_DATA(1) */ \ | |
| 7cfc12a7 SR |
563 | {GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO14 EBC_DATA(18) USB2_DATA(2) */ \ |
| 564 | {GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO15 EBC_DATA(19) USB2_DATA(3) */ \ | |
| 9ea61b57 | 565 | {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 UART0_DCD UART1_CTS */ \ |
| 8be76090 | 566 | {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 UART0_DSR UART1_RTS */ \ |
| 9ea61b57 SR |
567 | {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 UART0_CTS */ \ |
| 568 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 UART0_RTS */ \ | |
| 569 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO20 UART0_DTR UART1_TX */ \ | |
| 570 | {GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0}, /* GPIO21 UART0_RI UART1_RX */ \ | |
| 571 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO22 EBC_HOLD_REQ DMA_ACK2 */ \ | |
| 572 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO23 EBC_HOLD_ACK DMA_REQ2 */ \ | |
| 573 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO24 EBC_EXT_REQ DMA_EOT2 IRQ(4) */ \ | |
| 574 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO25 EBC_EXT_ACK DMA_ACK3 IRQ(3) */ \ | |
| 575 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 EBC_ADDR(5) DMA_EOT0 TS(3) */ \ | |
| 576 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO27 EBC_BUS_REQ DMA_EOT3 IRQ(5) */ \ | |
| 577 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO28 */ \ | |
| 8be76090 SR |
578 | {GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0}, /* GPIO29 DMA_EOT1 IRQ(2) */ \ |
| 579 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO30 DMA_REQ1 IRQ(1) */ \ | |
| 580 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO31 DMA_ACK1 IRQ(0) */ \ | |
| 9ea61b57 SR |
581 | } \ |
| 582 | } | |
| 566806ca | 583 | |
| 566806ca SR |
584 | /*----------------------------------------------------------------------- |
| 585 | * Some Kilauea stuff..., mainly fpga registers | |
| 586 | */ | |
| 6d0f6bcf | 587 | #define CONFIG_SYS_FPGA_REG_BASE CONFIG_SYS_FPGA_BASE |
| 9998b136 | 588 | #define CONFIG_SYS_FPGA_FIFO_BASE (CONFIG_SYS_FPGA_BASE | (1 << 10)) |
| 566806ca SR |
589 | |
| 590 | /* interrupt */ | |
| 6d0f6bcf JCPV |
591 | #define CONFIG_SYS_FPGA_SLIC0_R_DPRAM_INT 0x80000000 |
| 592 | #define CONFIG_SYS_FPGA_SLIC0_W_DPRAM_INT 0x40000000 | |
| 593 | #define CONFIG_SYS_FPGA_SLIC1_R_DPRAM_INT 0x20000000 | |
| 594 | #define CONFIG_SYS_FPGA_SLIC1_W_DPRAM_INT 0x10000000 | |
| 595 | #define CONFIG_SYS_FPGA_PHY0_INT 0x08000000 | |
| 596 | #define CONFIG_SYS_FPGA_PHY1_INT 0x04000000 | |
| 597 | #define CONFIG_SYS_FPGA_SLIC0_INT 0x02000000 | |
| 598 | #define CONFIG_SYS_FPGA_SLIC1_INT 0x01000000 | |
| 566806ca SR |
599 | |
| 600 | /* DPRAM setting */ | |
| 601 | /* 00: 32B; 01: 64B; 10: 128B; 11: 256B */ | |
| 6d0f6bcf JCPV |
602 | #define CONFIG_SYS_FPGA_DPRAM_R_INT_LINE 0x00400000 /* 64 B */ |
| 603 | #define CONFIG_SYS_FPGA_DPRAM_W_INT_LINE 0x00100000 /* 64 B */ | |
| 604 | #define CONFIG_SYS_FPGA_DPRAM_RW_TYPE 0x00080000 | |
| 605 | #define CONFIG_SYS_FPGA_DPRAM_RST 0x00040000 | |
| 606 | #define CONFIG_SYS_FPGA_UART0_FO 0x00020000 | |
| 607 | #define CONFIG_SYS_FPGA_UART1_FO 0x00010000 | |
| 566806ca SR |
608 | |
| 609 | /* loopback */ | |
| 6d0f6bcf JCPV |
610 | #define CONFIG_SYS_FPGA_CHIPSIDE_LOOPBACK 0x00004000 |
| 611 | #define CONFIG_SYS_FPGA_LINESIDE_LOOPBACK 0x00008000 | |
| 612 | #define CONFIG_SYS_FPGA_SLIC0_ENABLE 0x00002000 | |
| 613 | #define CONFIG_SYS_FPGA_SLIC1_ENABLE 0x00001000 | |
| 614 | #define CONFIG_SYS_FPGA_SLIC0_CS 0x00000800 | |
| 615 | #define CONFIG_SYS_FPGA_SLIC1_CS 0x00000400 | |
| 616 | #define CONFIG_SYS_FPGA_USER_LED0 0x00000200 | |
| 617 | #define CONFIG_SYS_FPGA_USER_LED1 0x00000100 | |
| 566806ca | 618 | |
| 9998b136 SR |
619 | #define CONFIG_SYS_FPGA_MAGIC_MASK 0xffff0000 |
| 620 | #define CONFIG_SYS_FPGA_MAGIC 0xabcd0000 | |
| 621 | #define CONFIG_SYS_FPGA_VER_MASK 0x0000ff00 | |
| 622 | ||
| 837c730b | 623 | #endif /* __CONFIG_H */ |