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566806ca | 1 | /* |
8a24c07b GE |
2 | * Copyright (c) 2008 Nuovation System Designs, LLC |
3 | * Grant Erickson <gerickson@nuovations.com> | |
4 | * | |
566806ca SR |
5 | * (C) Copyright 2007 |
6 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
7 | * | |
8 | * See file CREDITS for list of people who contributed to this | |
9 | * project. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of | |
14 | * the License, or (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
24 | * MA 02111-1307 USA | |
25 | */ | |
26 | ||
27 | /************************************************************************ | |
28 | * kilauea.h - configuration for AMCC Kilauea (405EX) | |
29 | ***********************************************************************/ | |
30 | ||
31 | #ifndef __CONFIG_H | |
32 | #define __CONFIG_H | |
33 | ||
34 | /*----------------------------------------------------------------------- | |
35 | * High Level Configuration Options | |
36 | *----------------------------------------------------------------------*/ | |
37 | #define CONFIG_KILAUEA 1 /* Board is Kilauea */ | |
38 | #define CONFIG_4xx 1 /* ... PPC4xx family */ | |
39 | #define CONFIG_405EX 1 /* Specifc 405EX support*/ | |
40 | #define CONFIG_SYS_CLK_FREQ 33333333 /* ext frequency to pll */ | |
41 | ||
490f2040 SR |
42 | /* |
43 | * Include common defines/options for all AMCC eval boards | |
44 | */ | |
45 | #define CONFIG_HOSTNAME kilauea | |
46 | #include "amcc-common.h" | |
47 | ||
566806ca SR |
48 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ |
49 | #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ | |
9998b136 | 50 | #define CONFIG_BOARD_TYPES |
353f2688 | 51 | #define CONFIG_BOARD_EMAC_COUNT |
566806ca SR |
52 | |
53 | /*----------------------------------------------------------------------- | |
54 | * Base addresses -- Note these are effective addresses where the | |
55 | * actual resources get mapped (not physical addresses) | |
56 | *----------------------------------------------------------------------*/ | |
6d0f6bcf JCPV |
57 | #define CONFIG_SYS_FLASH_BASE 0xFC000000 |
58 | #define CONFIG_SYS_NAND_ADDR 0xF8000000 | |
59 | #define CONFIG_SYS_FPGA_BASE 0xF0000000 | |
566806ca SR |
60 | |
61 | /*----------------------------------------------------------------------- | |
8a24c07b GE |
62 | * Initial RAM & Stack Pointer Configuration Options |
63 | * | |
64 | * There are traditionally three options for the primordial | |
65 | * (i.e. initial) stack usage on the 405-series: | |
66 | * | |
67 | * 1) On-chip Memory (OCM) (i.e. SRAM) | |
68 | * 2) Data cache | |
69 | * 3) SDRAM | |
70 | * | |
71 | * For the 405EX(r), there is no OCM, so we are left with (2) or (3) | |
72 | * the latter of which is less than desireable since it requires | |
73 | * setting up the SDRAM and ECC in assembly code. | |
74 | * | |
6d0f6bcf | 75 | * To use (2), define 'CONFIG_SYS_INIT_DCACHE_CS' to be an unused chip |
8a24c07b | 76 | * select on the External Bus Controller (EBC) and then select a |
6d0f6bcf JCPV |
77 | * value for 'CONFIG_SYS_INIT_RAM_ADDR' outside of the range of valid, |
78 | * physical SDRAM. Otherwise, undefine 'CONFIG_SYS_INIT_DCACHE_CS' and | |
79 | * select a value for 'CONFIG_SYS_INIT_RAM_ADDR' within the range of valid, | |
8a24c07b GE |
80 | * physical SDRAM to use (3). |
81 | *-----------------------------------------------------------------------*/ | |
82 | ||
6d0f6bcf | 83 | #define CONFIG_SYS_INIT_DCACHE_CS 4 |
8a24c07b | 84 | |
6d0f6bcf JCPV |
85 | #if defined(CONFIG_SYS_INIT_DCACHE_CS) |
86 | #define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_SDRAM_BASE + ( 1 << 30)) /* 1 GiB */ | |
8a24c07b | 87 | #else |
6d0f6bcf JCPV |
88 | #define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_SDRAM_BASE + (32 << 20)) /* 32 MiB */ |
89 | #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */ | |
8a24c07b | 90 | |
6d0f6bcf JCPV |
91 | #define CONFIG_SYS_INIT_RAM_END (4 << 10) /* 4 KiB */ |
92 | #define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */ | |
93 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
566806ca | 94 | |
8a24c07b GE |
95 | /* |
96 | * If the data cache is being used for the primordial stack and global | |
97 | * data area, the POST word must be placed somewhere else. The General | |
98 | * Purpose Timer (GPT) is unused by u-boot and the kernel and preserves | |
99 | * its compare and mask register contents across reset, so it is used | |
100 | * for the POST word. | |
101 | */ | |
102 | ||
6d0f6bcf JCPV |
103 | #if defined(CONFIG_SYS_INIT_DCACHE_CS) |
104 | # define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
800eb096 | 105 | # define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6) |
8a24c07b | 106 | #else |
6d0f6bcf JCPV |
107 | # define CONFIG_SYS_INIT_EXTRA_SIZE 16 |
108 | # define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_EXTRA_SIZE) | |
6d0f6bcf JCPV |
109 | # define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_INIT_RAM_ADDR |
110 | #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */ | |
566806ca SR |
111 | |
112 | /*----------------------------------------------------------------------- | |
113 | * Serial Port | |
114 | *----------------------------------------------------------------------*/ | |
6d0f6bcf | 115 | #define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */ |
550650dd | 116 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
566806ca | 117 | |
566806ca SR |
118 | /*----------------------------------------------------------------------- |
119 | * Environment | |
120 | *----------------------------------------------------------------------*/ | |
121 | #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) | |
5a1aceb0 | 122 | #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ |
566806ca | 123 | #else |
51bfee19 | 124 | #define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ |
0e8d1586 | 125 | #define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */ |
566806ca SR |
126 | #endif |
127 | ||
128 | /*----------------------------------------------------------------------- | |
129 | * FLASH related | |
130 | *----------------------------------------------------------------------*/ | |
6d0f6bcf | 131 | #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ |
00b1883a | 132 | #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ |
566806ca | 133 | |
6d0f6bcf JCPV |
134 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} |
135 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
136 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ | |
566806ca | 137 | |
6d0f6bcf JCPV |
138 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
139 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
566806ca | 140 | |
6d0f6bcf JCPV |
141 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ |
142 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ | |
566806ca | 143 | |
5a1aceb0 | 144 | #ifdef CONFIG_ENV_IS_IN_FLASH |
0e8d1586 | 145 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ |
6d0f6bcf | 146 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) |
0e8d1586 | 147 | #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ |
566806ca SR |
148 | |
149 | /* Address and size of Redundant Environment Sector */ | |
0e8d1586 JCPV |
150 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) |
151 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
5a1aceb0 | 152 | #endif /* CONFIG_ENV_IS_IN_FLASH */ |
566806ca | 153 | |
3d6cb3b2 SR |
154 | /* |
155 | * IPL (Initial Program Loader, integrated inside CPU) | |
156 | * Will load first 4k from NAND (SPL) into cache and execute it from there. | |
157 | * | |
158 | * SPL (Secondary Program Loader) | |
159 | * Will load special U-Boot version (NUB) from NAND and execute it. This SPL | |
160 | * has to fit into 4kByte. It sets up the CPU and configures the SDRAM | |
161 | * controller and the NAND controller so that the special U-Boot image can be | |
162 | * loaded from NAND to SDRAM. | |
163 | * | |
164 | * NUB (NAND U-Boot) | |
165 | * This NAND U-Boot (NUB) is a special U-Boot version which can be started | |
166 | * from RAM. Therefore it mustn't (re-)configure the SDRAM controller. | |
167 | * | |
ec724f88 SR |
168 | * On 405EX the SPL is copied to SDRAM before the NAND controller is |
169 | * set up. While still running from location 0xfffff000...0xffffffff the | |
170 | * NAND controller cannot be accessed since it is attached to CS0 too. | |
3d6cb3b2 | 171 | */ |
6d0f6bcf JCPV |
172 | #define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */ |
173 | #define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */ | |
174 | #define CONFIG_SYS_NAND_BOOT_SPL_DST 0x00800000 /* Copy SPL here */ | |
175 | #define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */ | |
176 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr */ | |
177 | #define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST) | |
3d6cb3b2 SR |
178 | |
179 | /* | |
180 | * Define the partitioning of the NAND chip (only RAM U-Boot is needed here) | |
181 | */ | |
6d0f6bcf JCPV |
182 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */ |
183 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */ | |
3d6cb3b2 SR |
184 | |
185 | /* | |
186 | * Now the NAND chip has to be defined (no autodetection used!) | |
187 | */ | |
6d0f6bcf JCPV |
188 | #define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */ |
189 | #define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */ | |
190 | #define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */ | |
191 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */ | |
192 | #define CONFIG_SYS_NAND_4_ADDR_CYCLE 1 /* Fourth addr used (>32MB) */ | |
193 | ||
194 | #define CONFIG_SYS_NAND_ECCSIZE 256 | |
195 | #define CONFIG_SYS_NAND_ECCBYTES 3 | |
196 | #define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE) | |
197 | #define CONFIG_SYS_NAND_OOBSIZE 16 | |
198 | #define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS) | |
199 | #define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7} | |
3d6cb3b2 | 200 | |
51bfee19 | 201 | #ifdef CONFIG_ENV_IS_IN_NAND |
3d6cb3b2 SR |
202 | /* |
203 | * For NAND booting the environment is embedded in the U-Boot image. Please take | |
204 | * look at the file board/amcc/sequoia/u-boot-nand.lds for details. | |
205 | */ | |
6d0f6bcf JCPV |
206 | #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE |
207 | #define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE) | |
0e8d1586 | 208 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) |
3d6cb3b2 SR |
209 | #endif |
210 | ||
211 | /*----------------------------------------------------------------------- | |
212 | * NAND FLASH | |
213 | *----------------------------------------------------------------------*/ | |
6d0f6bcf | 214 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
6d0f6bcf JCPV |
215 | #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS) |
216 | #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ | |
3d6cb3b2 | 217 | |
566806ca SR |
218 | /*----------------------------------------------------------------------- |
219 | * DDR SDRAM | |
220 | *----------------------------------------------------------------------*/ | |
6d0f6bcf | 221 | #define CONFIG_SYS_MBYTES_SDRAM (256) /* 256MB */ |
566806ca | 222 | |
f6b6c458 AG |
223 | /* |
224 | * CONFIG_PPC4xx_DDR_AUTOCALIBRATION | |
225 | * | |
226 | * Note: DDR Autocalibration Method_A scans the full range of possible PPC4xx | |
227 | * SDRAM Controller DDR autocalibration values and takes a lot longer | |
228 | * to run than Method_B. | |
229 | * (See the Method_A and Method_B algorithm discription in the file: | |
a47a12be | 230 | * arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c) |
f6b6c458 AG |
231 | * Define CONFIG_PPC4xx_DDR_METHOD_A to use DDR autocalibration Method_A |
232 | * | |
233 | * DDR Autocalibration Method_B is the default. | |
234 | */ | |
5b34691f | 235 | #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) |
f6b6c458 AG |
236 | #define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */ |
237 | #define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */ | |
238 | #undef CONFIG_PPC4xx_DDR_METHOD_A | |
5b34691f | 239 | #endif |
f6b6c458 | 240 | |
6d0f6bcf | 241 | #define CONFIG_SYS_SDRAM0_MB0CF_BASE (( 0 << 20) + CONFIG_SYS_SDRAM_BASE) |
8a24c07b GE |
242 | |
243 | /* DDR1/2 SDRAM Device Control Register Data Values */ | |
6d0f6bcf | 244 | #define CONFIG_SYS_SDRAM0_MB0CF ((CONFIG_SYS_SDRAM0_MB0CF_BASE >> 3) | \ |
8a24c07b GE |
245 | SDRAM_RXBAS_SDSZ_256MB | \ |
246 | SDRAM_RXBAS_SDAM_MODE7 | \ | |
247 | SDRAM_RXBAS_SDBE_ENABLE) | |
6d0f6bcf JCPV |
248 | #define CONFIG_SYS_SDRAM0_MB1CF SDRAM_RXBAS_SDBE_DISABLE |
249 | #define CONFIG_SYS_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE | |
250 | #define CONFIG_SYS_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE | |
251 | #define CONFIG_SYS_SDRAM0_MCOPT1 (SDRAM_MCOPT1_PMU_OPEN | \ | |
2e205084 GE |
252 | SDRAM_MCOPT1_8_BANKS | \ |
253 | SDRAM_MCOPT1_DDR2_TYPE | \ | |
254 | SDRAM_MCOPT1_QDEP | \ | |
255 | SDRAM_MCOPT1_DCOO_DISABLED) | |
6d0f6bcf JCPV |
256 | #define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000 |
257 | #define CONFIG_SYS_SDRAM0_MODT0 (SDRAM_MODT_EB0W_ENABLE | \ | |
2e205084 | 258 | SDRAM_MODT_EB0R_ENABLE) |
6d0f6bcf JCPV |
259 | #define CONFIG_SYS_SDRAM0_MODT1 0x00000000 |
260 | #define CONFIG_SYS_SDRAM0_CODT (SDRAM_CODT_RK0R_ON | \ | |
2e205084 GE |
261 | SDRAM_CODT_CKLZ_36OHM | \ |
262 | SDRAM_CODT_DQS_1_8_V_DDR2 | \ | |
263 | SDRAM_CODT_IO_NMODE) | |
6d0f6bcf JCPV |
264 | #define CONFIG_SYS_SDRAM0_RTR SDRAM_RTR_RINT_ENCODE(1560) |
265 | #define CONFIG_SYS_SDRAM0_INITPLR0 (SDRAM_INITPLR_ENABLE | \ | |
2e205084 GE |
266 | SDRAM_INITPLR_IMWT_ENCODE(80) | \ |
267 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP)) | |
6d0f6bcf | 268 | #define CONFIG_SYS_SDRAM0_INITPLR1 (SDRAM_INITPLR_ENABLE | \ |
2e205084 GE |
269 | SDRAM_INITPLR_IMWT_ENCODE(3) | \ |
270 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \ | |
271 | SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \ | |
272 | SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL)) | |
6d0f6bcf | 273 | #define CONFIG_SYS_SDRAM0_INITPLR2 (SDRAM_INITPLR_ENABLE | \ |
2e205084 GE |
274 | SDRAM_INITPLR_IMWT_ENCODE(2) | \ |
275 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ | |
276 | SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2) | \ | |
277 | SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL)) | |
6d0f6bcf | 278 | #define CONFIG_SYS_SDRAM0_INITPLR3 (SDRAM_INITPLR_ENABLE | \ |
2e205084 GE |
279 | SDRAM_INITPLR_IMWT_ENCODE(2) | \ |
280 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ | |
281 | SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3) | \ | |
282 | SDRAM_INITPLR_IMA_ENCODE(0)) | |
6d0f6bcf | 283 | #define CONFIG_SYS_SDRAM0_INITPLR4 (SDRAM_INITPLR_ENABLE | \ |
2e205084 GE |
284 | SDRAM_INITPLR_IMWT_ENCODE(2) | \ |
285 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ | |
286 | SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \ | |
287 | SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_DISABLE | \ | |
288 | JEDEC_MA_EMR_RTT_75OHM)) | |
6d0f6bcf | 289 | #define CONFIG_SYS_SDRAM0_INITPLR5 (SDRAM_INITPLR_ENABLE | \ |
2e205084 GE |
290 | SDRAM_INITPLR_IMWT_ENCODE(2) | \ |
291 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ | |
292 | SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \ | |
293 | SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \ | |
294 | JEDEC_MA_MR_CL_DDR2_4_0_CLK | \ | |
295 | JEDEC_MA_MR_BLEN_4 | \ | |
296 | JEDEC_MA_MR_DLL_RESET)) | |
6d0f6bcf | 297 | #define CONFIG_SYS_SDRAM0_INITPLR6 (SDRAM_INITPLR_ENABLE | \ |
2e205084 GE |
298 | SDRAM_INITPLR_IMWT_ENCODE(3) | \ |
299 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \ | |
300 | SDRAM_INITPLR_IBA_ENCODE(0x0) | \ | |
301 | SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL)) | |
6d0f6bcf | 302 | #define CONFIG_SYS_SDRAM0_INITPLR7 (SDRAM_INITPLR_ENABLE | \ |
2e205084 GE |
303 | SDRAM_INITPLR_IMWT_ENCODE(26) | \ |
304 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH)) | |
6d0f6bcf | 305 | #define CONFIG_SYS_SDRAM0_INITPLR8 (SDRAM_INITPLR_ENABLE | \ |
2e205084 GE |
306 | SDRAM_INITPLR_IMWT_ENCODE(26) | \ |
307 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH)) | |
6d0f6bcf | 308 | #define CONFIG_SYS_SDRAM0_INITPLR9 (SDRAM_INITPLR_ENABLE | \ |
2e205084 GE |
309 | SDRAM_INITPLR_IMWT_ENCODE(26) | \ |
310 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH)) | |
6d0f6bcf | 311 | #define CONFIG_SYS_SDRAM0_INITPLR10 (SDRAM_INITPLR_ENABLE | \ |
2e205084 GE |
312 | SDRAM_INITPLR_IMWT_ENCODE(26) | \ |
313 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH)) | |
6d0f6bcf | 314 | #define CONFIG_SYS_SDRAM0_INITPLR11 (SDRAM_INITPLR_ENABLE | \ |
2e205084 GE |
315 | SDRAM_INITPLR_IMWT_ENCODE(2) | \ |
316 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ | |
317 | SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \ | |
318 | SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \ | |
319 | JEDEC_MA_MR_CL_DDR2_4_0_CLK | \ | |
320 | JEDEC_MA_MR_BLEN_4)) | |
6d0f6bcf | 321 | #define CONFIG_SYS_SDRAM0_INITPLR12 (SDRAM_INITPLR_ENABLE | \ |
2e205084 GE |
322 | SDRAM_INITPLR_IMWT_ENCODE(2) | \ |
323 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ | |
324 | SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \ | |
325 | SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER | \ | |
326 | JEDEC_MA_EMR_RDQS_DISABLE | \ | |
327 | JEDEC_MA_EMR_DQS_DISABLE | \ | |
328 | JEDEC_MA_EMR_RTT_DISABLED | \ | |
329 | JEDEC_MA_EMR_ODS_NORMAL)) | |
6d0f6bcf | 330 | #define CONFIG_SYS_SDRAM0_INITPLR13 (SDRAM_INITPLR_ENABLE | \ |
2e205084 GE |
331 | SDRAM_INITPLR_IMWT_ENCODE(2) | \ |
332 | SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \ | |
333 | SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \ | |
334 | SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT | \ | |
335 | JEDEC_MA_EMR_RDQS_DISABLE | \ | |
336 | JEDEC_MA_EMR_DQS_DISABLE | \ | |
337 | JEDEC_MA_EMR_RTT_DISABLED | \ | |
338 | JEDEC_MA_EMR_ODS_NORMAL)) | |
6d0f6bcf JCPV |
339 | #define CONFIG_SYS_SDRAM0_INITPLR14 (SDRAM_INITPLR_DISABLE) |
340 | #define CONFIG_SYS_SDRAM0_INITPLR15 (SDRAM_INITPLR_DISABLE) | |
341 | #define CONFIG_SYS_SDRAM0_RQDC (SDRAM_RQDC_RQDE_ENABLE | \ | |
2e205084 | 342 | SDRAM_RQDC_RQFD_ENCODE(56)) |
6d0f6bcf JCPV |
343 | #define CONFIG_SYS_SDRAM0_RFDC SDRAM_RFDC_RFFD_ENCODE(521) |
344 | #define CONFIG_SYS_SDRAM0_RDCC (SDRAM_RDCC_RDSS_T2) | |
345 | #define CONFIG_SYS_SDRAM0_DLCR (SDRAM_DLCR_DCLM_AUTO | \ | |
2e205084 GE |
346 | SDRAM_DLCR_DLCS_CONT_DONE | \ |
347 | SDRAM_DLCR_DLCV_ENCODE(165)) | |
6d0f6bcf JCPV |
348 | #define CONFIG_SYS_SDRAM0_CLKTR (SDRAM_CLKTR_CLKP_180_DEG_ADV) |
349 | #define CONFIG_SYS_SDRAM0_WRDTR 0x00000000 | |
350 | #define CONFIG_SYS_SDRAM0_SDTR1 (SDRAM_SDTR1_LDOF_2_CLK | \ | |
2e205084 GE |
351 | SDRAM_SDTR1_RTW_2_CLK | \ |
352 | SDRAM_SDTR1_RTRO_1_CLK) | |
6d0f6bcf | 353 | #define CONFIG_SYS_SDRAM0_SDTR2 (SDRAM_SDTR2_RCD_3_CLK | \ |
2e205084 GE |
354 | SDRAM_SDTR2_WTR_2_CLK | \ |
355 | SDRAM_SDTR2_XSNR_32_CLK | \ | |
356 | SDRAM_SDTR2_WPC_4_CLK | \ | |
357 | SDRAM_SDTR2_RPC_2_CLK | \ | |
358 | SDRAM_SDTR2_RP_3_CLK | \ | |
359 | SDRAM_SDTR2_RRD_2_CLK) | |
6d0f6bcf | 360 | #define CONFIG_SYS_SDRAM0_SDTR3 (SDRAM_SDTR3_RAS_ENCODE(8) | \ |
2e205084 GE |
361 | SDRAM_SDTR3_RC_ENCODE(11) | \ |
362 | SDRAM_SDTR3_XCS | \ | |
363 | SDRAM_SDTR3_RFC_ENCODE(26)) | |
6d0f6bcf | 364 | #define CONFIG_SYS_SDRAM0_MMODE (SDRAM_MMODE_WR_DDR2_3_CYC | \ |
2e205084 GE |
365 | SDRAM_MMODE_DCL_DDR2_4_0_CLK | \ |
366 | SDRAM_MMODE_BLEN_4) | |
6d0f6bcf | 367 | #define CONFIG_SYS_SDRAM0_MEMODE (SDRAM_MEMODE_DQS_DISABLE | \ |
2e205084 | 368 | SDRAM_MEMODE_RTT_75OHM) |
8a24c07b | 369 | |
566806ca SR |
370 | /*----------------------------------------------------------------------- |
371 | * I2C | |
372 | *----------------------------------------------------------------------*/ | |
6d0f6bcf | 373 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
566806ca | 374 | |
6d0f6bcf JCPV |
375 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* I2C boot EEPROM (24C02BN) */ |
376 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ | |
f6af8ce0 SR |
377 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 |
378 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
566806ca | 379 | |
4b1389e0 SR |
380 | /* I2C bootstrap EEPROM */ |
381 | #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52 | |
382 | #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0 | |
383 | #define CONFIG_4xx_CONFIG_BLOCKSIZE 16 | |
384 | ||
566806ca SR |
385 | /* Standard DTT sensor configuration */ |
386 | #define CONFIG_DTT_DS1775 1 | |
387 | #define CONFIG_DTT_SENSORS { 0 } | |
6d0f6bcf | 388 | #define CONFIG_SYS_I2C_DTT_ADDR 0x48 |
566806ca SR |
389 | |
390 | /* RTC configuration */ | |
391 | #define CONFIG_RTC_DS1338 1 | |
6d0f6bcf | 392 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
566806ca SR |
393 | |
394 | /*----------------------------------------------------------------------- | |
395 | * Ethernet | |
396 | *----------------------------------------------------------------------*/ | |
397 | #define CONFIG_M88E1111_PHY 1 | |
398 | #define CONFIG_IBM_EMAC4_V4 1 | |
1740c1bf | 399 | #define CONFIG_EMAC_PHY_MODE EMAC_PHY_MODE_RGMII_RGMII |
566806ca SR |
400 | #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ |
401 | ||
402 | #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ | |
403 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
404 | ||
405 | #define CONFIG_HAS_ETH0 1 | |
406 | ||
566806ca SR |
407 | #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ |
408 | #define CONFIG_PHY1_ADDR 2 | |
409 | ||
f6b6c458 AG |
410 | /* Debug messages for the DDR autocalibration */ |
411 | #define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */ | |
412 | ||
490f2040 SR |
413 | /* |
414 | * Default environment variables | |
415 | */ | |
566806ca | 416 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
490f2040 SR |
417 | CONFIG_AMCC_DEF_ENV \ |
418 | CONFIG_AMCC_DEF_ENV_POWERPC \ | |
419 | CONFIG_AMCC_DEF_ENV_PPC_OLD \ | |
420 | CONFIG_AMCC_DEF_ENV_NOR_UPD \ | |
421 | CONFIG_AMCC_DEF_ENV_NAND_UPD \ | |
566806ca | 422 | "logversion=2\0" \ |
566806ca | 423 | "kernel_addr=fc000000\0" \ |
64e541f4 | 424 | "fdt_addr=fc1e0000\0" \ |
566806ca | 425 | "ramdisk_addr=fc200000\0" \ |
566806ca | 426 | "pciconfighost=1\0" \ |
d4cb2d17 | 427 | "pcie_mode=RP:RP\0" \ |
566806ca | 428 | "" |
566806ca SR |
429 | |
430 | /* | |
490f2040 | 431 | * Commands additional to the ones defined in amcc-common.h |
566806ca | 432 | */ |
4b1389e0 | 433 | #define CONFIG_CMD_CHIP_CONFIG |
566806ca | 434 | #define CONFIG_CMD_DATE |
566806ca | 435 | #define CONFIG_CMD_LOG |
566806ca | 436 | #define CONFIG_CMD_NAND |
566806ca | 437 | #define CONFIG_CMD_PCI |
afe9fa59 | 438 | #define CONFIG_CMD_SNTP |
566806ca | 439 | |
dd7c3020 SR |
440 | /* |
441 | * Don't run the memory POST on the NAND-booting version. It will | |
442 | * overwrite part of the U-Boot image which is already loaded from NAND | |
443 | * to SDRAM. | |
444 | */ | |
445 | #if defined(CONFIG_NAND_U_BOOT) | |
446 | #define CONFIG_SYS_POST_MEMORY_ON 0 | |
447 | #else | |
448 | #define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY | |
449 | #endif | |
450 | ||
566806ca | 451 | /* POST support */ |
6d0f6bcf JCPV |
452 | #define CONFIG_POST (CONFIG_SYS_POST_CACHE | \ |
453 | CONFIG_SYS_POST_CPU | \ | |
454 | CONFIG_SYS_POST_ETHER | \ | |
455 | CONFIG_SYS_POST_I2C | \ | |
dd7c3020 | 456 | CONFIG_SYS_POST_MEMORY_ON | \ |
6d0f6bcf | 457 | CONFIG_SYS_POST_UART) |
566806ca SR |
458 | |
459 | /* Define here the base-addresses of the UARTs to test in POST */ | |
6d0f6bcf | 460 | #define CONFIG_SYS_POST_UART_TABLE {UART0_BASE, UART1_BASE} |
566806ca SR |
461 | |
462 | #define CONFIG_LOGBUFFER | |
6d0f6bcf | 463 | #define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */ |
566806ca | 464 | |
6d0f6bcf | 465 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ |
566806ca | 466 | |
566806ca SR |
467 | /*----------------------------------------------------------------------- |
468 | * PCI stuff | |
469 | *----------------------------------------------------------------------*/ | |
470 | #define CONFIG_PCI /* include pci support */ | |
471 | #define CONFIG_PCI_PNP 1 /* do pci plug-and-play */ | |
472 | #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ | |
473 | #define CONFIG_PCI_CONFIG_HOST_BRIDGE | |
474 | ||
475 | /*----------------------------------------------------------------------- | |
476 | * PCIe stuff | |
477 | *----------------------------------------------------------------------*/ | |
6d0f6bcf JCPV |
478 | #define CONFIG_SYS_PCIE_MEMBASE 0x90000000 /* mapped PCIe memory */ |
479 | #define CONFIG_SYS_PCIE_MEMSIZE 0x08000000 /* 128 Meg, smallest incr per port */ | |
566806ca | 480 | |
6d0f6bcf JCPV |
481 | #define CONFIG_SYS_PCIE0_CFGBASE 0xa0000000 /* remote access */ |
482 | #define CONFIG_SYS_PCIE0_XCFGBASE 0xb0000000 /* local access */ | |
483 | #define CONFIG_SYS_PCIE0_CFGMASK 0xe0000001 /* 512 Meg */ | |
566806ca | 484 | |
6d0f6bcf JCPV |
485 | #define CONFIG_SYS_PCIE1_CFGBASE 0xc0000000 /* remote access */ |
486 | #define CONFIG_SYS_PCIE1_XCFGBASE 0xd0000000 /* local access */ | |
487 | #define CONFIG_SYS_PCIE1_CFGMASK 0xe0000001 /* 512 Meg */ | |
566806ca | 488 | |
6d0f6bcf JCPV |
489 | #define CONFIG_SYS_PCIE0_UTLBASE 0xef502000 |
490 | #define CONFIG_SYS_PCIE1_UTLBASE 0xef503000 | |
566806ca SR |
491 | |
492 | /* base address of inbound PCIe window */ | |
6d0f6bcf | 493 | #define CONFIG_SYS_PCIE_INBOUND_BASE 0x0000000000000000ULL |
566806ca | 494 | |
566806ca SR |
495 | /*----------------------------------------------------------------------- |
496 | * External Bus Controller (EBC) Setup | |
497 | *----------------------------------------------------------------------*/ | |
3d6cb3b2 SR |
498 | #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) |
499 | /* booting from NAND, so NAND chips select has to be on CS 0 */ | |
6d0f6bcf | 500 | #define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */ |
3d6cb3b2 SR |
501 | |
502 | /* Memory Bank 1 (NOR-FLASH) initialization */ | |
6d0f6bcf JCPV |
503 | #define CONFIG_SYS_EBC_PB1AP 0x05806500 |
504 | #define CONFIG_SYS_EBC_PB1CR 0xFC0DA000 /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/ | |
3d6cb3b2 SR |
505 | |
506 | /* Memory Bank 0 (NAND-FLASH) initialization */ | |
6d0f6bcf JCPV |
507 | #define CONFIG_SYS_EBC_PB0AP 0x018003c0 |
508 | #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1e000) | |
3d6cb3b2 | 509 | #else |
6d0f6bcf | 510 | #define CONFIG_SYS_NAND_CS 1 /* NAND chip connected to CSx */ |
566806ca SR |
511 | |
512 | /* Memory Bank 0 (NOR-FLASH) initialization */ | |
6d0f6bcf JCPV |
513 | #define CONFIG_SYS_EBC_PB0AP 0x05806500 |
514 | #define CONFIG_SYS_EBC_PB0CR 0xFC0DA000 /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/ | |
566806ca SR |
515 | |
516 | /* Memory Bank 1 (NAND-FLASH) initialization */ | |
6d0f6bcf JCPV |
517 | #define CONFIG_SYS_EBC_PB1AP 0x018003c0 |
518 | #define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_NAND_ADDR | 0x1e000) | |
3d6cb3b2 | 519 | #endif |
566806ca | 520 | |
9998b136 SR |
521 | /* Memory Bank 2 (FPGA) initialization */ |
522 | #define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_ENABLED | \ | |
523 | EBC_BXAP_FWT_ENCODE(6) | \ | |
524 | EBC_BXAP_BWT_ENCODE(1) | \ | |
525 | EBC_BXAP_BCE_DISABLE | \ | |
526 | EBC_BXAP_BCT_2TRANS | \ | |
527 | EBC_BXAP_CSN_ENCODE(0) | \ | |
528 | EBC_BXAP_OEN_ENCODE(0) | \ | |
529 | EBC_BXAP_WBN_ENCODE(3) | \ | |
530 | EBC_BXAP_WBF_ENCODE(1) | \ | |
531 | EBC_BXAP_TH_ENCODE(4) | \ | |
532 | EBC_BXAP_RE_DISABLED | \ | |
533 | EBC_BXAP_SOR_DELAYED | \ | |
534 | EBC_BXAP_BEM_WRITEONLY | \ | |
535 | EBC_BXAP_PEN_DISABLED) | |
536 | #define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA_BASE | 0x18000) | |
566806ca | 537 | |
6d0f6bcf | 538 | #define CONFIG_SYS_EBC_CFG 0x7FC00000 /* EBC0_CFG */ |
566806ca | 539 | |
566806ca SR |
540 | /*----------------------------------------------------------------------- |
541 | * GPIO Setup | |
542 | *----------------------------------------------------------------------*/ | |
6d0f6bcf | 543 | #define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ |
9ea61b57 SR |
544 | { \ |
545 | /* GPIO Core 0 */ \ | |
546 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO0 EBC_DATA_PAR(0) */ \ | |
547 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO1 EBC_DATA_PAR(1) */ \ | |
548 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO2 EBC_DATA_PAR(2) */ \ | |
549 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO3 EBC_DATA_PAR(3) */ \ | |
550 | {GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO4 EBC_DATA(20) USB2_DATA(4) */ \ | |
551 | {GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO5 EBC_DATA(21) USB2_DATA(5) */ \ | |
552 | {GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO6 EBC_DATA(22) USB2_DATA(6) */ \ | |
553 | {GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO7 EBC_DATA(23) USB2_DATA(7) */ \ | |
8be76090 SR |
554 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 CS(1)/NFCE(1) IRQ(7) */ \ |
555 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 CS(2)/NFCE(2) IRQ(8) */ \ | |
556 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 CS(3)/NFCE(3) IRQ(9) */ \ | |
9ea61b57 SR |
557 | {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 IRQ(6) */ \ |
558 | {GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO12 EBC_DATA(16) USB2_DATA(0) */ \ | |
559 | {GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO13 EBC_DATA(17) USB2_DATA(1) */ \ | |
7cfc12a7 SR |
560 | {GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO14 EBC_DATA(18) USB2_DATA(2) */ \ |
561 | {GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO15 EBC_DATA(19) USB2_DATA(3) */ \ | |
9ea61b57 | 562 | {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 UART0_DCD UART1_CTS */ \ |
8be76090 | 563 | {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 UART0_DSR UART1_RTS */ \ |
9ea61b57 SR |
564 | {GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 UART0_CTS */ \ |
565 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 UART0_RTS */ \ | |
566 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO20 UART0_DTR UART1_TX */ \ | |
567 | {GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0}, /* GPIO21 UART0_RI UART1_RX */ \ | |
568 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO22 EBC_HOLD_REQ DMA_ACK2 */ \ | |
569 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO23 EBC_HOLD_ACK DMA_REQ2 */ \ | |
570 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO24 EBC_EXT_REQ DMA_EOT2 IRQ(4) */ \ | |
571 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO25 EBC_EXT_ACK DMA_ACK3 IRQ(3) */ \ | |
572 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 EBC_ADDR(5) DMA_EOT0 TS(3) */ \ | |
573 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO27 EBC_BUS_REQ DMA_EOT3 IRQ(5) */ \ | |
574 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO28 */ \ | |
8be76090 SR |
575 | {GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0}, /* GPIO29 DMA_EOT1 IRQ(2) */ \ |
576 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO30 DMA_REQ1 IRQ(1) */ \ | |
577 | {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO31 DMA_ACK1 IRQ(0) */ \ | |
9ea61b57 SR |
578 | } \ |
579 | } | |
566806ca | 580 | |
566806ca SR |
581 | /*----------------------------------------------------------------------- |
582 | * Some Kilauea stuff..., mainly fpga registers | |
583 | */ | |
6d0f6bcf | 584 | #define CONFIG_SYS_FPGA_REG_BASE CONFIG_SYS_FPGA_BASE |
9998b136 | 585 | #define CONFIG_SYS_FPGA_FIFO_BASE (CONFIG_SYS_FPGA_BASE | (1 << 10)) |
566806ca SR |
586 | |
587 | /* interrupt */ | |
6d0f6bcf JCPV |
588 | #define CONFIG_SYS_FPGA_SLIC0_R_DPRAM_INT 0x80000000 |
589 | #define CONFIG_SYS_FPGA_SLIC0_W_DPRAM_INT 0x40000000 | |
590 | #define CONFIG_SYS_FPGA_SLIC1_R_DPRAM_INT 0x20000000 | |
591 | #define CONFIG_SYS_FPGA_SLIC1_W_DPRAM_INT 0x10000000 | |
592 | #define CONFIG_SYS_FPGA_PHY0_INT 0x08000000 | |
593 | #define CONFIG_SYS_FPGA_PHY1_INT 0x04000000 | |
594 | #define CONFIG_SYS_FPGA_SLIC0_INT 0x02000000 | |
595 | #define CONFIG_SYS_FPGA_SLIC1_INT 0x01000000 | |
566806ca SR |
596 | |
597 | /* DPRAM setting */ | |
598 | /* 00: 32B; 01: 64B; 10: 128B; 11: 256B */ | |
6d0f6bcf JCPV |
599 | #define CONFIG_SYS_FPGA_DPRAM_R_INT_LINE 0x00400000 /* 64 B */ |
600 | #define CONFIG_SYS_FPGA_DPRAM_W_INT_LINE 0x00100000 /* 64 B */ | |
601 | #define CONFIG_SYS_FPGA_DPRAM_RW_TYPE 0x00080000 | |
602 | #define CONFIG_SYS_FPGA_DPRAM_RST 0x00040000 | |
603 | #define CONFIG_SYS_FPGA_UART0_FO 0x00020000 | |
604 | #define CONFIG_SYS_FPGA_UART1_FO 0x00010000 | |
566806ca SR |
605 | |
606 | /* loopback */ | |
6d0f6bcf JCPV |
607 | #define CONFIG_SYS_FPGA_CHIPSIDE_LOOPBACK 0x00004000 |
608 | #define CONFIG_SYS_FPGA_LINESIDE_LOOPBACK 0x00008000 | |
609 | #define CONFIG_SYS_FPGA_SLIC0_ENABLE 0x00002000 | |
610 | #define CONFIG_SYS_FPGA_SLIC1_ENABLE 0x00001000 | |
611 | #define CONFIG_SYS_FPGA_SLIC0_CS 0x00000800 | |
612 | #define CONFIG_SYS_FPGA_SLIC1_CS 0x00000400 | |
613 | #define CONFIG_SYS_FPGA_USER_LED0 0x00000200 | |
614 | #define CONFIG_SYS_FPGA_USER_LED1 0x00000100 | |
566806ca | 615 | |
9998b136 SR |
616 | #define CONFIG_SYS_FPGA_MAGIC_MASK 0xffff0000 |
617 | #define CONFIG_SYS_FPGA_MAGIC 0xabcd0000 | |
618 | #define CONFIG_SYS_FPGA_VER_MASK 0x0000ff00 | |
619 | ||
837c730b | 620 | #endif /* __CONFIG_H */ |