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af895e45 | 1 | /* |
bae5407d | 2 | * (C) Copyright 2007-2011 |
af895e45 HS |
3 | * Heiko Schocher, DENX Software Engineering, hs@denx.de. |
4 | * | |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
af895e45 HS |
6 | */ |
7 | ||
bae5407d GF |
8 | #ifndef __CONFIG_H |
9 | #define __CONFIG_H | |
af895e45 HS |
10 | |
11 | /* | |
12 | * High Level Configuration Options | |
13 | * (easy to change) | |
14 | */ | |
489337f5 | 15 | |
af895e45 | 16 | #define CONFIG_MPC8247 |
b83cf848 GF |
17 | /* MGCOGE */ |
18 | #if defined(CONFIG_MGCOGE) | |
19 | #define CONFIG_HOSTNAME mgcoge | |
20 | #define CONFIG_KM_BOARD_EXTRA_ENV "" | |
21 | ||
22 | /* MGCOGE3NE */ | |
23 | #elif defined(CONFIG_MGCOGE3NE) | |
489337f5 HB |
24 | #define CONFIG_HOSTNAME mgcoge3ne |
25 | #define CONFIG_KM_82XX | |
bae5407d | 26 | #define CONFIG_KM_BOARD_EXTRA_ENV "bobcatreset=true\0" |
af895e45 | 27 | |
b83cf848 GF |
28 | #else |
29 | #error ("Board unsupported") | |
30 | #endif | |
31 | ||
a0744285 VL |
32 | #define CONFIG_DISPLAY_BOARDINFO |
33 | ||
af895e45 HS |
34 | #define CONFIG_SYS_TEXT_BASE 0xFE000000 |
35 | ||
2973b098 VL |
36 | #define CONFIG_MISC_INIT_R |
37 | ||
af895e45 | 38 | /* include common defines/options for all Keymile boards */ |
264eaa0e VL |
39 | #include "km/keymile-common.h" |
40 | #include "km/km-powerpc.h" | |
af895e45 HS |
41 | |
42 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
43 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 | |
44 | #define CONFIG_SYS_FLASH_SIZE 32 | |
45 | #define CONFIG_SYS_FLASH_CFI | |
46 | #define CONFIG_FLASH_CFI_DRIVER | |
b83cf848 GF |
47 | |
48 | /* MGCOGE */ | |
49 | #if defined(CONFIG_MGCOGE) | |
50 | #define CONFIG_SYS_MAX_FLASH_BANKS 3 | |
51 | /* max num of sects on one chip */ | |
52 | #define CONFIG_SYS_MAX_FLASH_SECT 512 | |
53 | ||
54 | #define CONFIG_SYS_FLASH_BASE_1 0x50000000 | |
55 | #define CONFIG_SYS_FLASH_SIZE_1 32 | |
56 | #define CONFIG_SYS_FLASH_BASE_2 0x52000000 | |
57 | #define CONFIG_SYS_FLASH_SIZE_2 32 | |
58 | ||
59 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \ | |
60 | CONFIG_SYS_FLASH_BASE_1, \ | |
61 | CONFIG_SYS_FLASH_BASE_2 } | |
62 | #define MTDIDS_DEFAULT "nor3=app" | |
63 | ||
64 | /* | |
65 | * Bank 1 - 60x bus SDRAM | |
66 | */ | |
67 | #define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ | |
68 | #define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (256 << 20) /* less than 256 MB */ | |
69 | ||
70 | /* SDRAM initialization values | |
71 | */ | |
72 | ||
73 | #define CONFIG_SYS_OR1 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & \ | |
74 | ORxS_SDAM_MSK) |\ | |
75 | ORxS_BPD_8 |\ | |
76 | ORxS_ROWST_PBI0_A7 |\ | |
77 | ORxS_NUMR_13) | |
78 | ||
79 | #define CONFIG_SYS_PSDMR ( \ | |
80 | PSDMR_SDAM_A14_IS_A5 |\ | |
81 | PSDMR_BSMA_A14_A16 |\ | |
82 | PSDMR_SDA10_PBI0_A9 |\ | |
83 | PSDMR_RFRC_5_CLK |\ | |
84 | PSDMR_PRETOACT_2W |\ | |
85 | PSDMR_ACTTORW_2W |\ | |
86 | PSDMR_LDOTOPRE_1C |\ | |
87 | PSDMR_WRC_1C |\ | |
88 | PSDMR_CL_2) | |
89 | ||
90 | /* MGCOGE3NE */ | |
91 | #elif defined(CONFIG_MGCOGE3NE) | |
489337f5 HB |
92 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */ |
93 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* | |
af895e45 HS |
94 | * max num of sects on one |
95 | * chip | |
96 | */ | |
97 | ||
98 | #define CONFIG_SYS_FLASH_BASE_1 0x50000000 | |
489337f5 HB |
99 | #define CONFIG_SYS_FLASH_SIZE_1 128 |
100 | ||
101 | #define CONFIG_SYS_FLASH_SIZE_2 0 /* dummy value to calc SYS_OR5 */ | |
af895e45 HS |
102 | |
103 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \ | |
104 | CONFIG_SYS_FLASH_BASE_1 } | |
105 | ||
106 | #define MTDIDS_DEFAULT "nor2=app" | |
107 | ||
489337f5 HB |
108 | /* |
109 | * Bank 1 - 60x bus SDRAM | |
c9718210 GF |
110 | * mgcoge3ne has 256MB |
111 | * mgcoge2ne has 128MB | |
489337f5 HB |
112 | */ |
113 | #define SDRAM_MAX_SIZE 0x10000000 /* max. 256 MB */ | |
114 | #define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (512 << 20) /* less than 512 MB */ | |
115 | ||
bae5407d GF |
116 | #define CONFIG_SYS_OR1 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & \ |
117 | ORxS_SDAM_MSK) |\ | |
489337f5 | 118 | ORxS_BPD_4 |\ |
56249fea GF |
119 | ORxS_NUMR_13 |\ |
120 | ORxS_IBID) | |
489337f5 | 121 | |
bae5407d GF |
122 | #define CONFIG_SYS_PSDMR ( \ |
123 | PSDMR_PBI |\ | |
56249fea | 124 | PSDMR_RFEN |\ |
bae5407d | 125 | PSDMR_BSMA_A13_A15 |\ |
bae5407d GF |
126 | PSDMR_RFRC_5_CLK |\ |
127 | PSDMR_PRETOACT_2W |\ | |
128 | PSDMR_ACTTORW_2W |\ | |
129 | PSDMR_LDOTOPRE_1C |\ | |
56249fea | 130 | PSDMR_WRC_1C |\ |
489337f5 | 131 | PSDMR_CL_2) |
c9718210 GF |
132 | |
133 | #define CONFIG_SYS_SDRAM_LIST { \ | |
134 | { .size = 256 << 20, \ | |
135 | .or1 = ORxS_ROWST_PBI1_A4, \ | |
136 | .psdmr = PSDMR_SDAM_A17_IS_A5 | PSDMR_SDA10_PBI1_A6, \ | |
137 | }, \ | |
138 | { .size = 128 << 20, \ | |
139 | .or1 = ORxS_ROWST_PBI1_A5, \ | |
140 | .psdmr = PSDMR_SDAM_A16_IS_A5 | PSDMR_SDA10_PBI1_A7, \ | |
141 | }, \ | |
142 | } | |
b83cf848 | 143 | #endif /* defined(CONFIG_MGCOGE3NE) */ |
489337f5 | 144 | |
af895e45 | 145 | /* include further common stuff for all keymile 82xx boards */ |
65c7f923 GF |
146 | /* |
147 | * Select serial console configuration | |
148 | * | |
149 | * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then | |
150 | * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 | |
151 | * for SCC). | |
152 | */ | |
153 | #define CONFIG_CONS_ON_SMC /* Console is on SMC */ | |
154 | #undef CONFIG_CONS_ON_SCC /* It's not on SCC */ | |
155 | #undef CONFIG_CONS_NONE /* It's not on external UART */ | |
156 | #define CONFIG_CONS_INDEX 2 /* SMC2 is used for console */ | |
157 | #define CONFIG_SYS_SMC_RXBUFLEN 128 | |
158 | #define CONFIG_SYS_MAXIDLE 10 | |
159 | ||
160 | /* | |
161 | * Select ethernet configuration | |
162 | * | |
163 | * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, | |
164 | * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for | |
165 | * SCC, 1-3 for FCC) | |
166 | * | |
167 | * If CONFIG_ETHER_NONE is defined, then either the ethernet routines | |
168 | * must be defined elsewhere (as for the console), or CONFIG_CMD_NET | |
169 | * must be unset. | |
170 | */ | |
171 | #define CONFIG_ETHER_ON_SCC /* Ethernet is on SCC */ | |
172 | #undef CONFIG_ETHER_ON_FCC /* Ethernet is not on FCC */ | |
173 | #undef CONFIG_ETHER_NONE /* No external Ethernet */ | |
174 | ||
175 | #define CONFIG_ETHER_INDEX 4 | |
176 | #define CONFIG_HAS_ETH0 | |
177 | #define CONFIG_SYS_SCC_TOUT_LOOP 10000000 | |
178 | ||
179 | #define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8) | |
180 | ||
181 | #ifndef CONFIG_8260_CLKIN | |
182 | #define CONFIG_8260_CLKIN 66000000 /* in Hz */ | |
183 | #endif | |
184 | ||
185 | #define BOOTFLASH_START 0xFE000000 | |
186 | ||
187 | #define CONFIG_KM_CONSOLE_TTY "ttyCPM0" | |
188 | ||
189 | #define MTDPARTS_DEFAULT "mtdparts=" \ | |
190 | "app:" \ | |
191 | "768k(u-boot)," \ | |
192 | "128k(env)," \ | |
193 | "128k(envred)," \ | |
194 | "3072k(free)," \ | |
195 | "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ")" | |
196 | ||
197 | /* | |
198 | * Default environment settings | |
199 | */ | |
200 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
201 | CONFIG_KM_BOARD_EXTRA_ENV \ | |
202 | CONFIG_KM_DEF_ENV \ | |
65c7f923 GF |
203 | "unlock=yes\0" \ |
204 | "newenv=" \ | |
205 | "prot off 0xFE0C0000 +0x40000 && " \ | |
206 | "era 0xFE0C0000 +0x40000\0" \ | |
207 | "arch=ppc_82xx\0" \ | |
208 | "" | |
209 | ||
210 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE | |
65c7f923 GF |
211 | |
212 | #define CONFIG_SYS_MONITOR_LEN (768 << 10) | |
213 | ||
214 | #define CONFIG_ENV_IS_IN_FLASH | |
215 | ||
216 | #ifdef CONFIG_ENV_IS_IN_FLASH | |
217 | #define CONFIG_ENV_SECT_SIZE 0x20000 | |
218 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ | |
219 | CONFIG_SYS_MONITOR_LEN) | |
220 | #define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN | |
221 | ||
222 | /* Address and size of Redundant Environment Sector */ | |
223 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ | |
224 | CONFIG_ENV_SECT_SIZE) | |
225 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
226 | #endif /* CONFIG_ENV_IS_IN_FLASH */ | |
227 | ||
228 | /* enable I2C and select the hardware/software driver */ | |
ea818dbb HS |
229 | #define CONFIG_SYS_I2C |
230 | #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ | |
0a4f88b9 | 231 | #define CONFIG_SYS_I2C_INIT_BOARD |
ea818dbb HS |
232 | #define CONFIG_SYS_NUM_I2C_BUSES 3 |
233 | #define CONFIG_SYS_I2C_MAX_HOPS 1 | |
234 | #define CONFIG_SYS_I2C_SOFT_SPEED 50000 | |
235 | #define CONFIG_SYS_I2C_SPEED CONFIG_SYS_I2C_SOFT_SPEED | |
236 | #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F | |
237 | #define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ | |
238 | {0, {{I2C_MUX_PCA9542, 0x70, 0} } }, \ | |
239 | {0, {{I2C_MUX_PCA9542, 0x70, 1} } } } | |
65c7f923 | 240 | |
f3e93617 | 241 | #define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/ |
0a4f88b9 | 242 | #define CONFIG_KM_I2C_ABORT |
65c7f923 GF |
243 | |
244 | /* | |
245 | * Software (bit-bang) I2C driver configuration | |
246 | */ | |
247 | ||
248 | #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ | |
249 | #define I2C_ACTIVE (iop->pdir |= 0x00010000) | |
250 | #define I2C_TRISTATE (iop->pdir &= ~0x00010000) | |
251 | #define I2C_READ ((iop->pdat & 0x00010000) != 0) | |
252 | #define I2C_SDA(bit) do { \ | |
253 | if (bit) \ | |
254 | iop->pdat |= 0x00010000; \ | |
255 | else \ | |
256 | iop->pdat &= ~0x00010000; \ | |
257 | } while (0) | |
258 | #define I2C_SCL(bit) do { \ | |
259 | if (bit) \ | |
260 | iop->pdat |= 0x00020000; \ | |
261 | else \ | |
262 | iop->pdat &= ~0x00020000; \ | |
263 | } while (0) | |
264 | #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ | |
265 | ||
266 | #ifndef __ASSEMBLY__ | |
267 | void set_sda(int state); | |
268 | void set_scl(int state); | |
269 | int get_sda(void); | |
270 | int get_scl(void); | |
271 | #endif | |
272 | ||
273 | /* I2C SYSMON (LM75, AD7414 is almost compatible) */ | |
274 | #define CONFIG_DTT_LM75 /* ON Semi's LM75 */ | |
275 | #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ | |
276 | #define CONFIG_SYS_DTT_MAX_TEMP 70 | |
65c7f923 | 277 | #define CONFIG_SYS_DTT_HYSTERESIS 3 |
ea818dbb | 278 | #define CONFIG_SYS_DTT_BUS_NUM 2 |
65c7f923 GF |
279 | |
280 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
281 | ||
282 | #define CONFIG_SYS_IMMR 0xF0000000 | |
283 | ||
284 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR | |
285 | #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* used size in DPRAM */ | |
286 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ | |
287 | GENERATED_GBL_DATA_SIZE) | |
288 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
289 | ||
290 | /* Hard reset configuration word */ | |
291 | #define CONFIG_SYS_HRCW_MASTER 0x0604b211 | |
292 | ||
293 | /* No slaves */ | |
294 | #define CONFIG_SYS_HRCW_SLAVE1 0 | |
295 | #define CONFIG_SYS_HRCW_SLAVE2 0 | |
296 | #define CONFIG_SYS_HRCW_SLAVE3 0 | |
297 | #define CONFIG_SYS_HRCW_SLAVE4 0 | |
298 | #define CONFIG_SYS_HRCW_SLAVE5 0 | |
299 | #define CONFIG_SYS_HRCW_SLAVE6 0 | |
300 | #define CONFIG_SYS_HRCW_SLAVE7 0 | |
301 | ||
302 | /* Initial Memory map for Linux */ | |
303 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) | |
304 | ||
305 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */ | |
306 | #if defined(CONFIG_CMD_KGDB) | |
307 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ | |
308 | #endif | |
309 | ||
310 | #define CONFIG_SYS_HID0_INIT 0 | |
311 | #define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE) | |
312 | ||
313 | #define CONFIG_SYS_HID2 0 | |
314 | ||
315 | #define CONFIG_SYS_SIUMCR 0x4020c200 | |
316 | #define CONFIG_SYS_SYPCR 0xFFFFFF83 | |
317 | #define CONFIG_SYS_BCR 0x10000000 | |
318 | #define CONFIG_SYS_SCCR (SCCR_PCI_MODE | SCCR_PCI_MODCK) | |
319 | ||
320 | /* | |
321 | *----------------------------------------------------------------------- | |
322 | * RMR - Reset Mode Register 5-5 | |
323 | *----------------------------------------------------------------------- | |
324 | * turn on Checkstop Reset Enable | |
325 | */ | |
326 | #define CONFIG_SYS_RMR 0 | |
327 | ||
328 | /* | |
329 | *----------------------------------------------------------------------- | |
330 | * TMCNTSC - Time Counter Status and Control 4-40 | |
331 | *----------------------------------------------------------------------- | |
332 | * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, | |
333 | * and enable Time Counter | |
334 | */ | |
335 | #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) | |
336 | ||
337 | /* | |
338 | *----------------------------------------------------------------------- | |
339 | * PISCR - Periodic Interrupt Status and Control 4-42 | |
340 | *----------------------------------------------------------------------- | |
341 | * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable | |
342 | * Periodic timer | |
343 | */ | |
344 | #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) | |
345 | ||
346 | /* | |
347 | *----------------------------------------------------------------------- | |
348 | * RCCR - RISC Controller Configuration 13-7 | |
349 | *----------------------------------------------------------------------- | |
350 | */ | |
351 | #define CONFIG_SYS_RCCR 0 | |
352 | ||
353 | /* | |
354 | * Init Memory Controller: | |
355 | * | |
356 | * Bank Bus Machine PortSz Device | |
357 | * ---- --- ------- ------ ------ | |
358 | * 0 60x GPCM 8 bit FLASH | |
359 | * 1 60x SDRAM 32 bit SDRAM | |
360 | * 3 60x GPCM 8 bit GPIO/PIGGY | |
361 | * 5 60x GPCM 16 bit CFG-Flash | |
362 | * | |
363 | */ | |
364 | /* Bank 0 - FLASH | |
365 | */ | |
366 | #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ | |
367 | BRx_PS_8 |\ | |
368 | BRx_MS_GPCM_P |\ | |
369 | BRx_V) | |
370 | ||
371 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ | |
372 | ORxG_CSNT |\ | |
373 | ORxG_ACS_DIV2 |\ | |
374 | ORxG_SCY_5_CLK |\ | |
375 | ORxG_TRLX) | |
376 | ||
377 | #define CONFIG_SYS_MPTPR 0x1800 | |
378 | ||
379 | /* | |
380 | *----------------------------------------------------------------------------- | |
381 | * Address for Mode Register Set (MRS) command | |
382 | *----------------------------------------------------------------------------- | |
383 | */ | |
384 | #define CONFIG_SYS_MRS_OFFS 0x00000110 | |
385 | #define CONFIG_SYS_PSRT 0x0e | |
386 | ||
387 | #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ | |
388 | BRx_PS_64 |\ | |
389 | BRx_MS_SDRAM_P |\ | |
390 | BRx_V) | |
391 | ||
392 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1 | |
393 | ||
394 | /* | |
395 | * UPIO FPGA (GPIO/PIGGY) on CS3 initialization values | |
396 | */ | |
397 | #define CONFIG_SYS_KMBEC_FPGA_BASE 0x30000000 | |
398 | #define CONFIG_SYS_KMBEC_FPGA_SIZE 128 | |
399 | ||
400 | #define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_KMBEC_FPGA_BASE & BRx_BA_MSK) |\ | |
401 | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V) | |
402 | ||
403 | #define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) |\ | |
404 | ORxG_CSNT | ORxG_ACS_DIV2 |\ | |
405 | ORxG_SCY_3_CLK | ORxG_TRLX) | |
406 | ||
407 | /* | |
408 | * BFTICU board FPGA on CS4 initialization values | |
409 | */ | |
410 | #define CONFIG_SYS_FPGA_BASE 0x40000000 | |
411 | #define CONFIG_SYS_FPGA_SIZE 1 /*1KB*/ | |
412 | ||
413 | #define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_FPGA_BASE & BRx_BA_MSK) |\ | |
414 | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V) | |
415 | ||
416 | #define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FPGA_SIZE << 10) |\ | |
417 | ORxG_CSNT | ORxG_ACS_DIV2 |\ | |
418 | ORxG_SCY_3_CLK | ORxG_TRLX) | |
419 | ||
420 | /* | |
421 | * CFG-Flash on CS5 initialization values | |
422 | */ | |
423 | #define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_FLASH_BASE_1 & BRx_BA_MSK) |\ | |
424 | BRx_PS_16 | BRx_MS_GPCM_P | BRx_V) | |
425 | ||
426 | #define CONFIG_SYS_OR5_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE_1 + \ | |
427 | CONFIG_SYS_FLASH_SIZE_2) |\ | |
428 | ORxG_CSNT | ORxG_ACS_DIV2 |\ | |
429 | ORxG_SCY_5_CLK | ORxG_TRLX) | |
430 | ||
431 | #define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */ | |
432 | ||
65c7f923 GF |
433 | #define OF_TBCLK (bd->bi_busfreq / 4) |
434 | #define OF_STDOUT_PATH "/soc/cpm/serial@11a90" | |
af895e45 | 435 | |
bae5407d | 436 | #endif /* __CONFIG_H */ |