[people/ms/u-boot.git] / include / configs / ls1043a_common.h

/*
 * Copyright (C) 2015 Freescale Semiconductor
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __LS1043A_COMMON_H
#define __LS1043A_COMMON_H

/* SPL build */
#ifdef CONFIG_SPL_BUILD
#define SPL_NO_FMAN
#define SPL_NO_DSPI
#define SPL_NO_PCIE
#define SPL_NO_ENV
#define SPL_NO_MISC
#define SPL_NO_USB
#define SPL_NO_SATA
#define SPL_NO_QE
#define SPL_NO_EEPROM
#endif
#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT))
#define SPL_NO_MMC
#endif
#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT_QSPI))
#define SPL_NO_IFC
#endif

#define CONFIG_REMAKE_ELF
#define CONFIG_FSL_LAYERSCAPE
#define CONFIG_MP
#define CONFIG_GICV2

#include <asm/arch/stream_id_lsch2.h>
#include <asm/arch/config.h>

/* Link Definitions */
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)

#define CONFIG_SUPPORT_RAW_INITRD

#define CONFIG_SKIP_LOWLEVEL_INIT

#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_DDR_BLOCK2_BASE      0x880000000ULL

#define CPU_RELEASE_ADDR               secondary_boot_func

/* Generic Timer Definitions */
#define COUNTER_FREQUENCY		25000000	/* 25MHz */

/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 1024 * 1024)

/* Serial Port */
#define CONFIG_CONS_INDEX		1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK          (get_serial_clock())

#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/* SD boot SPL */
#ifdef CONFIG_SD_BOOT
#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"

#define CONFIG_SPL_TEXT_BASE		0x10000000
#define CONFIG_SPL_MAX_SIZE		0x17000
#define CONFIG_SPL_STACK		0x1001e000
#define CONFIG_SPL_PAD_TO		0x1d000

#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SPL_BSS_START_ADDR + \
					CONFIG_SPL_BSS_MAX_SIZE)
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
#define CONFIG_SPL_BSS_START_ADDR	0x8f000000
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000

#ifdef CONFIG_SECURE_BOOT
#define CONFIG_U_BOOT_HDR_SIZE				(16 << 10)
/*
 * HDR would be appended at end of image and copied to DDR along
 * with U-Boot image. Here u-boot max. size is 512K. So if binary
 * size increases then increase this size in case of secure boot as
 * it uses raw u-boot image instead of fit image.
 */
#define CONFIG_SYS_MONITOR_LEN		(0x100000 + CONFIG_U_BOOT_HDR_SIZE)
#else
#define CONFIG_SYS_MONITOR_LEN		0x100000
#endif /* ifdef CONFIG_SECURE_BOOT */
#endif

/* NAND SPL */
#ifdef CONFIG_NAND_BOOT
#define CONFIG_SPL_PBL_PAD
#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE		0x10000000
#define CONFIG_SPL_MAX_SIZE		0x1a000
#define CONFIG_SPL_STACK		0x1001d000
#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_SPL_MALLOC_START	0x80200000
#define CONFIG_SPL_BSS_START_ADDR	0x80100000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000

#ifdef CONFIG_SECURE_BOOT
#define CONFIG_U_BOOT_HDR_SIZE				(16 << 10)
#endif /* ifdef CONFIG_SECURE_BOOT */

#ifdef CONFIG_U_BOOT_HDR_SIZE
/*
 * HDR would be appended at end of image and copied to DDR along
 * with U-Boot image. Here u-boot max. size is 512K. So if binary
 * size increases then increase this size in case of secure boot as
 * it uses raw u-boot image instead of fit image.
 */
#define CONFIG_SYS_MONITOR_LEN		(0x100000 + CONFIG_U_BOOT_HDR_SIZE)
#else
#define CONFIG_SYS_MONITOR_LEN		0x100000
#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */

#endif

/* IFC */
#ifndef SPL_NO_IFC
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_FSL_IFC
/*
 * CONFIG_SYS_FLASH_BASE has the final address (core view)
 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
 */
#define CONFIG_SYS_FLASH_BASE			0x60000000
#define CONFIG_SYS_FLASH_BASE_PHYS		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY	0x00000000

#ifdef CONFIG_MTD_NOR_FLASH
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */
#endif
#endif
#endif

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1
#define CONFIG_SYS_I2C_MXC_I2C2
#define CONFIG_SYS_I2C_MXC_I2C3
#define CONFIG_SYS_I2C_MXC_I2C4

/* PCIe */
#ifndef SPL_NO_PCIE
#define CONFIG_PCIE1		/* PCIE controller 1 */
#define CONFIG_PCIE2		/* PCIE controller 2 */
#define CONFIG_PCIE3		/* PCIE controller 3 */

#ifdef CONFIG_PCI
#define CONFIG_PCI_SCAN_SHOW
#endif
#endif

/* Command line configuration */

/*  MMC  */
#ifndef SPL_NO_MMC
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
#endif
#endif

/*  DSPI  */
#ifndef SPL_NO_DSPI
#define CONFIG_FSL_DSPI
#ifdef CONFIG_FSL_DSPI
#define CONFIG_DM_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO	/* cs0 */
#define CONFIG_SPI_FLASH_SST		/* cs1 */
#define CONFIG_SPI_FLASH_EON		/* cs2 */
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_SF_DEFAULT_BUS		1
#define CONFIG_SF_DEFAULT_CS		0
#endif
#endif
#endif

/* FMan ucode */
#ifndef SPL_NO_FMAN
#define CONFIG_SYS_DPAA_FMAN
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_FM_MURAM_SIZE	0x60000

#ifdef CONFIG_NAND_BOOT
/* Store Fman ucode at offeset 0x900000(72 blocks). */
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
#define CONFIG_SYS_FMAN_FW_ADDR		(72 * CONFIG_SYS_NAND_BLOCK_SIZE)
#elif defined(CONFIG_SD_BOOT)
/*
 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 * about 1MB (2040 blocks), Env is stored after the image, and the env size is
 * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 18432(0x4800).
 */
#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
#define CONFIG_SYS_FMAN_FW_ADDR		(512 * 0x4800)
#define CONFIG_SYS_QE_FW_ADDR		(512 * 0x4a08)
#elif defined(CONFIG_QSPI_BOOT)
#define CONFIG_SYS_QE_FW_IN_SPIFLASH
#define CONFIG_SYS_FMAN_FW_ADDR		0x40900000
#define CONFIG_ENV_SPI_BUS		0
#define CONFIG_ENV_SPI_CS		0
#define CONFIG_ENV_SPI_MAX_HZ		1000000
#define CONFIG_ENV_SPI_MODE		0x03
#else
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
/* FMan fireware Pre-load address */
#define CONFIG_SYS_FMAN_FW_ADDR		0x60900000
#define CONFIG_SYS_QE_FW_ADDR		0x60940000
#endif
#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#endif
#endif

/* Miscellaneous configurable options */
#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)

#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE		128

#ifndef SPL_NO_MISC
#include <config_distro_defaults.h>
#ifndef CONFIG_SPL_BUILD
#define BOOT_TARGET_DEVICES(func) \
	func(MMC, mmc, 0) \
	func(USB, usb, 0)
#include <config_distro_bootcmd.h>
#endif

/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
	"fdt_high=0xffffffffffffffff\0"		\
	"initrd_high=0xffffffffffffffff\0"	\
	"fdt_addr=0x64f00000\0"		 	\
	"kernel_addr=0x61000000\0"		\
	"scriptaddr=0x80000000\0"		\
	"scripthdraddr=0x80080000\0"		\
	"fdtheader_addr_r=0x80100000\0"		\
	"kernelheader_addr_r=0x80200000\0"	\
	"kernel_addr_r=0x81000000\0"		\
	"fdt_addr_r=0x90000000\0"		\
	"load_addr=0xa0000000\0"		\
	"kernelheader_addr=0x60800000\0"	\
	"kernel_size=0x2800000\0"		\
	"kernelheader_size=0x40000\0"		\
	"kernel_addr_sd=0x8000\0"		\
	"kernel_size_sd=0x14000\0"		\
	"kernelhdr_addr_sd=0x4000\0"		\
	"kernelhdr_size_sd=0x10\0"		\
	"console=ttyS0,115200\0"		\
	"boot_os=y\0"				\
	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"	\
	BOOTENV					\
	"boot_scripts=ls1043ardb_boot.scr\0"	\
	"boot_script_hdr=hdr_ls1043ardb_bs.out\0"	\
	"scan_dev_for_boot_part="		\
		"part list ${devtype} ${devnum} devplist; "	\
		"env exists devplist || setenv devplist 1; "	\
		"for distro_bootpart in ${devplist}; do "	\
			"if fstype ${devtype} "			\
				"${devnum}:${distro_bootpart} "	\
				"bootfstype; then "		\
				"run scan_dev_for_boot; "	\
			"fi; "					\
		"done\0"			\
	"scan_dev_for_boot="					\
		"echo Scanning ${devtype} "			\
			"${devnum}:${distro_bootpart}...; "	\
		"for prefix in ${boot_prefixes}; do "		\
			"run scan_dev_for_scripts; "		\
		"done;\0"					\
	"boot_a_script="					\
		"load ${devtype} ${devnum}:${distro_bootpart} "	\
			"${scriptaddr} ${prefix}${script}; "	\
		"env exists secureboot && load ${devtype} "	\
			"${devnum}:${distro_bootpart} "		\
			"${scripthdraddr} ${prefix}${boot_script_hdr} "	\
			"&& esbc_validate ${scripthdraddr};"	\
		"source ${scriptaddr}\0"			\
	"qspi_bootcmd=echo Trying load from qspi..;"	\
		"sf probe && sf read $load_addr "	\
		"$kernel_addr $kernel_size; env exists secureboot "	\
		"&& sf read $kernelheader_addr_r $kernelheader_addr "	\
		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
		"bootm $load_addr#$board\0"	\
	"nor_bootcmd=echo Trying load from nor..;"	\
		"cp.b $kernel_addr $load_addr "	\
		"$kernel_size; env exists secureboot "	\
		"&& cp.b $kernelheader_addr $kernelheader_addr_r "	\
		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
		"bootm $load_addr#$board\0"	    \
	"sd_bootcmd=echo Trying load from SD ..;"       \
		"mmcinfo; mmc read $load_addr "         \
		"$kernel_addr_sd $kernel_size_sd && "     \
		"env exists secureboot && mmc read $kernelheader_addr_r "		\
		"$kernelhdr_addr_sd $kernelhdr_size_sd "		\
		" && esbc_validate ${kernelheader_addr_r};"	\
		"bootm $load_addr#$board\0"


#undef CONFIG_BOOTCOMMAND
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "	\
			   "env exists secureboot && esbc_halt;"
#elif defined(CONFIG_SD_BOOT)
#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "  \
			   "env exists secureboot && esbc_halt;"
#else
#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; "	\
			   "env exists secureboot && esbc_halt;"
#endif
#endif

/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
#define CONFIG_SYS_LONGHELP

#ifndef SPL_NO_MISC
#ifndef CONFIG_CMDLINE_EDITING
#define CONFIG_CMDLINE_EDITING		1
#endif
#endif

#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_MAXARGS		64	/* max command args */

#define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */

#include <asm/arch/soc.h>

#endif /* __LS1043A_COMMON_H */
Commit	Line	Data
f3a8e2b7 MH	1	/*
	2	* Copyright (C) 2015 Freescale Semiconductor
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#ifndef __LS1043A_COMMON_H
	8	#define __LS1043A_COMMON_H
	9
4139b170 SG	10	/* SPL build */
	11	#ifdef CONFIG_SPL_BUILD
	12	#define SPL_NO_FMAN
	13	#define SPL_NO_DSPI
	14	#define SPL_NO_PCIE
	15	#define SPL_NO_ENV
	16	#define SPL_NO_MISC
	17	#define SPL_NO_USB
	18	#define SPL_NO_SATA
	19	#define SPL_NO_QE
	20	#define SPL_NO_EEPROM
	21	#endif
	22	#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT))
	23	#define SPL_NO_MMC
	24	#endif
3c7d647e	25	#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT_QSPI))
4139b170 SG	26	#define SPL_NO_IFC
	27	#endif
	28
f3a8e2b7 MH	29	#define CONFIG_REMAKE_ELF
f3a8e2b7 MH	30	#define CONFIG_FSL_LAYERSCAPE
831c068f	31	#define CONFIG_MP
f3a8e2b7 MH	32	#define CONFIG_GICV2
f3a8e2b7 MH	33
5344c7b7	34	#include <asm/arch/stream_id_lsch2.h>
f3a8e2b7	35	#include <asm/arch/config.h>
f3a8e2b7 MH	36
	37	/* Link Definitions */
	38	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
	39
	40	#define CONFIG_SUPPORT_RAW_INITRD
	41
	42	#define CONFIG_SKIP_LOWLEVEL_INIT
f3a8e2b7	43
f3a8e2b7 MH	44	#define CONFIG_VERY_BIG_RAM
	45	#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
	46	#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
	47	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
e994dddb	48	#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
f3a8e2b7	49
831c068f HZ	50	#define CPU_RELEASE_ADDR secondary_boot_func
831c068f HZ	51
f3a8e2b7 MH	52	/* Generic Timer Definitions */
	53	#define COUNTER_FREQUENCY 25000000 /* 25MHz */
	54
	55	/* Size of malloc() pool */
	56	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
	57
	58	/* Serial Port */
	59	#define CONFIG_CONS_INDEX 1
f3a8e2b7 MH	60	#define CONFIG_SYS_NS16550_SERIAL
f3a8e2b7 MH	61	#define CONFIG_SYS_NS16550_REG_SIZE 1
904110c7	62	#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
f3a8e2b7	63
f3a8e2b7 MH	64	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
f3a8e2b7 MH	65
c7ca8b07 GQ	66	/* SD boot SPL */
c7ca8b07 GQ	67	#ifdef CONFIG_SD_BOOT
c7ca8b07	68	#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
c7ca8b07 GQ	69
c7ca8b07 GQ	70	#define CONFIG_SPL_TEXT_BASE 0x10000000
70f9661c	71	#define CONFIG_SPL_MAX_SIZE 0x17000
c7ca8b07 GQ	72	#define CONFIG_SPL_STACK 0x1001e000
	73	#define CONFIG_SPL_PAD_TO 0x1d000
	74
23af484b YS	75	#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
23af484b YS	76	CONFIG_SPL_BSS_MAX_SIZE)
c7ca8b07	77	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
23af484b	78	#define CONFIG_SPL_BSS_START_ADDR 0x8f000000
c7ca8b07	79	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
70f9661c RG	80
	81	#ifdef CONFIG_SECURE_BOOT
	82	#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
	83	/*
	84	* HDR would be appended at end of image and copied to DDR along
	85	* with U-Boot image. Here u-boot max. size is 512K. So if binary
	86	* size increases then increase this size in case of secure boot as
	87	* it uses raw u-boot image instead of fit image.
	88	*/
	89	#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
	90	#else
	91	#define CONFIG_SYS_MONITOR_LEN 0x100000
	92	#endif /* ifdef CONFIG_SECURE_BOOT */
c7ca8b07 GQ	93	#endif
c7ca8b07 GQ	94
3ad44729 GQ	95	/* NAND SPL */
	96	#ifdef CONFIG_NAND_BOOT
	97	#define CONFIG_SPL_PBL_PAD
3ad44729	98	#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
3ad44729 GQ	99	#define CONFIG_SPL_TEXT_BASE 0x10000000
	100	#define CONFIG_SPL_MAX_SIZE 0x1a000
	101	#define CONFIG_SPL_STACK 0x1001d000
	102	#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
	103	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
	104	#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
	105	#define CONFIG_SPL_BSS_START_ADDR 0x80100000
	106	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
	107	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
762f92a6 RG	108
	109	#ifdef CONFIG_SECURE_BOOT
	110	#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
	111	#endif /* ifdef CONFIG_SECURE_BOOT */
	112
	113	#ifdef CONFIG_U_BOOT_HDR_SIZE
	114	/*
	115	* HDR would be appended at end of image and copied to DDR along
	116	* with U-Boot image. Here u-boot max. size is 512K. So if binary
	117	* size increases then increase this size in case of secure boot as
	118	* it uses raw u-boot image instead of fit image.
	119	*/
	120	#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
	121	#else
	122	#define CONFIG_SYS_MONITOR_LEN 0x100000
	123	#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
	124
3ad44729 GQ	125	#endif
3ad44729 GQ	126
f3a8e2b7	127	/* IFC */
4139b170	128	#ifndef SPL_NO_IFC
b0f20caf	129	#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
f3a8e2b7 MH	130	#define CONFIG_FSL_IFC
	131	/*
	132	* CONFIG_SYS_FLASH_BASE has the final address (core view)
	133	* CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
	134	* CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
	135	* CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
	136	*/
	137	#define CONFIG_SYS_FLASH_BASE 0x60000000
	138	#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
	139	#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
	140
e856bdcf	141	#ifdef CONFIG_MTD_NOR_FLASH
f3a8e2b7 MH	142	#define CONFIG_FLASH_CFI_DRIVER
	143	#define CONFIG_SYS_FLASH_CFI
	144	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
	145	#define CONFIG_SYS_FLASH_QUIET_TEST
	146	#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
	147	#endif
166ef1e9	148	#endif
4139b170	149	#endif
f3a8e2b7 MH	150
f3a8e2b7 MH	151	/* I2C */
f3a8e2b7 MH	152	#define CONFIG_SYS_I2C
	153	#define CONFIG_SYS_I2C_MXC
	154	#define CONFIG_SYS_I2C_MXC_I2C1
	155	#define CONFIG_SYS_I2C_MXC_I2C2
	156	#define CONFIG_SYS_I2C_MXC_I2C3
	157	#define CONFIG_SYS_I2C_MXC_I2C4
	158
	159	/* PCIe */
4139b170	160	#ifndef SPL_NO_PCIE
f3a8e2b7 MH	161	#define CONFIG_PCIE1 /* PCIE controller 1 */
	162	#define CONFIG_PCIE2 /* PCIE controller 2 */
	163	#define CONFIG_PCIE3 /* PCIE controller 3 */
f3a8e2b7	164
f3a8e2b7	165	#ifdef CONFIG_PCI
f3a8e2b7	166	#define CONFIG_PCI_SCAN_SHOW
f3a8e2b7	167	#endif
4139b170	168	#endif
f3a8e2b7 MH	169
f3a8e2b7 MH	170	/* Command line configuration */
f3a8e2b7	171
8ef0d5c4	172	/* MMC */
4139b170	173	#ifndef SPL_NO_MMC
8ef0d5c4	174	#ifdef CONFIG_MMC
8ef0d5c4 YL	175	#define CONFIG_FSL_ESDHC
8ef0d5c4 YL	176	#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
8ef0d5c4	177	#endif
4139b170	178	#endif
8ef0d5c4	179
e0579a58	180	/* DSPI */
4139b170	181	#ifndef SPL_NO_DSPI
e0579a58 GQ	182	#define CONFIG_FSL_DSPI
e0579a58 GQ	183	#ifdef CONFIG_FSL_DSPI
e0579a58 GQ	184	#define CONFIG_DM_SPI_FLASH
	185	#define CONFIG_SPI_FLASH_STMICRO /* cs0 */
	186	#define CONFIG_SPI_FLASH_SST /* cs1 */
	187	#define CONFIG_SPI_FLASH_EON /* cs2 */
b0f20caf	188	#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
e0579a58 GQ	189	#define CONFIG_SF_DEFAULT_BUS 1
	190	#define CONFIG_SF_DEFAULT_CS 0
	191	#endif
166ef1e9	192	#endif
4139b170	193	#endif
e0579a58	194
e8297341	195	/* FMan ucode */
4139b170	196	#ifndef SPL_NO_FMAN
e8297341 SX	197	#define CONFIG_SYS_DPAA_FMAN
	198	#ifdef CONFIG_SYS_DPAA_FMAN
	199	#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
	200
fd1b147c	201	#ifdef CONFIG_NAND_BOOT
a9a5cef3	202	/* Store Fman ucode at offeset 0x900000(72 blocks). */
fd1b147c	203	#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
a9a5cef3	204	#define CONFIG_SYS_FMAN_FW_ADDR (72 * CONFIG_SYS_NAND_BLOCK_SIZE)
2a555839 QG	205	#elif defined(CONFIG_SD_BOOT)
	206	/*
	207	* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
	208	* about 1MB (2040 blocks), Env is stored after the image, and the env size is
a9a5cef3	209	* 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 18432(0x4800).
2a555839 QG	210	*/
2a555839 QG	211	#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
a9a5cef3	212	#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800)
5aa03ddd	213	#define CONFIG_SYS_QE_FW_ADDR (512 * 0x4a08)
2a555839	214	#elif defined(CONFIG_QSPI_BOOT)
166ef1e9	215	#define CONFIG_SYS_QE_FW_IN_SPIFLASH
a9a5cef3	216	#define CONFIG_SYS_FMAN_FW_ADDR 0x40900000
166ef1e9 GQ	217	#define CONFIG_ENV_SPI_BUS 0
	218	#define CONFIG_ENV_SPI_CS 0
	219	#define CONFIG_ENV_SPI_MAX_HZ 1000000
	220	#define CONFIG_ENV_SPI_MODE 0x03
	221	#else
e8297341 SX	222	#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
e8297341 SX	223	/* FMan fireware Pre-load address */
a9a5cef3	224	#define CONFIG_SYS_FMAN_FW_ADDR 0x60900000
5aa03ddd	225	#define CONFIG_SYS_QE_FW_ADDR 0x60940000
166ef1e9	226	#endif
e8297341 SX	227	#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
	228	#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
	229	#endif
4139b170	230	#endif
e8297341	231
f3a8e2b7 MH	232	/* Miscellaneous configurable options */
f3a8e2b7 MH	233	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
f3a8e2b7 MH	234
	235	#define CONFIG_HWCONFIG
	236	#define HWCONFIG_BUFFER_SIZE 128
	237
4139b170	238	#ifndef SPL_NO_MISC
5ba909f4 SL	239	#include <config_distro_defaults.h>
	240	#ifndef CONFIG_SPL_BUILD
	241	#define BOOT_TARGET_DEVICES(func) \
	242	func(MMC, mmc, 0) \
	243	func(USB, usb, 0)
	244	#include <config_distro_bootcmd.h>
	245	#endif
	246
f3a8e2b7 MH	247	/* Initial environment variables */
	248	#define CONFIG_EXTRA_ENV_SETTINGS \
	249	"hwconfig=fsl_ddr:bank_intlv=auto\0" \
f3a8e2b7 MH	250	"fdt_high=0xffffffffffffffff\0" \
f3a8e2b7 MH	251	"initrd_high=0xffffffffffffffff\0" \
5ba909f4	252	"fdt_addr=0x64f00000\0" \
9b457cc6	253	"kernel_addr=0x61000000\0" \
5ba909f4	254	"scriptaddr=0x80000000\0" \
76bbf1c6	255	"scripthdraddr=0x80080000\0" \
5ba909f4 SL	256	"fdtheader_addr_r=0x80100000\0" \
	257	"kernelheader_addr_r=0x80200000\0" \
	258	"kernel_addr_r=0x81000000\0" \
	259	"fdt_addr_r=0x90000000\0" \
	260	"load_addr=0xa0000000\0" \
9b457cc6	261	"kernelheader_addr=0x60800000\0" \
ad6767b6	262	"kernel_size=0x2800000\0" \
9b457cc6	263	"kernelheader_size=0x40000\0" \
1c8263de SL	264	"kernel_addr_sd=0x8000\0" \
1c8263de SL	265	"kernel_size_sd=0x14000\0" \
9b457cc6 VPB	266	"kernelhdr_addr_sd=0x4000\0" \
9b457cc6 VPB	267	"kernelhdr_size_sd=0x10\0" \
5ba909f4	268	"console=ttyS0,115200\0" \
23af484b	269	"boot_os=y\0" \
43ede0bc	270	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
5ba909f4 SL	271	BOOTENV \
5ba909f4 SL	272	"boot_scripts=ls1043ardb_boot.scr\0" \
76bbf1c6	273	"boot_script_hdr=hdr_ls1043ardb_bs.out\0" \
5ba909f4 SL	274	"scan_dev_for_boot_part=" \
	275	"part list ${devtype} ${devnum} devplist; " \
	276	"env exists devplist \|\| setenv devplist 1; " \
	277	"for distro_bootpart in ${devplist}; do " \
	278	"if fstype ${devtype} " \
	279	"${devnum}:${distro_bootpart} " \
	280	"bootfstype; then " \
	281	"run scan_dev_for_boot; " \
	282	"fi; " \
	283	"done\0" \
76bbf1c6 SG	284	"scan_dev_for_boot=" \
	285	"echo Scanning ${devtype} " \
	286	"${devnum}:${distro_bootpart}...; " \
	287	"for prefix in ${boot_prefixes}; do " \
	288	"run scan_dev_for_scripts; " \
	289	"done;\0" \
	290	"boot_a_script=" \
	291	"load ${devtype} ${devnum}:${distro_bootpart} " \
	292	"${scriptaddr} ${prefix}${script}; " \
	293	"env exists secureboot && load ${devtype} " \
	294	"${devnum}:${distro_bootpart} " \
	295	"${scripthdraddr} ${prefix}${boot_script_hdr} " \
	296	"&& esbc_validate ${scripthdraddr};" \
	297	"source ${scriptaddr}\0" \
5ba909f4 SL	298	"qspi_bootcmd=echo Trying load from qspi..;" \
5ba909f4 SL	299	"sf probe && sf read $load_addr " \
9b457cc6 VPB	300	"$kernel_addr $kernel_size; env exists secureboot " \
	301	"&& sf read $kernelheader_addr_r $kernelheader_addr " \
	302	"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
	303	"bootm $load_addr#$board\0" \
5ba909f4 SL	304	"nor_bootcmd=echo Trying load from nor..;" \
5ba909f4 SL	305	"cp.b $kernel_addr $load_addr " \
9b457cc6 VPB	306	"$kernel_size; env exists secureboot " \
	307	"&& cp.b $kernelheader_addr $kernelheader_addr_r " \
	308	"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
	309	"bootm $load_addr#$board\0" \
1c8263de SL	310	"sd_bootcmd=echo Trying load from SD ..;" \
	311	"mmcinfo; mmc read $load_addr " \
	312	"$kernel_addr_sd $kernel_size_sd && " \
9b457cc6 VPB	313	"env exists secureboot && mmc read $kernelheader_addr_r " \
	314	"$kernelhdr_addr_sd $kernelhdr_size_sd " \
	315	" && esbc_validate ${kernelheader_addr_r};" \
1c8263de SL	316	"bootm $load_addr#$board\0"
1c8263de SL	317
5ba909f4 SL	318
	319	#undef CONFIG_BOOTCOMMAND
	320	#if defined(CONFIG_QSPI_BOOT) \|\| defined(CONFIG_SD_BOOT_QSPI)
9b457cc6 VPB	321	#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
9b457cc6 VPB	322	"env exists secureboot && esbc_halt;"
1c8263de	323	#elif defined(CONFIG_SD_BOOT)
9b457cc6 VPB	324	#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
9b457cc6 VPB	325	"env exists secureboot && esbc_halt;"
5ba909f4	326	#else
9b457cc6 VPB	327	#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
9b457cc6 VPB	328	"env exists secureboot && esbc_halt;"
5ba909f4	329	#endif
4139b170	330	#endif
f3a8e2b7 MH	331
	332	/* Monitor Command Prompt */
	333	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
f3a8e2b7	334	#define CONFIG_SYS_LONGHELP
4139b170 SG	335
4139b170 SG	336	#ifndef SPL_NO_MISC
5ba909f4	337	#ifndef CONFIG_CMDLINE_EDITING
f3a8e2b7	338	#define CONFIG_CMDLINE_EDITING 1
4139b170	339	#endif
5ba909f4	340	#endif
4139b170	341
f3a8e2b7 MH	342	#define CONFIG_AUTO_COMPLETE
	343	#define CONFIG_SYS_MAXARGS 64 /* max command args */
	344
	345	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
	346
457e51cf SG	347	#include <asm/arch/soc.h>
457e51cf SG	348
f3a8e2b7	349	#endif /* __LS1043A_COMMON_H */