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b765ffb7 | 1 | /* |
7e4a0d25 | 2 | * (C) Copyright 2007-2008 |
b765ffb7 SR |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License as | |
7 | * published by the Free Software Foundation; either version 2 of | |
8 | * the License, or (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
18 | * MA 02111-1307 USA | |
19 | */ | |
20 | ||
21 | /************************************************************************ | |
22 | * lwmon5.h - configuration for lwmon5 board | |
23 | ***********************************************************************/ | |
24 | #ifndef __CONFIG_H | |
25 | #define __CONFIG_H | |
26 | ||
27 | /*----------------------------------------------------------------------- | |
28 | * High Level Configuration Options | |
29 | *----------------------------------------------------------------------*/ | |
30 | #define CONFIG_LWMON5 1 /* Board is lwmon5 */ | |
31 | #define CONFIG_440EPX 1 /* Specific PPC440EPx */ | |
e73846b7 | 32 | #define CONFIG_440 1 /* ... PPC440 family */ |
b765ffb7 SR |
33 | #define CONFIG_4xx 1 /* ... PPC4xx family */ |
34 | #define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */ | |
35 | ||
36 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ | |
3ad63878 | 37 | #define CONFIG_BOARD_POSTCLK_INIT 1 /* Call board_postclk_init */ |
b765ffb7 | 38 | #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ |
0f009f78 | 39 | #define CONFIG_BOARD_RESET 1 /* Call board_reset */ |
b765ffb7 SR |
40 | |
41 | /*----------------------------------------------------------------------- | |
42 | * Base addresses -- Note these are effective addresses where the | |
43 | * actual resources get mapped (not physical addresses) | |
44 | *----------------------------------------------------------------------*/ | |
6d0f6bcf JCPV |
45 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ |
46 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc() */ | |
47 | ||
48 | #define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000 | |
49 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ | |
50 | #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */ | |
51 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE | |
52 | #define CONFIG_SYS_LIME_BASE_0 0xc0000000 | |
53 | #define CONFIG_SYS_LIME_BASE_1 0xc1000000 | |
54 | #define CONFIG_SYS_LIME_BASE_2 0xc2000000 | |
55 | #define CONFIG_SYS_LIME_BASE_3 0xc3000000 | |
56 | #define CONFIG_SYS_FPGA_BASE_0 0xc4000000 | |
57 | #define CONFIG_SYS_FPGA_BASE_1 0xc4200000 | |
58 | #define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */ | |
59 | #define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */ | |
60 | #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ | |
61 | #define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000 | |
62 | #define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000 | |
63 | #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000 | |
b765ffb7 SR |
64 | |
65 | /* Don't change either of these */ | |
6d0f6bcf | 66 | #define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripherals */ |
b765ffb7 | 67 | |
6d0f6bcf JCPV |
68 | #define CONFIG_SYS_USB2D0_BASE 0xe0000100 |
69 | #define CONFIG_SYS_USB_DEVICE 0xe0000000 | |
70 | #define CONFIG_SYS_USB_HOST 0xe0000400 | |
b765ffb7 SR |
71 | |
72 | /*----------------------------------------------------------------------- | |
73 | * Initial RAM & stack pointer | |
74 | *----------------------------------------------------------------------*/ | |
8f24e063 SR |
75 | /* |
76 | * On LWMON5 we use D-cache as init-ram and stack pointer. We also move | |
77 | * the POST_WORD from OCM to a 440EPx register that preserves it's | |
eb0615bf YT |
78 | * content during reset (GPT0_COMP6). This way we reserve the OCM (16k) |
79 | * for logbuffer only. (GPT0_COMP1-COMP5 are reserved for logbuffer header.) | |
8f24e063 | 80 | */ |
6d0f6bcf JCPV |
81 | #define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */ |
82 | #define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */ | |
83 | #define CONFIG_SYS_INIT_RAM_END (4 << 10) | |
84 | #define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data*/ | |
85 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
86 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
87 | #define CONFIG_SYS_POST_ALT_WORD_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6) | |
8f24e063 | 88 | /* unused GPT0 COMP reg */ |
6d0f6bcf | 89 | #define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */ |
14f73ca6 | 90 | /* 440EPx errata CHIP 11 */ |
6d0f6bcf | 91 | #define CONFIG_SYS_OCM_SIZE (16 << 10) |
b765ffb7 | 92 | |
8f15d4ad YT |
93 | /* Additional registers for watchdog timer post test */ |
94 | ||
6d0f6bcf JCPV |
95 | #define CONFIG_SYS_WATCHDOG_TIME_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK2) |
96 | #define CONFIG_SYS_WATCHDOG_FLAGS_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK1) | |
97 | #define CONFIG_SYS_DSPIC_TEST_ADDR CONFIG_SYS_WATCHDOG_FLAGS_ADDR | |
98 | #define CONFIG_SYS_OCM_STATUS_ADDR CONFIG_SYS_WATCHDOG_FLAGS_ADDR | |
99 | #define CONFIG_SYS_WATCHDOG_MAGIC 0x12480000 | |
100 | #define CONFIG_SYS_WATCHDOG_MAGIC_MASK 0xFFFF0000 | |
101 | #define CONFIG_SYS_DSPIC_TEST_MASK 0x00000001 | |
102 | #define CONFIG_SYS_OCM_STATUS_OK 0x00009A00 | |
103 | #define CONFIG_SYS_OCM_STATUS_FAIL 0x0000A300 | |
104 | #define CONFIG_SYS_OCM_STATUS_MASK 0x0000FF00 | |
8f15d4ad | 105 | |
b765ffb7 SR |
106 | /*----------------------------------------------------------------------- |
107 | * Serial Port | |
108 | *----------------------------------------------------------------------*/ | |
6d0f6bcf | 109 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external clock provided */ |
b765ffb7 SR |
110 | #define CONFIG_BAUDRATE 115200 |
111 | #define CONFIG_SERIAL_MULTI 1 | |
112 | /* define this if you want console on UART1 */ | |
113 | #define CONFIG_UART1_CONSOLE 1 /* use UART1 as console */ | |
114 | ||
6d0f6bcf | 115 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
b765ffb7 SR |
116 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} |
117 | ||
118 | /*----------------------------------------------------------------------- | |
119 | * Environment | |
120 | *----------------------------------------------------------------------*/ | |
5a1aceb0 | 121 | #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ |
b765ffb7 SR |
122 | |
123 | /*----------------------------------------------------------------------- | |
124 | * FLASH related | |
125 | *----------------------------------------------------------------------*/ | |
6d0f6bcf | 126 | #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ |
00b1883a | 127 | #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ |
b765ffb7 | 128 | |
6d0f6bcf JCPV |
129 | #define CONFIG_SYS_FLASH0 0xFC000000 |
130 | #define CONFIG_SYS_FLASH1 0xF8000000 | |
131 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 } | |
b765ffb7 | 132 | |
6d0f6bcf JCPV |
133 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
134 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ | |
b765ffb7 | 135 | |
6d0f6bcf JCPV |
136 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
137 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
b765ffb7 | 138 | |
6d0f6bcf JCPV |
139 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ |
140 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */ | |
b765ffb7 | 141 | |
6d0f6bcf JCPV |
142 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
143 | #define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ | |
b765ffb7 | 144 | |
0e8d1586 | 145 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ |
6d0f6bcf | 146 | #define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE) |
0e8d1586 | 147 | #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ |
b765ffb7 SR |
148 | |
149 | /* Address and size of Redundant Environment Sector */ | |
0e8d1586 JCPV |
150 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) |
151 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
b765ffb7 SR |
152 | |
153 | /*----------------------------------------------------------------------- | |
154 | * DDR SDRAM | |
155 | *----------------------------------------------------------------------*/ | |
6d0f6bcf JCPV |
156 | #define CONFIG_SYS_MBYTES_SDRAM (256) /* 256MB */ |
157 | #define CONFIG_SYS_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */ | |
b765ffb7 | 158 | #define CONFIG_DDR_DATA_EYE 1 /* use DDR2 optimization */ |
b765ffb7 | 159 | #define CONFIG_DDR_ECC 1 /* enable ECC */ |
6d0f6bcf | 160 | #define CONFIG_SYS_POST_ECC_ON CONFIG_SYS_POST_ECC |
531e3e8b PK |
161 | |
162 | /* POST support */ | |
6d0f6bcf JCPV |
163 | #define CONFIG_POST (CONFIG_SYS_POST_CACHE | \ |
164 | CONFIG_SYS_POST_CPU | \ | |
165 | CONFIG_SYS_POST_ECC_ON | \ | |
166 | CONFIG_SYS_POST_ETHER | \ | |
167 | CONFIG_SYS_POST_FPU | \ | |
168 | CONFIG_SYS_POST_I2C | \ | |
169 | CONFIG_SYS_POST_MEMORY | \ | |
170 | CONFIG_SYS_POST_OCM | \ | |
171 | CONFIG_SYS_POST_RTC | \ | |
172 | CONFIG_SYS_POST_SPR | \ | |
173 | CONFIG_SYS_POST_UART | \ | |
174 | CONFIG_SYS_POST_SYSMON | \ | |
175 | CONFIG_SYS_POST_WATCHDOG | \ | |
176 | CONFIG_SYS_POST_DSP | \ | |
177 | CONFIG_SYS_POST_BSPEC1 | \ | |
178 | CONFIG_SYS_POST_BSPEC2 | \ | |
179 | CONFIG_SYS_POST_BSPEC3 | \ | |
180 | CONFIG_SYS_POST_BSPEC4 | \ | |
181 | CONFIG_SYS_POST_BSPEC5) | |
8f15d4ad YT |
182 | |
183 | #define CONFIG_POST_WATCHDOG {\ | |
184 | "Watchdog timer test", \ | |
185 | "watchdog", \ | |
186 | "This test checks the watchdog timer.", \ | |
187 | POST_RAM | POST_POWERON | POST_SLOWTEST | POST_MANUAL | POST_REBOOT, \ | |
188 | &lwmon5_watchdog_post_test, \ | |
189 | NULL, \ | |
190 | NULL, \ | |
6d0f6bcf | 191 | CONFIG_SYS_POST_WATCHDOG \ |
8f15d4ad YT |
192 | } |
193 | ||
194 | #define CONFIG_POST_BSPEC1 {\ | |
195 | "dsPIC init test", \ | |
196 | "dspic_init", \ | |
197 | "This test returns result of dsPIC READY test run earlier.", \ | |
198 | POST_RAM | POST_ALWAYS, \ | |
199 | &dspic_init_post_test, \ | |
200 | NULL, \ | |
201 | NULL, \ | |
6d0f6bcf | 202 | CONFIG_SYS_POST_BSPEC1 \ |
8f15d4ad YT |
203 | } |
204 | ||
205 | #define CONFIG_POST_BSPEC2 {\ | |
206 | "dsPIC test", \ | |
207 | "dspic", \ | |
208 | "This test gets result of dsPIC POST and dsPIC version.", \ | |
209 | POST_RAM | POST_ALWAYS, \ | |
210 | &dspic_post_test, \ | |
211 | NULL, \ | |
212 | NULL, \ | |
6d0f6bcf | 213 | CONFIG_SYS_POST_BSPEC2 \ |
8f15d4ad YT |
214 | } |
215 | ||
216 | #define CONFIG_POST_BSPEC3 {\ | |
217 | "FPGA test", \ | |
218 | "fpga", \ | |
219 | "This test checks FPGA registers and memory.", \ | |
220 | POST_RAM | POST_ALWAYS, \ | |
221 | &fpga_post_test, \ | |
222 | NULL, \ | |
223 | NULL, \ | |
6d0f6bcf | 224 | CONFIG_SYS_POST_BSPEC3 \ |
8f15d4ad YT |
225 | } |
226 | ||
227 | #define CONFIG_POST_BSPEC4 {\ | |
228 | "GDC test", \ | |
229 | "gdc", \ | |
230 | "This test checks GDC registers and memory.", \ | |
231 | POST_RAM | POST_ALWAYS, \ | |
232 | &gdc_post_test, \ | |
233 | NULL, \ | |
234 | NULL, \ | |
6d0f6bcf | 235 | CONFIG_SYS_POST_BSPEC4 \ |
8f15d4ad YT |
236 | } |
237 | ||
238 | #define CONFIG_POST_BSPEC5 {\ | |
239 | "SYSMON1 test", \ | |
240 | "sysmon1", \ | |
241 | "This test checks GPIO_62_EPX pin indicating power failure.", \ | |
242 | POST_RAM | POST_MANUAL | POST_NORMAL | POST_SLOWTEST, \ | |
243 | &sysmon1_post_test, \ | |
244 | NULL, \ | |
245 | NULL, \ | |
6d0f6bcf | 246 | CONFIG_SYS_POST_BSPEC5 \ |
8f15d4ad | 247 | } |
3e4c90c6 | 248 | |
6d0f6bcf | 249 | #define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */ |
3e4c90c6 | 250 | #define CONFIG_LOGBUFFER |
eb0615bf | 251 | /* Reserve GPT0_COMP1-COMP5 for logbuffer header */ |
6d0f6bcf JCPV |
252 | #define CONFIG_ALT_LH_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP1) |
253 | #define CONFIG_ALT_LB_ADDR (CONFIG_SYS_OCM_BASE) | |
254 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ | |
b765ffb7 SR |
255 | |
256 | /*----------------------------------------------------------------------- | |
257 | * I2C | |
258 | *----------------------------------------------------------------------*/ | |
259 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
260 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
d0b0dcaa | 261 | #define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ |
6d0f6bcf JCPV |
262 | #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ |
263 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
b765ffb7 | 264 | |
6d0f6bcf JCPV |
265 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 /* EEPROM AT24C128 */ |
266 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ | |
267 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel AT24C128 has */ | |
c25dd8fc SR |
268 | /* 64 byte page write mode using*/ |
269 | /* last 6 bits of the address */ | |
6d0f6bcf | 270 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
b765ffb7 SR |
271 | |
272 | #define CONFIG_RTC_PCF8563 1 /* enable Philips PCF8563 RTC */ | |
6d0f6bcf JCPV |
273 | #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */ |
274 | #define CONFIG_SYS_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */ | |
275 | #define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* PIC I/O addr */ | |
b765ffb7 | 276 | |
3ad63878 SR |
277 | #define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */ |
278 | #if 0 | |
279 | #define CONFIG_AUTOBOOT_KEYED /* Enable "password" protection */ | |
c37207d7 WD |
280 | #define CONFIG_AUTOBOOT_PROMPT \ |
281 | "\nEnter password - autoboot in %d sec...\n", bootdelay | |
3ad63878 SR |
282 | #define CONFIG_AUTOBOOT_DELAY_STR " " /* "password" */ |
283 | #endif | |
284 | ||
285 | #define CONFIG_PREBOOT "setenv bootdelay 15" | |
b765ffb7 SR |
286 | |
287 | #undef CONFIG_BOOTARGS | |
288 | ||
289 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
290 | "hostname=lwmon5\0" \ | |
291 | "netdev=eth0\0" \ | |
5d187430 | 292 | "unlock=yes\0" \ |
3e4c90c6 | 293 | "logversion=2\0" \ |
b765ffb7 SR |
294 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
295 | "nfsroot=${serverip}:${rootpath}\0" \ | |
296 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
297 | "addip=setenv bootargs ${bootargs} " \ | |
298 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
299 | ":${hostname}:${netdev}:off panic=1\0" \ | |
300 | "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\ | |
04625764 SR |
301 | "addmisc=setenv bootargs ${bootargs} rtc-pcf8563.probe=0,0x51\0"\ |
302 | "flash_nfs=run nfsargs addip addtty addmisc;" \ | |
b765ffb7 | 303 | "bootm ${kernel_addr}\0" \ |
04625764 | 304 | "flash_self=run ramargs addip addtty addmisc;" \ |
b765ffb7 | 305 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
04625764 SR |
306 | "net_nfs=tftp 200000 ${bootfile};" \ |
307 | "run nfsargs addip addtty addmisc;bootm\0" \ | |
b765ffb7 SR |
308 | "rootpath=/opt/eldk/ppc_4xxFP\0" \ |
309 | "bootfile=/tftpboot/lwmon5/uImage\0" \ | |
310 | "kernel_addr=FC000000\0" \ | |
311 | "ramdisk_addr=FC180000\0" \ | |
312 | "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \ | |
313 | "update=protect off FFF80000 FFFFFFFF;era FFF80000 FFFFFFFF;" \ | |
314 | "cp.b 200000 FFF80000 80000\0" \ | |
d8ab58b2 | 315 | "upd=run load update\0" \ |
334043f6 | 316 | "lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;" \ |
74de7aef | 317 | "source 200000\0" \ |
b765ffb7 SR |
318 | "" |
319 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
320 | ||
321 | #if 0 | |
322 | #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ | |
323 | #else | |
324 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
325 | #endif | |
326 | ||
327 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 328 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
b765ffb7 | 329 | |
96e21f86 | 330 | #define CONFIG_PPC4xx_EMAC |
b765ffb7 SR |
331 | #define CONFIG_IBM_EMAC4_V4 1 |
332 | #define CONFIG_MII 1 /* MII PHY management */ | |
333 | #define CONFIG_PHY_ADDR 3 /* PHY address, See schematics */ | |
334 | ||
335 | #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ | |
3ad63878 | 336 | #define CONFIG_PHY_RESET_DELAY 300 |
b765ffb7 SR |
337 | |
338 | #define CONFIG_HAS_ETH0 | |
6d0f6bcf | 339 | #define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ |
b765ffb7 SR |
340 | |
341 | #define CONFIG_NET_MULTI 1 | |
342 | #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ | |
343 | #define CONFIG_PHY1_ADDR 1 | |
344 | ||
d610a607 AG |
345 | /* Video console */ |
346 | #define CONFIG_VIDEO | |
347 | #define CONFIG_VIDEO_MB862xx | |
5d16ca87 | 348 | #define CONFIG_VIDEO_MB862xx_ACCEL |
d610a607 AG |
349 | #define CONFIG_CFB_CONSOLE |
350 | #define CONFIG_VIDEO_LOGO | |
351 | #define CONFIG_CONSOLE_EXTRA_INFO | |
352 | #define VIDEO_FB_16BPP_PIXEL_SWAP | |
229b6dce | 353 | #define VIDEO_FB_16BPP_WORD_SWAP |
d610a607 AG |
354 | |
355 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
356 | #define CONFIG_VIDEO_SW_CURSOR | |
357 | #define CONFIG_SPLASH_SCREEN | |
358 | ||
b765ffb7 SR |
359 | /* USB */ |
360 | #ifdef CONFIG_440EPX | |
361 | #define CONFIG_USB_OHCI | |
362 | #define CONFIG_USB_STORAGE | |
363 | ||
364 | /* Comment this out to enable USB 1.1 device */ | |
365 | #define USB_2_0_DEVICE | |
366 | ||
b765ffb7 SR |
367 | #endif /* CONFIG_440EPX */ |
368 | ||
369 | /* Partitions */ | |
370 | #define CONFIG_MAC_PARTITION | |
371 | #define CONFIG_DOS_PARTITION | |
372 | #define CONFIG_ISO_PARTITION | |
373 | ||
079a136c JL |
374 | /* |
375 | * BOOTP options | |
376 | */ | |
377 | #define CONFIG_BOOTP_BOOTFILESIZE | |
378 | #define CONFIG_BOOTP_BOOTPATH | |
379 | #define CONFIG_BOOTP_GATEWAY | |
380 | #define CONFIG_BOOTP_HOSTNAME | |
b765ffb7 | 381 | |
a22d4da9 JL |
382 | /* |
383 | * Command line configuration. | |
384 | */ | |
385 | #include <config_cmd_default.h> | |
386 | ||
387 | #define CONFIG_CMD_ASKENV | |
388 | #define CONFIG_CMD_DATE | |
389 | #define CONFIG_CMD_DHCP | |
390 | #define CONFIG_CMD_DIAG | |
391 | #define CONFIG_CMD_EEPROM | |
392 | #define CONFIG_CMD_ELF | |
393 | #define CONFIG_CMD_FAT | |
394 | #define CONFIG_CMD_I2C | |
395 | #define CONFIG_CMD_IRQ | |
3b3bff4c | 396 | #define CONFIG_CMD_LOG |
a22d4da9 JL |
397 | #define CONFIG_CMD_MII |
398 | #define CONFIG_CMD_NET | |
399 | #define CONFIG_CMD_NFS | |
400 | #define CONFIG_CMD_PCI | |
401 | #define CONFIG_CMD_PING | |
402 | #define CONFIG_CMD_REGINFO | |
403 | #define CONFIG_CMD_SDRAM | |
b765ffb7 | 404 | |
d610a607 AG |
405 | #ifdef CONFIG_VIDEO |
406 | #define CONFIG_CMD_BMP | |
407 | #endif | |
408 | ||
a22d4da9 JL |
409 | #ifdef CONFIG_440EPX |
410 | #define CONFIG_CMD_USB | |
411 | #endif | |
b765ffb7 SR |
412 | |
413 | /*----------------------------------------------------------------------- | |
414 | * Miscellaneous configurable options | |
415 | *----------------------------------------------------------------------*/ | |
a22d4da9 JL |
416 | #define CONFIG_SUPPORT_VFAT |
417 | ||
6d0f6bcf JCPV |
418 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
419 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
58d20425 | 420 | |
6d0f6bcf JCPV |
421 | #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ |
422 | #ifdef CONFIG_SYS_HUSH_PARSER | |
423 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
58d20425 WD |
424 | #endif |
425 | ||
a22d4da9 | 426 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 427 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
b765ffb7 | 428 | #else |
6d0f6bcf | 429 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
b765ffb7 | 430 | #endif |
6d0f6bcf JCPV |
431 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
432 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
433 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
b765ffb7 | 434 | |
6d0f6bcf JCPV |
435 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
436 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
b765ffb7 | 437 | |
6d0f6bcf JCPV |
438 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
439 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
b765ffb7 | 440 | |
6d0f6bcf | 441 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
b765ffb7 SR |
442 | |
443 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
444 | #define CONFIG_LOOPW 1 /* enable loopw command */ | |
445 | #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ | |
b765ffb7 SR |
446 | #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ |
447 | ||
448 | /*----------------------------------------------------------------------- | |
449 | * PCI stuff | |
450 | *----------------------------------------------------------------------*/ | |
451 | /* General PCI */ | |
452 | #define CONFIG_PCI /* include pci support */ | |
453 | #undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ | |
454 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
6d0f6bcf | 455 | #define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/ |
b765ffb7 SR |
456 | |
457 | /* Board-specific PCI */ | |
6d0f6bcf JCPV |
458 | #define CONFIG_SYS_PCI_TARGET_INIT |
459 | #define CONFIG_SYS_PCI_MASTER_INIT | |
b765ffb7 | 460 | |
6d0f6bcf JCPV |
461 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ |
462 | #define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */ | |
b765ffb7 SR |
463 | |
464 | #define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */ | |
2e721094 | 465 | #define CONFIG_WD_PERIOD 40000 /* in usec */ |
d32a874b | 466 | #define CONFIG_WD_MAX_RATE 66600 /* in ticks */ |
b765ffb7 SR |
467 | |
468 | /* | |
469 | * For booting Linux, the board info and command line data | |
470 | * have to be in the first 8 MB of memory, since this is | |
471 | * the maximum mapped by the Linux kernel during initialization. | |
472 | */ | |
6d0f6bcf | 473 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
b765ffb7 SR |
474 | |
475 | /*----------------------------------------------------------------------- | |
476 | * External Bus Controller (EBC) Setup | |
477 | *----------------------------------------------------------------------*/ | |
6d0f6bcf | 478 | #define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE |
b765ffb7 SR |
479 | |
480 | /* Memory Bank 0 (NOR-FLASH) initialization */ | |
6d0f6bcf JCPV |
481 | #define CONFIG_SYS_EBC_PB0AP 0x03050200 |
482 | #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0xfc000) | |
b765ffb7 SR |
483 | |
484 | /* Memory Bank 1 (Lime) initialization */ | |
6d0f6bcf JCPV |
485 | #define CONFIG_SYS_EBC_PB1AP 0x01004380 |
486 | #define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_LIME_BASE_0 | 0xdc000) | |
b765ffb7 SR |
487 | |
488 | /* Memory Bank 2 (FPGA) initialization */ | |
6d0f6bcf JCPV |
489 | #define CONFIG_SYS_EBC_PB2AP 0x01004400 |
490 | #define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA_BASE_0 | 0x1c000) | |
b765ffb7 SR |
491 | |
492 | /* Memory Bank 3 (FPGA2) initialization */ | |
6d0f6bcf JCPV |
493 | #define CONFIG_SYS_EBC_PB3AP 0x01004400 |
494 | #define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_FPGA_BASE_1 | 0x1c000) | |
b765ffb7 | 495 | |
6d0f6bcf | 496 | #define CONFIG_SYS_EBC_CFG 0xb8400000 |
b765ffb7 | 497 | |
04e6c38b SR |
498 | /*----------------------------------------------------------------------- |
499 | * Graphics (Fujitsu Lime) | |
500 | *----------------------------------------------------------------------*/ | |
b66091de | 501 | /* Lime Clock frequency is to set 100MHz */ |
6d0f6bcf | 502 | #define CONFIG_SYS_LIME_CLOCK_100MHZ 0x00000 |
b66091de AG |
503 | #if 0 |
504 | /* Lime Clock frequency for 133MHz */ | |
6d0f6bcf | 505 | #define CONFIG_SYS_LIME_CLOCK_133MHZ 0x10000 |
b66091de | 506 | #endif |
04e6c38b | 507 | |
b66091de AG |
508 | /* SDRAM parameter value; was 0x414FB7F2, caused several vertical bars |
509 | and pixel flare on display when 133MHz was configured. According to | |
510 | SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed Grade */ | |
6d0f6bcf | 511 | #ifdef CONFIG_SYS_LIME_CLOCK_133MHZ |
c28d3bbe WG |
512 | #define CONFIG_SYS_MB862xx_MMR 0x414FB7F3 |
513 | #define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_133MHZ | |
b66091de | 514 | #else |
c28d3bbe WG |
515 | #define CONFIG_SYS_MB862xx_MMR 0x414FB7F2 |
516 | #define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_100MHZ | |
b66091de | 517 | #endif |
04e6c38b | 518 | |
b765ffb7 SR |
519 | /*----------------------------------------------------------------------- |
520 | * GPIO Setup | |
521 | *----------------------------------------------------------------------*/ | |
6d0f6bcf JCPV |
522 | #define CONFIG_SYS_GPIO_PHY1_RST 12 |
523 | #define CONFIG_SYS_GPIO_FLASH_WP 14 | |
524 | #define CONFIG_SYS_GPIO_PHY0_RST 22 | |
525 | #define CONFIG_SYS_GPIO_DSPIC_READY 51 | |
526 | #define CONFIG_SYS_GPIO_EEPROM_EXT_WP 55 | |
527 | #define CONFIG_SYS_GPIO_HIGHSIDE 56 | |
528 | #define CONFIG_SYS_GPIO_EEPROM_INT_WP 57 | |
529 | #define CONFIG_SYS_GPIO_BOARD_RESET 58 | |
530 | #define CONFIG_SYS_GPIO_LIME_S 59 | |
531 | #define CONFIG_SYS_GPIO_LIME_RST 60 | |
532 | #define CONFIG_SYS_GPIO_SYSMON_STATUS 62 | |
533 | #define CONFIG_SYS_GPIO_WATCHDOG 63 | |
b765ffb7 SR |
534 | |
535 | /*----------------------------------------------------------------------- | |
536 | * PPC440 GPIO Configuration | |
537 | */ | |
6d0f6bcf | 538 | #define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ |
b765ffb7 SR |
539 | { \ |
540 | /* GPIO Core 0 */ \ | |
541 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \ | |
542 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \ | |
543 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \ | |
544 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \ | |
545 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \ | |
546 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \ | |
547 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \ | |
548 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \ | |
549 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \ | |
550 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \ | |
551 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \ | |
552 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \ | |
553 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \ | |
554 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \ | |
555 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \ | |
20d500d5 | 556 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO15 */ \ |
1636d1c8 | 557 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4) */ \ |
b765ffb7 SR |
558 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5) */ \ |
559 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6) */ \ | |
560 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMCTxD(7) */ \ | |
561 | {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \ | |
562 | {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \ | |
563 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \ | |
564 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0 */ \ | |
565 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 GMCTxD(2) */ \ | |
566 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 GMCTxD(3) */ \ | |
567 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \ | |
568 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \ | |
569 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 USB2D_TXVALID */ \ | |
570 | {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \ | |
571 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \ | |
572 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \ | |
573 | }, \ | |
574 | { \ | |
575 | /* GPIO Core 1 */ \ | |
576 | {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \ | |
577 | {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \ | |
578 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \ | |
579 | {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \ | |
580 | {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0) UART3_SIN*/ \ | |
581 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \ | |
582 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \ | |
583 | {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \ | |
584 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \ | |
585 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \ | |
586 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \ | |
587 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \ | |
588 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \ | |
589 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \ | |
590 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \ | |
591 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \ | |
592 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \ | |
593 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO49 Unselect via TraceSelect Bit */ \ | |
04e6c38b | 594 | {GPIO1_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \ |
b765ffb7 SR |
595 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \ |
596 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \ | |
20d500d5 | 597 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \ |
b765ffb7 SR |
598 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \ |
599 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 Unselect via TraceSelect Bit */ \ | |
600 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \ | |
601 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO57 Unselect via TraceSelect Bit */ \ | |
3e954beb | 602 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \ |
b765ffb7 SR |
603 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \ |
604 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \ | |
605 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \ | |
606 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \ | |
607 | {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \ | |
608 | } \ | |
609 | } | |
610 | ||
b765ffb7 SR |
611 | /* |
612 | * Internal Definitions | |
613 | * | |
614 | * Boot Flags | |
615 | */ | |
616 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
617 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
618 | ||
a22d4da9 | 619 | #if defined(CONFIG_CMD_KGDB) |
b765ffb7 SR |
620 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
621 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
622 | #endif | |
623 | #endif /* __CONFIG_H */ |