[people/ms/u-boot.git] / include / configs / m28evk.h

/*
 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
 * on behalf of DENX Software Engineering GmbH
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
#ifndef __M28EVK_CONFIG_H__
#define __M28EVK_CONFIG_H__

/*
 * SoC configurations
 */
#define CONFIG_MX28				/* i.MX28 SoC */
#define CONFIG_MXS_GPIO				/* GPIO control */
#define CONFIG_SYS_HZ		1000		/* Ticks per second */

/*
 * Define M28EVK machine type by hand until it lands in mach-types
 */
#define MACH_TYPE_M28EVK	3613

#define CONFIG_MACH_TYPE	MACH_TYPE_M28EVK

#include <asm/arch/regs-base.h>

#define CONFIG_SYS_NO_FLASH
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_ARCH_MISC_INIT

/*
 * SPL
 */
#define CONFIG_SPL
#define CONFIG_SPL_NO_CPU_SUPPORT_CODE
#define CONFIG_SPL_START_S_PATH		"arch/arm/cpu/arm926ejs/mxs"
#define CONFIG_SPL_LDSCRIPT	"arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds"
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_GPIO_SUPPORT

/*
 * U-Boot Commands
 */
#include <config_cmd_default.h>
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DOS_PARTITION

#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_GPIO
#define CONFIG_CMD_GREPENV
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_MMC
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NET
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
#define CONFIG_CMD_SETEXPR
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
#define CONFIG_CMD_USB
#define	CONFIG_VIDEO

#define CONFIG_REGEX			/* Enable regular expression support */

/*
 * Memory configurations
 */
#define CONFIG_NR_DRAM_BANKS		1		/* 1 bank of DRAM */
#define PHYS_SDRAM_1			0x40000000	/* Base address */
#define PHYS_SDRAM_1_SIZE		0x20000000	/* Max 512 MB RAM */
#define CONFIG_SYS_MALLOC_LEN		0x00400000	/* 4 MB for malloc */
#define CONFIG_SYS_GBL_DATA_SIZE	128		/* Initial data */
#define CONFIG_SYS_MEMTEST_START	0x40000000	/* Memtest start adr */
#define CONFIG_SYS_MEMTEST_END		0x40400000	/* 4 MB RAM test */
#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
/* Point initial SP in SRAM so SPL can use it too. */

#define CONFIG_SYS_INIT_RAM_ADDR	0x00000000
#define CONFIG_SYS_INIT_RAM_SIZE	(128 * 1024)

#define CONFIG_SYS_INIT_SP_OFFSET \
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/*
 * We need to sacrifice first 4 bytes of RAM here to avoid triggering some
 * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot
 * binary. In case there was more of this mess, 0x100 bytes are skipped.
 */
#define CONFIG_SYS_TEXT_BASE		0x40000100

/*
 * U-Boot general configurations
 */
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_PROMPT	"=> "
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O buffer size */
#define CONFIG_SYS_PBSIZE	\
	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
						/* Print buffer size */
#define CONFIG_SYS_MAXARGS	32		/* Max number of command args */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
						/* Boot argument buffer size */
#define CONFIG_VERSION_VARIABLE			/* U-BOOT version */
#define CONFIG_AUTO_COMPLETE			/* Command auto complete */
#define CONFIG_CMDLINE_EDITING			/* Command history etc */
#define CONFIG_SYS_HUSH_PARSER

/*
 * Serial Driver
 */
#define CONFIG_PL011_SERIAL
#define CONFIG_PL011_CLOCK		24000000
#define CONFIG_PL01x_PORTS		{ (void *)MXS_UARTDBG_BASE }
#define CONFIG_CONS_INDEX		0
#define CONFIG_BAUDRATE			115200	/* Default baud rate */

/*
 * MMC Driver
 */
#ifdef	CONFIG_CMD_MMC
#define CONFIG_MMC
#define CONFIG_BOUNCE_BUFFER
#define CONFIG_GENERIC_MMC
#define CONFIG_MXS_MMC
#endif

/*
 * APBH DMA
 */
#define CONFIG_APBH_DMA

/*
 * NAND
 */
#define CONFIG_ENV_SIZE			(16 * 1024)
#ifdef	CONFIG_CMD_NAND
#define CONFIG_NAND_MXS
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_BASE		0x60000000
#define CONFIG_SYS_NAND_5_ADDR_CYCLE

/* Environment is in NAND */
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
#define CONFIG_ENV_SECT_SIZE		(128 * 1024)
#define CONFIG_ENV_RANGE		(512 * 1024)
#define CONFIG_ENV_OFFSET		0x300000
#define CONFIG_ENV_OFFSET_REDUND	\
		(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)

#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define CONFIG_CMD_MTDPARTS
#define CONFIG_RBTREE
#define CONFIG_LZO
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#define MTDIDS_DEFAULT			"nand0=gpmi-nand"
#define MTDPARTS_DEFAULT			\
	"mtdparts=gpmi-nand:"			\
		"3m(bootloader)ro,"		\
		"512k(environment),"		\
		"512k(redundant-environment),"	\
		"4m(kernel),"			\
		"128k(fdt),"			\
		"8m(ramdisk),"			\
		"-(filesystem)"
#else
#define CONFIG_ENV_IS_NOWHERE
#endif

/*
 * Ethernet on SOC (FEC)
 */
#ifdef	CONFIG_CMD_NET
#define CONFIG_ETHPRIME			"FEC0"
#define CONFIG_FEC_MXC
#define CONFIG_MII
#define CONFIG_FEC_XCV_TYPE		RMII
#endif

/*
 * I2C
 */
#ifdef	CONFIG_CMD_I2C
#define CONFIG_I2C_MXS
#define CONFIG_HARD_I2C
#define CONFIG_SYS_I2C_SPEED		400000
#endif

/*
 * EEPROM
 */
#ifdef	CONFIG_CMD_EEPROM
#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
#endif

/*
 * RTC
 */
#ifdef	CONFIG_CMD_DATE
/* Use the internal RTC in the MXS chip */
#define CONFIG_RTC_INTERNAL
#ifdef	CONFIG_RTC_INTERNAL
#define CONFIG_RTC_MXS
#else
#define CONFIG_RTC_M41T62
#define CONFIG_SYS_I2C_RTC_ADDR		0x68
#define CONFIG_SYS_M41T11_BASE_YEAR	2000
#endif
#endif

/*
 * USB
 */
#ifdef	CONFIG_CMD_USB
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_MXS
#define CONFIG_EHCI_MXS_PORT0
#define CONFIG_EHCI_MXS_PORT1
#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_STORAGE
#endif

/*
 * SPI
 */
#ifdef	CONFIG_CMD_SPI
#define CONFIG_HARD_SPI
#define CONFIG_MXS_SPI
#define CONFIG_SPI_HALF_DUPLEX
#define CONFIG_DEFAULT_SPI_BUS		2
#define CONFIG_DEFAULT_SPI_CS		0
#define CONFIG_DEFAULT_SPI_MODE		SPI_MODE_0

/* SPI FLASH */
#ifdef	CONFIG_CMD_SF
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SF_DEFAULT_BUS		2
#define CONFIG_SF_DEFAULT_CS		0
#define CONFIG_SF_DEFAULT_SPEED		40000000
#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0

#define CONFIG_ENV_SPI_BUS		2
#define CONFIG_ENV_SPI_CS		0
#define CONFIG_ENV_SPI_MAX_HZ		40000000
#define CONFIG_ENV_SPI_MODE		SPI_MODE_0
#endif
#endif

/*
 * LCD
 */
#ifdef	CONFIG_VIDEO
#define	CONFIG_CFB_CONSOLE
#define	CONFIG_VIDEO_MXS
#define	CONFIG_VIDEO_LOGO
#define	CONFIG_VIDEO_SW_CURSOR
#define	CONFIG_VGA_AS_SINGLE_DEVICE
#define	CONFIG_SYS_CONSOLE_IS_IN_ENV
#define	CONFIG_SPLASH_SCREEN
#define	CONFIG_CMD_BMP
#define	CONFIG_BMP_16BPP
#define	CONFIG_VIDEO_BMP_RLE8
#define	CONFIG_VIDEO_BMP_GZIP
#define	CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(512 << 10)
#endif

/*
 * Boot Linux
 */
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_BOOTDELAY	3
#define CONFIG_BOOTFILE		"uImage"
#define CONFIG_BOOTARGS		"console=ttyAMA0,115200n8 "
#define CONFIG_BOOTCOMMAND	"run bootcmd_net"
#define CONFIG_LOADADDR		0x42000000
#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
#define CONFIG_OF_LIBFDT

/*
 * Extra Environments
 */
#define CONFIG_EXTRA_ENV_SETTINGS					\
	"update_nand_full_filename=u-boot.nand\0"			\
	"update_nand_firmware_filename=u-boot.sb\0"			\
	"update_sd_firmware_filename=u-boot.sd\0"			\
	"update_nand_firmware_maxsz=0x100000\0"				\
	"update_nand_stride=0x40\0"	/* MX28 datasheet ch. 12.12 */	\
	"update_nand_count=0x4\0"	/* MX28 datasheet ch. 12.12 */	\
	"update_nand_get_fcb_size="	/* Get size of FCB blocks */	\
		"nand device 0 ; "					\
		"nand info ; "						\
		"setexpr fcb_sz ${update_nand_stride} * ${update_nand_count};" \
		"setexpr update_nand_fcb ${fcb_sz} * ${nand_writesize}\0" \
	"update_nand_full="		/* Update FCB, DBBT and FW */	\
		"if tftp ${update_nand_full_filename} ; then "		\
		"run update_nand_get_fcb_size ; "			\
		"nand scrub -y 0x0 ${filesize} ; "			\
		"nand write.raw ${loadaddr} 0x0 ${fcb_sz} ; "	\
		"setexpr update_off ${loadaddr} + ${update_nand_fcb} ; " \
		"setexpr update_sz ${filesize} - ${update_nand_fcb} ; " \
		"nand write ${update_off} ${update_nand_fcb} ${update_sz} ; " \
		"fi\0"							\
	"update_nand_firmware="		/* Update only firmware */	\
		"if tftp ${update_nand_firmware_filename} ; then "	\
		"run update_nand_get_fcb_size ; "			\
		"setexpr fcb_sz ${update_nand_fcb} * 2 ; " /* FCB + DBBT */ \
		"setexpr fw_sz ${update_nand_firmware_maxsz} * 2 ; "	\
		"setexpr fw_off ${fcb_sz} + ${update_nand_firmware_maxsz};" \
		"nand erase ${fcb_sz} ${fw_sz} ; "			\
		"nand write ${loadaddr} ${fcb_sz} ${filesize} ; "	\
		"nand write ${loadaddr} ${fw_off} ${filesize} ; "	\
		"fi\0"							\
	"update_sd_firmware="		/* Update the SD firmware partition */ \
		"if mmc rescan ; then "					\
		"if tftp ${update_sd_firmware_filename} ; then "	\
		"setexpr fw_sz ${filesize} / 0x200 ; "	/* SD block size */ \
		"setexpr fw_sz ${fw_sz} + 1 ; "				\
		"mmc write ${loadaddr} 0x800 ${fw_sz} ; "		\
		"fi ; "							\
		"fi\0"

#endif /* __M28EVK_CONFIG_H__ */
Commit	Line	Data
fc102728 MV	1	/*
	2	* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
	3	* on behalf of DENX Software Engineering GmbH
	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License as
	7	* published by the Free Software Foundation; either version 2 of
	8	* the License, or (at your option) any later version.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	18	* MA 02111-1307 USA
	19	*/
212033fc OS	20	#ifndef __M28EVK_CONFIG_H__
212033fc OS	21	#define __M28EVK_CONFIG_H__
fc102728	22
fc102728 MV	23	/*
	24	* SoC configurations
	25	*/
5f71bca7 WD	26	#define CONFIG_MX28 /* i.MX28 SoC */
	27	#define CONFIG_MXS_GPIO /* GPIO control */
	28	#define CONFIG_SYS_HZ 1000 /* Ticks per second */
fc102728 MV	29
	30	/*
	31	* Define M28EVK machine type by hand until it lands in mach-types
	32	*/
5f71bca7	33	#define MACH_TYPE_M28EVK 3613
fc102728	34
5f71bca7	35	#define CONFIG_MACH_TYPE MACH_TYPE_M28EVK
fc102728	36
e229d445 OS	37	#include <asm/arch/regs-base.h>
e229d445 OS	38
5f71bca7 WD	39	#define CONFIG_SYS_NO_FLASH
	40	#define CONFIG_BOARD_EARLY_INIT_F
	41	#define CONFIG_ARCH_MISC_INIT
fc102728	42
04fe4273 MV	43	/*
	44	* SPL
	45	*/
5f71bca7 WD	46	#define CONFIG_SPL
	47	#define CONFIG_SPL_NO_CPU_SUPPORT_CODE
	48	#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs"
	49	#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds"
	50	#define CONFIG_SPL_LIBCOMMON_SUPPORT
	51	#define CONFIG_SPL_LIBGENERIC_SUPPORT
	52	#define CONFIG_SPL_GPIO_SUPPORT
04fe4273	53
fc102728 MV	54	/*
	55	* U-Boot Commands
	56	*/
	57	#include <config_cmd_default.h>
5f71bca7 WD	58	#define CONFIG_DISPLAY_CPUINFO
5f71bca7 WD	59	#define CONFIG_DOS_PARTITION
fc102728	60
5f71bca7 WD	61	#define CONFIG_CMD_CACHE
	62	#define CONFIG_CMD_DATE
	63	#define CONFIG_CMD_DHCP
	64	#define CONFIG_CMD_EEPROM
	65	#define CONFIG_CMD_EXT2
	66	#define CONFIG_CMD_FAT
	67	#define CONFIG_CMD_GPIO
ee747a21	68	#define CONFIG_CMD_GREPENV
5f71bca7 WD	69	#define CONFIG_CMD_I2C
	70	#define CONFIG_CMD_MII
	71	#define CONFIG_CMD_MMC
	72	#define CONFIG_CMD_NAND
	73	#define CONFIG_CMD_NET
	74	#define CONFIG_CMD_NFS
	75	#define CONFIG_CMD_PING
	76	#define CONFIG_CMD_SETEXPR
	77	#define CONFIG_CMD_SF
	78	#define CONFIG_CMD_SPI
	79	#define CONFIG_CMD_USB
d782c1fe	80	#define CONFIG_VIDEO
fc102728	81
ee747a21 WD	82	#define CONFIG_REGEX /* Enable regular expression support */
ee747a21 WD	83
fc102728 MV	84	/*
	85	* Memory configurations
	86	*/
5f71bca7 WD	87	#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
	88	#define PHYS_SDRAM_1 0x40000000 /* Base address */
	89	#define PHYS_SDRAM_1_SIZE 0x20000000 /* Max 512 MB RAM */
	90	#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */
	91	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Initial data */
	92	#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */
	93	#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */
	94	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
fc102728	95	/* Point initial SP in SRAM so SPL can use it too. */
1084606c	96
9ed5dfa8	97	#define CONFIG_SYS_INIT_RAM_ADDR 0x00000000
1084606c FE	98	#define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024)
	99
	100	#define CONFIG_SYS_INIT_SP_OFFSET \
	101	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	102	#define CONFIG_SYS_INIT_SP_ADDR \
	103	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
fc102728 MV	104	/*
	105	* We need to sacrifice first 4 bytes of RAM here to avoid triggering some
	106	* strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot
	107	* binary. In case there was more of this mess, 0x100 bytes are skipped.
	108	*/
5f71bca7	109	#define CONFIG_SYS_TEXT_BASE 0x40000100
fc102728 MV	110
	111	/*
	112	* U-Boot general configurations
	113	*/
5f71bca7 WD	114	#define CONFIG_SYS_LONGHELP
	115	#define CONFIG_SYS_PROMPT "=> "
	116	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
	117	#define CONFIG_SYS_PBSIZE \
fc102728 MV	118	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
fc102728 MV	119	/* Print buffer size */
5f71bca7 WD	120	#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
5f71bca7 WD	121	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
fc102728	122	/* Boot argument buffer size */
5f71bca7 WD	123	#define CONFIG_VERSION_VARIABLE /* U-BOOT version */
	124	#define CONFIG_AUTO_COMPLETE /* Command auto complete */
	125	#define CONFIG_CMDLINE_EDITING /* Command history etc */
	126	#define CONFIG_SYS_HUSH_PARSER
fc102728 MV	127
	128	/*
	129	* Serial Driver
	130	*/
5f71bca7 WD	131	#define CONFIG_PL011_SERIAL
	132	#define CONFIG_PL011_CLOCK 24000000
	133	#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE }
	134	#define CONFIG_CONS_INDEX 0
	135	#define CONFIG_BAUDRATE 115200 /* Default baud rate */
fc102728 MV	136
	137	/*
	138	* MMC Driver
	139	*/
	140	#ifdef CONFIG_CMD_MMC
5f71bca7 WD	141	#define CONFIG_MMC
	142	#define CONFIG_BOUNCE_BUFFER
	143	#define CONFIG_GENERIC_MMC
	144	#define CONFIG_MXS_MMC
fc102728 MV	145	#endif
fc102728 MV	146
e87ca8c0 MV	147	/*
	148	* APBH DMA
	149	*/
	150	#define CONFIG_APBH_DMA
	151
fc102728 MV	152	/*
	153	* NAND
	154	*/
5f71bca7	155	#define CONFIG_ENV_SIZE (16 * 1024)
fc102728	156	#ifdef CONFIG_CMD_NAND
5f71bca7 WD	157	#define CONFIG_NAND_MXS
	158	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	159	#define CONFIG_SYS_NAND_BASE 0x60000000
	160	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
fc102728 MV	161
fc102728 MV	162	/* Environment is in NAND */
5f71bca7 WD	163	#define CONFIG_ENV_IS_IN_NAND
	164	#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
	165	#define CONFIG_ENV_SECT_SIZE (128 * 1024)
	166	#define CONFIG_ENV_RANGE (512 * 1024)
	167	#define CONFIG_ENV_OFFSET 0x300000
	168	#define CONFIG_ENV_OFFSET_REDUND \
fc102728 MV	169	(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
fc102728 MV	170
5f71bca7 WD	171	#define CONFIG_CMD_UBI
	172	#define CONFIG_CMD_UBIFS
	173	#define CONFIG_CMD_MTDPARTS
	174	#define CONFIG_RBTREE
	175	#define CONFIG_LZO
	176	#define CONFIG_MTD_DEVICE
	177	#define CONFIG_MTD_PARTITIONS
	178	#define MTDIDS_DEFAULT "nand0=gpmi-nand"
	179	#define MTDPARTS_DEFAULT \
c16ecb09	180	"mtdparts=gpmi-nand:" \
fc102728 MV	181	"3m(bootloader)ro," \
	182	"512k(environment)," \
	183	"512k(redundant-environment)," \
	184	"4m(kernel)," \
1f75b541 MV	185	"128k(fdt)," \
1f75b541 MV	186	"8m(ramdisk)," \
fc102728	187	"-(filesystem)"
c660a541	188	#else
5f71bca7	189	#define CONFIG_ENV_IS_NOWHERE
fc102728 MV	190	#endif
	191
	192	/*
	193	* Ethernet on SOC (FEC)
	194	*/
	195	#ifdef CONFIG_CMD_NET
5f71bca7 WD	196	#define CONFIG_ETHPRIME "FEC0"
	197	#define CONFIG_FEC_MXC
	198	#define CONFIG_MII
	199	#define CONFIG_FEC_XCV_TYPE RMII
fc102728 MV	200	#endif
	201
	202	/*
	203	* I2C
	204	*/
	205	#ifdef CONFIG_CMD_I2C
5f71bca7 WD	206	#define CONFIG_I2C_MXS
	207	#define CONFIG_HARD_I2C
	208	#define CONFIG_SYS_I2C_SPEED 400000
fc102728 MV	209	#endif
	210
	211	/*
	212	* EEPROM
	213	*/
	214	#ifdef CONFIG_CMD_EEPROM
5f71bca7 WD	215	#define CONFIG_SYS_I2C_MULTI_EEPROMS
5f71bca7 WD	216	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
fc102728 MV	217	#endif
	218
	219	/*
	220	* RTC
	221	*/
	222	#ifdef CONFIG_CMD_DATE
	223	/* Use the internal RTC in the MXS chip */
5f71bca7	224	#define CONFIG_RTC_INTERNAL
fc102728	225	#ifdef CONFIG_RTC_INTERNAL
5f71bca7	226	#define CONFIG_RTC_MXS
fc102728	227	#else
5f71bca7 WD	228	#define CONFIG_RTC_M41T62
	229	#define CONFIG_SYS_I2C_RTC_ADDR 0x68
	230	#define CONFIG_SYS_M41T11_BASE_YEAR 2000
fc102728 MV	231	#endif
	232	#endif
	233
8f59bc1f MV	234	/*
	235	* USB
	236	*/
	237	#ifdef CONFIG_CMD_USB
5f71bca7 WD	238	#define CONFIG_USB_EHCI
5f71bca7 WD	239	#define CONFIG_USB_EHCI_MXS
afa87210 MV	240	#define CONFIG_EHCI_MXS_PORT0
	241	#define CONFIG_EHCI_MXS_PORT1
	242	#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
5f71bca7 WD	243	#define CONFIG_EHCI_IS_TDI
5f71bca7 WD	244	#define CONFIG_USB_STORAGE
8f59bc1f MV	245	#endif
8f59bc1f MV	246
fc102728 MV	247	/*
	248	* SPI
	249	*/
	250	#ifdef CONFIG_CMD_SPI
5f71bca7 WD	251	#define CONFIG_HARD_SPI
	252	#define CONFIG_MXS_SPI
	253	#define CONFIG_SPI_HALF_DUPLEX
	254	#define CONFIG_DEFAULT_SPI_BUS 2
	255	#define CONFIG_DEFAULT_SPI_CS 0
	256	#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0
fc102728 MV	257
	258	/* SPI FLASH */
	259	#ifdef CONFIG_CMD_SF
5f71bca7 WD	260	#define CONFIG_SPI_FLASH
	261	#define CONFIG_SPI_FLASH_STMICRO
	262	#define CONFIG_SF_DEFAULT_BUS 2
	263	#define CONFIG_SF_DEFAULT_CS 0
	264	#define CONFIG_SF_DEFAULT_SPEED 40000000
	265	#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
fc102728	266
5f71bca7 WD	267	#define CONFIG_ENV_SPI_BUS 2
	268	#define CONFIG_ENV_SPI_CS 0
	269	#define CONFIG_ENV_SPI_MAX_HZ 40000000
	270	#define CONFIG_ENV_SPI_MODE SPI_MODE_0
fc102728 MV	271	#endif
	272	#endif
	273
d782c1fe MV	274	/*
	275	* LCD
	276	*/
	277	#ifdef CONFIG_VIDEO
	278	#define CONFIG_CFB_CONSOLE
	279	#define CONFIG_VIDEO_MXS
	280	#define CONFIG_VIDEO_LOGO
	281	#define CONFIG_VIDEO_SW_CURSOR
	282	#define CONFIG_VGA_AS_SINGLE_DEVICE
	283	#define CONFIG_SYS_CONSOLE_IS_IN_ENV
	284	#define CONFIG_SPLASH_SCREEN
	285	#define CONFIG_CMD_BMP
	286	#define CONFIG_BMP_16BPP
	287	#define CONFIG_VIDEO_BMP_RLE8
	288	#define CONFIG_VIDEO_BMP_GZIP
	289	#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (512 << 10)
	290	#endif
	291
fc102728 MV	292	/*
	293	* Boot Linux
	294	*/
5f71bca7 WD	295	#define CONFIG_CMDLINE_TAG
	296	#define CONFIG_SETUP_MEMORY_TAGS
	297	#define CONFIG_BOOTDELAY 3
	298	#define CONFIG_BOOTFILE "uImage"
	299	#define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 "
	300	#define CONFIG_BOOTCOMMAND "run bootcmd_net"
	301	#define CONFIG_LOADADDR 0x42000000
	302	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
	303	#define CONFIG_OF_LIBFDT
fc102728 MV	304
	305	/*
	306	* Extra Environments
	307	*/
5f71bca7	308	#define CONFIG_EXTRA_ENV_SETTINGS \
fc102728 MV	309	"update_nand_full_filename=u-boot.nand\0" \
fc102728 MV	310	"update_nand_firmware_filename=u-boot.sb\0" \
9a0f98d3	311	"update_sd_firmware_filename=u-boot.sd\0" \
fc102728 MV	312	"update_nand_firmware_maxsz=0x100000\0" \
	313	"update_nand_stride=0x40\0" /* MX28 datasheet ch. 12.12 */ \
	314	"update_nand_count=0x4\0" /* MX28 datasheet ch. 12.12 */ \
	315	"update_nand_get_fcb_size=" /* Get size of FCB blocks */ \
	316	"nand device 0 ; " \
	317	"nand info ; " \
	318	"setexpr fcb_sz ${update_nand_stride} * ${update_nand_count};" \
	319	"setexpr update_nand_fcb ${fcb_sz} * ${nand_writesize}\0" \
	320	"update_nand_full=" /* Update FCB, DBBT and FW */ \
	321	"if tftp ${update_nand_full_filename} ; then " \
	322	"run update_nand_get_fcb_size ; " \
	323	"nand scrub -y 0x0 ${filesize} ; " \
71779d5b	324	"nand write.raw ${loadaddr} 0x0 ${fcb_sz} ; " \
fc102728 MV	325	"setexpr update_off ${loadaddr} + ${update_nand_fcb} ; " \
	326	"setexpr update_sz ${filesize} - ${update_nand_fcb} ; " \
	327	"nand write ${update_off} ${update_nand_fcb} ${update_sz} ; " \
	328	"fi\0" \
	329	"update_nand_firmware=" /* Update only firmware */ \
	330	"if tftp ${update_nand_firmware_filename} ; then " \
	331	"run update_nand_get_fcb_size ; " \
	332	"setexpr fcb_sz ${update_nand_fcb} * 2 ; " /* FCB + DBBT */ \
	333	"setexpr fw_sz ${update_nand_firmware_maxsz} * 2 ; " \
	334	"setexpr fw_off ${fcb_sz} + ${update_nand_firmware_maxsz};" \
	335	"nand erase ${fcb_sz} ${fw_sz} ; " \
	336	"nand write ${loadaddr} ${fcb_sz} ${filesize} ; " \
	337	"nand write ${loadaddr} ${fw_off} ${filesize} ; " \
9a0f98d3 MV	338	"fi\0" \
	339	"update_sd_firmware=" /* Update the SD firmware partition */ \
	340	"if mmc rescan ; then " \
	341	"if tftp ${update_sd_firmware_filename} ; then " \
	342	"setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \
	343	"setexpr fw_sz ${fw_sz} + 1 ; " \
	344	"mmc write ${loadaddr} 0x800 ${fw_sz} ; " \
	345	"fi ; " \
fc102728 MV	346	"fi\0"
fc102728 MV	347
212033fc	348	#endif /* __M28EVK_CONFIG_H__ */