[people/ms/u-boot.git] / include / configs / ms7750se.h

/*
 * Configuation settings for the Hitachi Solution Engine 7750
 *
 * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __MS7750SE_H
#define __MS7750SE_H

#define CONFIG_CPU_SH7750	1
/* #define CONFIG_CPU_SH7751	1 */
/* #define CONFIG_CPU_TYPE_R	1 */
#define CONFIG_MS7750SE		1
#define __LITTLE_ENDIAN__	1

#define CONFIG_DISPLAY_BOARDINFO

/*
 * Command line configuration.
 */
#define CONFIG_SCIF_CONSOLE	1
#define CONFIG_BAUDRATE		38400
#define CONFIG_CONS_SCIF1	1
#define CONFIG_BOARD_LATE_INIT

#define CONFIG_BOOTARGS		"console=ttySC0,38400"
#define CONFIG_ENV_OVERWRITE	1

/* SDRAM */
#define CONFIG_SYS_SDRAM_BASE		(0x8C000000)
#define CONFIG_SYS_SDRAM_SIZE		(64 * 1024 * 1024)

#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_CBSIZE		256
#define CONFIG_SYS_PBSIZE		256
#define CONFIG_SYS_MAXARGS		16
#define CONFIG_SYS_BARGSIZE		512

#define CONFIG_SYS_TEXT_BASE		0x8FFC0000
#define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_TEXT_BASE - 0x100000)

/* NOR Flash */
/* #define CONFIG_SYS_FLASH_BASE		(0xA1000000)*/
#define CONFIG_SYS_FLASH_BASE		(0xA0000000)
#define CONFIG_SYS_MAX_FLASH_BANKS	(1)	/* Max number of
					 * Flash memory banks
					 */
#define CONFIG_SYS_MAX_FLASH_SECT	142
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }

#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE)	/* Address of u-boot image in Flash */
#define CONFIG_SYS_MONITOR_LEN		(128 * 1024)
#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)		/* Size of DRAM reserved for malloc() use */

#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
#define CONFIG_SYS_RX_ETH_BUFFER	(8)

#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#undef CONFIG_SYS_FLASH_CFI_BROKEN_TABLE
#undef  CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_SYS_FLASH_EMPTY_INFO				/* print 'E' for empty sector on flinfo */

#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE	0x20000
#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_SYS_FLASH_ERASE_TOUT	120000
#define CONFIG_SYS_FLASH_WRITE_TOUT	500

/* Board Clock */
#define CONFIG_SYS_CLK_FREQ	33333333
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV		4

#endif /* __MS7750SE_H */
Commit	Line	Data
047375bf NI	1	/*
	2	* Configuation settings for the Hitachi Solution Engine 7750
	3	*
	4	* Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
047375bf NI	7	*/
	8
	9	#ifndef __MS7750SE_H
	10	#define __MS7750SE_H
69df3c4d	11
69df3c4d	12	#define CONFIG_CPU_SH7750 1
047375bf NI	13	/* #define CONFIG_CPU_SH7751 1 */
047375bf NI	14	/* #define CONFIG_CPU_TYPE_R 1 */
69df3c4d NI	15	#define CONFIG_MS7750SE 1
	16	#define __LITTLE_ENDIAN__ 1
	17
18a40e84 VZ	18	#define CONFIG_DISPLAY_BOARDINFO
18a40e84 VZ	19
047375bf NI	20	/*
	21	* Command line configuration.
	22	*/
6c58a030	23	#define CONFIG_SCIF_CONSOLE 1
69df3c4d NI	24	#define CONFIG_BAUDRATE 38400
69df3c4d NI	25	#define CONFIG_CONS_SCIF1 1
9660e442	26	#define CONFIG_BOARD_LATE_INIT
69df3c4d	27
53677ef1	28	#define CONFIG_BOOTARGS "console=ttySC0,38400"
69df3c4d NI	29	#define CONFIG_ENV_OVERWRITE 1
69df3c4d NI	30
047375bf	31	/* SDRAM */
6d0f6bcf JCPV	32	#define CONFIG_SYS_SDRAM_BASE (0x8C000000)
	33	#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
	34
	35	#define CONFIG_SYS_LONGHELP
6d0f6bcf JCPV	36	#define CONFIG_SYS_CBSIZE 256
	37	#define CONFIG_SYS_PBSIZE 256
	38	#define CONFIG_SYS_MAXARGS 16
	39	#define CONFIG_SYS_BARGSIZE 512
69df3c4d	40
da8241ba	41	#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
6d0f6bcf	42	#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
14d0a02a	43	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
69df3c4d	44
047375bf	45	/* NOR Flash */
6d0f6bcf JCPV	46	/* #define CONFIG_SYS_FLASH_BASE (0xA1000000)*/
	47	#define CONFIG_SYS_FLASH_BASE (0xA0000000)
	48	#define CONFIG_SYS_MAX_FLASH_BANKS (1) /* Max number of
53677ef1 WD	49	* Flash memory banks
53677ef1 WD	50	*/
6d0f6bcf JCPV	51	#define CONFIG_SYS_MAX_FLASH_SECT 142
6d0f6bcf JCPV	52	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
69df3c4d	53
6d0f6bcf JCPV	54	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
	55	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) /* Address of u-boot image in Flash */
	56	#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
	57	#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */
69df3c4d	58
6d0f6bcf JCPV	59	#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
6d0f6bcf JCPV	60	#define CONFIG_SYS_RX_ETH_BUFFER (8)
69df3c4d	61
6d0f6bcf	62	#define CONFIG_SYS_FLASH_CFI
00b1883a	63	#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf JCPV	64	#undef CONFIG_SYS_FLASH_CFI_BROKEN_TABLE
	65	#undef CONFIG_SYS_FLASH_QUIET_TEST
	66	#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
69df3c4d	67
5a1aceb0	68	#define CONFIG_ENV_IS_IN_FLASH
0e8d1586 JCPV	69	#define CONFIG_ENV_SECT_SIZE 0x20000
0e8d1586 JCPV	70	#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
6d0f6bcf JCPV	71	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
	72	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
	73	#define CONFIG_SYS_FLASH_WRITE_TOUT 500
69df3c4d	74
047375bf	75	/* Board Clock */
69df3c4d	76	#define CONFIG_SYS_CLK_FREQ 33333333
684a501e NI	77	#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
684a501e NI	78	#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
be45c632	79	#define CONFIG_SYS_TMU_CLK_DIV 4
69df3c4d	80
047375bf	81	#endif /* __MS7750SE_H */