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b5dc9b30 GL |
1 | /* |
2 | * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de> | |
3 | * | |
4 | * Configuration settings for the MX31ADS Freescale board. | |
5 | * | |
3765b3e7 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
b5dc9b30 GL |
7 | */ |
8 | ||
9 | #ifndef __CONFIG_H | |
10 | #define __CONFIG_H | |
11 | ||
86271115 | 12 | #include <asm/arch/imx-regs.h> |
b5dc9b30 GL |
13 | |
14 | /* High Level Configuration Options */ | |
3fd968e9 | 15 | #define CONFIG_MX31 1 /* This is a mx31 */ |
b5dc9b30 | 16 | |
4ac2e2d6 FE |
17 | #define CONFIG_SYS_TEXT_BASE 0xA0000000 |
18 | ||
da3598ac FE |
19 | #define CONFIG_MACH_TYPE MACH_TYPE_MX31ADS |
20 | ||
b5dc9b30 GL |
21 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
22 | #define CONFIG_SETUP_MEMORY_TAGS 1 | |
23 | #define CONFIG_INITRD_TAG 1 | |
24 | ||
25 | /* | |
26 | * Size of malloc() pool | |
27 | */ | |
6d0f6bcf | 28 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) |
b5dc9b30 GL |
29 | |
30 | /* | |
31 | * Hardware drivers | |
32 | */ | |
33 | ||
40f6fffe SB |
34 | #define CONFIG_MXC_UART |
35 | #define CONFIG_MXC_UART_BASE UART1_BASE | |
b5dc9b30 | 36 | |
0a0b606f GL |
37 | #define CONFIG_HARD_SPI 1 |
38 | #define CONFIG_MXC_SPI 1 | |
d255bb0e | 39 | #define CONFIG_DEFAULT_SPI_BUS 1 |
9f481e95 | 40 | #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) |
5bd9a9b0 | 41 | #define CONFIG_MXC_GPIO |
0a0b606f | 42 | |
d7d6780f | 43 | /* PMIC Controller */ |
be3b51aa ŁM |
44 | #define CONFIG_POWER |
45 | #define CONFIG_POWER_SPI | |
46 | #define CONFIG_POWER_FSL | |
dfe5e14f SB |
47 | #define CONFIG_FSL_PMIC_BUS 1 |
48 | #define CONFIG_FSL_PMIC_CS 0 | |
49 | #define CONFIG_FSL_PMIC_CLK 1000000 | |
9f481e95 | 50 | #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) |
d7d6780f | 51 | #define CONFIG_FSL_PMIC_BITLEN 32 |
4e8b7544 | 52 | #define CONFIG_RTC_MC13XXX |
0a0b606f | 53 | |
b5dc9b30 GL |
54 | /* allow to overwrite serial and ethaddr */ |
55 | #define CONFIG_ENV_OVERWRITE | |
56 | #define CONFIG_CONS_INDEX 1 | |
b5dc9b30 | 57 | |
7602ed50 | 58 | #define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */ |
0a0b606f GL |
59 | |
60 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
61 | "netdev=eth0\0" \ | |
62 | "uboot_addr=0xa0000000\0" \ | |
63 | "uboot=mx31ads/u-boot.bin\0" \ | |
64 | "kernel=mx31ads/uImage\0" \ | |
65 | "nfsroot=/opt/eldk/arm\0" \ | |
66 | "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \ | |
67 | "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \ | |
68 | "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ | |
69 | "bootcmd=run bootcmd_net\0" \ | |
70 | "bootcmd_net=run bootargs_base bootargs_nfs; " \ | |
71 | "tftpboot ${loadaddr} ${kernel}; bootm\0" \ | |
72 | "prg_uboot=tftpboot ${loadaddr} ${uboot}; " \ | |
73 | "protect off ${uboot_addr} 0xa003ffff; " \ | |
74 | "erase ${uboot_addr} 0xa003ffff; " \ | |
75 | "cp.b ${loadaddr} ${uboot_addr} ${filesize}; " \ | |
76 | "setenv filesize; saveenv\0" | |
b5dc9b30 | 77 | |
b1c0eaac BW |
78 | #define CONFIG_CS8900 |
79 | #define CONFIG_CS8900_BASE 0xb4020300 | |
80 | #define CONFIG_CS8900_BUS16 1 /* follow the Linux driver */ | |
d23ff682 GL |
81 | |
82 | /* | |
83 | * The MX31ADS board seems to have a hardware "peculiarity" confirmed under | |
84 | * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A | |
85 | * controller inverted. The controller is capable of detecting and correcting | |
86 | * this, but it needs 4 network packets for that. Which means, at startup, you | |
87 | * will not receive answers to the first 4 packest, unless there have been some | |
88 | * broadcasts on the network, or your board is on a hub. Reducing the ARP | |
89 | * timeout from default 5 seconds to 200ms we speed up the initial TFTP | |
90 | * transfer, should the user wish one, significantly. | |
91 | */ | |
92 | #define CONFIG_ARP_TIMEOUT 200UL | |
b5dc9b30 GL |
93 | |
94 | /* | |
95 | * Miscellaneous configurable options | |
96 | */ | |
6d0f6bcf | 97 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
b5dc9b30 | 98 | |
6d0f6bcf JCPV |
99 | #define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ |
100 | #define CONFIG_SYS_MEMTEST_END 0x10000 | |
b5dc9b30 | 101 | |
6d0f6bcf | 102 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR |
b5dc9b30 | 103 | |
b5dc9b30 GL |
104 | #define CONFIG_CMDLINE_EDITING 1 |
105 | ||
b5dc9b30 GL |
106 | /*----------------------------------------------------------------------- |
107 | * Physical Memory Map | |
108 | */ | |
109 | #define CONFIG_NR_DRAM_BANKS 1 | |
110 | #define PHYS_SDRAM_1 CSD0_BASE | |
111 | #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) | |
4ac2e2d6 FE |
112 | |
113 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 | |
114 | #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR | |
115 | #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE | |
116 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ | |
117 | GENERATED_GBL_DATA_SIZE) | |
118 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ | |
119 | CONFIG_SYS_GBL_DATA_OFFSET) | |
b5dc9b30 GL |
120 | |
121 | /*----------------------------------------------------------------------- | |
122 | * FLASH and environment organization | |
123 | */ | |
6d0f6bcf JCPV |
124 | #define CONFIG_SYS_FLASH_BASE CS0_BASE |
125 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
126 | #define CONFIG_SYS_MAX_FLASH_SECT 262 /* max number of sectors on one chip */ | |
127 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */ | |
128 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256KiB */ | |
b5dc9b30 | 129 | |
ba8dcca7 | 130 | #define CONFIG_ENV_SECT_SIZE (128 * 1024) |
0e8d1586 | 131 | #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE |
ba8dcca7 | 132 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
d23ff682 GL |
133 | |
134 | /* Address and size of Redundant Environment Sector */ | |
ba8dcca7 | 135 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) |
0e8d1586 | 136 | #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE |
d23ff682 | 137 | |
b5dc9b30 GL |
138 | /*----------------------------------------------------------------------- |
139 | * CFI FLASH driver setup | |
140 | */ | |
6d0f6bcf | 141 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */ |
00b1883a | 142 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ |
d23ff682 | 143 | #define CONFIG_FLASH_SPANSION_S29WS_N 1 /* A non-standard buffered write algorithm */ |
6d0f6bcf JCPV |
144 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ |
145 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */ | |
b5dc9b30 GL |
146 | |
147 | /* | |
148 | * JFFS2 partitions | |
149 | */ | |
b5dc9b30 GL |
150 | #define CONFIG_JFFS2_DEV "nor0" |
151 | ||
152 | #endif /* __CONFIG_H */ |