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b5dc9b30 GL |
1 | /* |
2 | * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de> | |
3 | * | |
4 | * Configuration settings for the MX31ADS Freescale board. | |
5 | * | |
3765b3e7 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
b5dc9b30 GL |
7 | */ |
8 | ||
9 | #ifndef __CONFIG_H | |
10 | #define __CONFIG_H | |
11 | ||
86271115 | 12 | #include <asm/arch/imx-regs.h> |
b5dc9b30 GL |
13 | |
14 | /* High Level Configuration Options */ | |
3fd968e9 | 15 | #define CONFIG_MX31 1 /* This is a mx31 */ |
b5dc9b30 | 16 | |
b5dc9b30 GL |
17 | #define CONFIG_DISPLAY_BOARDINFO |
18 | ||
4ac2e2d6 FE |
19 | #define CONFIG_SYS_TEXT_BASE 0xA0000000 |
20 | ||
da3598ac FE |
21 | #define CONFIG_MACH_TYPE MACH_TYPE_MX31ADS |
22 | ||
b5dc9b30 GL |
23 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
24 | #define CONFIG_SETUP_MEMORY_TAGS 1 | |
25 | #define CONFIG_INITRD_TAG 1 | |
26 | ||
27 | /* | |
28 | * Size of malloc() pool | |
29 | */ | |
6d0f6bcf | 30 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) |
b5dc9b30 GL |
31 | |
32 | /* | |
33 | * Hardware drivers | |
34 | */ | |
35 | ||
40f6fffe SB |
36 | #define CONFIG_MXC_UART |
37 | #define CONFIG_MXC_UART_BASE UART1_BASE | |
b5dc9b30 | 38 | |
0a0b606f GL |
39 | #define CONFIG_HARD_SPI 1 |
40 | #define CONFIG_MXC_SPI 1 | |
d255bb0e | 41 | #define CONFIG_DEFAULT_SPI_BUS 1 |
9f481e95 | 42 | #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) |
5bd9a9b0 | 43 | #define CONFIG_MXC_GPIO |
0a0b606f | 44 | |
d7d6780f | 45 | /* PMIC Controller */ |
be3b51aa ŁM |
46 | #define CONFIG_POWER |
47 | #define CONFIG_POWER_SPI | |
48 | #define CONFIG_POWER_FSL | |
dfe5e14f SB |
49 | #define CONFIG_FSL_PMIC_BUS 1 |
50 | #define CONFIG_FSL_PMIC_CS 0 | |
51 | #define CONFIG_FSL_PMIC_CLK 1000000 | |
9f481e95 | 52 | #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) |
d7d6780f | 53 | #define CONFIG_FSL_PMIC_BITLEN 32 |
4e8b7544 | 54 | #define CONFIG_RTC_MC13XXX |
0a0b606f | 55 | |
b5dc9b30 GL |
56 | /* allow to overwrite serial and ethaddr */ |
57 | #define CONFIG_ENV_OVERWRITE | |
58 | #define CONFIG_CONS_INDEX 1 | |
59 | #define CONFIG_BAUDRATE 115200 | |
b5dc9b30 GL |
60 | |
61 | /*********************************************************** | |
62 | * Command definition | |
63 | ***********************************************************/ | |
0a0b606f | 64 | #define CONFIG_CMD_DATE |
b5dc9b30 | 65 | |
b5dc9b30 | 66 | |
7602ed50 | 67 | #define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */ |
0a0b606f GL |
68 | |
69 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
70 | "netdev=eth0\0" \ | |
71 | "uboot_addr=0xa0000000\0" \ | |
72 | "uboot=mx31ads/u-boot.bin\0" \ | |
73 | "kernel=mx31ads/uImage\0" \ | |
74 | "nfsroot=/opt/eldk/arm\0" \ | |
75 | "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \ | |
76 | "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \ | |
77 | "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ | |
78 | "bootcmd=run bootcmd_net\0" \ | |
79 | "bootcmd_net=run bootargs_base bootargs_nfs; " \ | |
80 | "tftpboot ${loadaddr} ${kernel}; bootm\0" \ | |
81 | "prg_uboot=tftpboot ${loadaddr} ${uboot}; " \ | |
82 | "protect off ${uboot_addr} 0xa003ffff; " \ | |
83 | "erase ${uboot_addr} 0xa003ffff; " \ | |
84 | "cp.b ${loadaddr} ${uboot_addr} ${filesize}; " \ | |
85 | "setenv filesize; saveenv\0" | |
b5dc9b30 | 86 | |
b1c0eaac BW |
87 | #define CONFIG_CS8900 |
88 | #define CONFIG_CS8900_BASE 0xb4020300 | |
89 | #define CONFIG_CS8900_BUS16 1 /* follow the Linux driver */ | |
d23ff682 GL |
90 | |
91 | /* | |
92 | * The MX31ADS board seems to have a hardware "peculiarity" confirmed under | |
93 | * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A | |
94 | * controller inverted. The controller is capable of detecting and correcting | |
95 | * this, but it needs 4 network packets for that. Which means, at startup, you | |
96 | * will not receive answers to the first 4 packest, unless there have been some | |
97 | * broadcasts on the network, or your board is on a hub. Reducing the ARP | |
98 | * timeout from default 5 seconds to 200ms we speed up the initial TFTP | |
99 | * transfer, should the user wish one, significantly. | |
100 | */ | |
101 | #define CONFIG_ARP_TIMEOUT 200UL | |
b5dc9b30 GL |
102 | |
103 | /* | |
104 | * Miscellaneous configurable options | |
105 | */ | |
6d0f6bcf | 106 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
6d0f6bcf | 107 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
b5dc9b30 | 108 | /* Print Buffer Size */ |
6d0f6bcf JCPV |
109 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
110 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
111 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
b5dc9b30 | 112 | |
6d0f6bcf JCPV |
113 | #define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ |
114 | #define CONFIG_SYS_MEMTEST_END 0x10000 | |
b5dc9b30 | 115 | |
6d0f6bcf | 116 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR |
b5dc9b30 | 117 | |
b5dc9b30 GL |
118 | #define CONFIG_CMDLINE_EDITING 1 |
119 | ||
b5dc9b30 GL |
120 | /*----------------------------------------------------------------------- |
121 | * Physical Memory Map | |
122 | */ | |
123 | #define CONFIG_NR_DRAM_BANKS 1 | |
124 | #define PHYS_SDRAM_1 CSD0_BASE | |
125 | #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) | |
4ac2e2d6 FE |
126 | #define CONFIG_BOARD_EARLY_INIT_F |
127 | ||
128 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 | |
129 | #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR | |
130 | #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE | |
131 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ | |
132 | GENERATED_GBL_DATA_SIZE) | |
133 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ | |
134 | CONFIG_SYS_GBL_DATA_OFFSET) | |
b5dc9b30 GL |
135 | |
136 | /*----------------------------------------------------------------------- | |
137 | * FLASH and environment organization | |
138 | */ | |
6d0f6bcf JCPV |
139 | #define CONFIG_SYS_FLASH_BASE CS0_BASE |
140 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
141 | #define CONFIG_SYS_MAX_FLASH_SECT 262 /* max number of sectors on one chip */ | |
142 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */ | |
143 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256KiB */ | |
b5dc9b30 | 144 | |
5a1aceb0 | 145 | #define CONFIG_ENV_IS_IN_FLASH 1 |
ba8dcca7 | 146 | #define CONFIG_ENV_SECT_SIZE (128 * 1024) |
0e8d1586 | 147 | #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE |
ba8dcca7 | 148 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
d23ff682 GL |
149 | |
150 | /* Address and size of Redundant Environment Sector */ | |
ba8dcca7 | 151 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) |
0e8d1586 | 152 | #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE |
d23ff682 | 153 | |
b5dc9b30 GL |
154 | /*----------------------------------------------------------------------- |
155 | * CFI FLASH driver setup | |
156 | */ | |
6d0f6bcf | 157 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */ |
00b1883a | 158 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ |
d23ff682 | 159 | #define CONFIG_FLASH_SPANSION_S29WS_N 1 /* A non-standard buffered write algorithm */ |
6d0f6bcf JCPV |
160 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ |
161 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */ | |
b5dc9b30 GL |
162 | |
163 | /* | |
164 | * JFFS2 partitions | |
165 | */ | |
68d7d651 | 166 | #undef CONFIG_CMD_MTDPARTS |
b5dc9b30 GL |
167 | #define CONFIG_JFFS2_DEV "nor0" |
168 | ||
169 | #endif /* __CONFIG_H */ |