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b5dc9b30 GL |
1 | /* |
2 | * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de> | |
3 | * | |
4 | * Configuration settings for the MX31ADS Freescale board. | |
5 | * | |
3765b3e7 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
b5dc9b30 GL |
7 | */ |
8 | ||
9 | #ifndef __CONFIG_H | |
10 | #define __CONFIG_H | |
11 | ||
86271115 | 12 | #include <asm/arch/imx-regs.h> |
b5dc9b30 GL |
13 | |
14 | /* High Level Configuration Options */ | |
3fd968e9 | 15 | #define CONFIG_MX31 1 /* This is a mx31 */ |
b5dc9b30 GL |
16 | |
17 | #define CONFIG_DISPLAY_CPUINFO | |
18 | #define CONFIG_DISPLAY_BOARDINFO | |
19 | ||
4ac2e2d6 FE |
20 | #define CONFIG_SYS_TEXT_BASE 0xA0000000 |
21 | ||
da3598ac FE |
22 | #define CONFIG_MACH_TYPE MACH_TYPE_MX31ADS |
23 | ||
b5dc9b30 GL |
24 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
25 | #define CONFIG_SETUP_MEMORY_TAGS 1 | |
26 | #define CONFIG_INITRD_TAG 1 | |
27 | ||
28 | /* | |
29 | * Size of malloc() pool | |
30 | */ | |
6d0f6bcf | 31 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) |
b5dc9b30 GL |
32 | |
33 | /* | |
34 | * Hardware drivers | |
35 | */ | |
36 | ||
40f6fffe SB |
37 | #define CONFIG_MXC_UART |
38 | #define CONFIG_MXC_UART_BASE UART1_BASE | |
b5dc9b30 | 39 | |
0a0b606f GL |
40 | #define CONFIG_HARD_SPI 1 |
41 | #define CONFIG_MXC_SPI 1 | |
d255bb0e | 42 | #define CONFIG_DEFAULT_SPI_BUS 1 |
9f481e95 | 43 | #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) |
5bd9a9b0 | 44 | #define CONFIG_MXC_GPIO |
0a0b606f | 45 | |
d7d6780f | 46 | /* PMIC Controller */ |
be3b51aa ŁM |
47 | #define CONFIG_POWER |
48 | #define CONFIG_POWER_SPI | |
49 | #define CONFIG_POWER_FSL | |
dfe5e14f SB |
50 | #define CONFIG_FSL_PMIC_BUS 1 |
51 | #define CONFIG_FSL_PMIC_CS 0 | |
52 | #define CONFIG_FSL_PMIC_CLK 1000000 | |
9f481e95 | 53 | #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) |
d7d6780f | 54 | #define CONFIG_FSL_PMIC_BITLEN 32 |
4e8b7544 | 55 | #define CONFIG_RTC_MC13XXX |
0a0b606f | 56 | |
b5dc9b30 GL |
57 | /* allow to overwrite serial and ethaddr */ |
58 | #define CONFIG_ENV_OVERWRITE | |
59 | #define CONFIG_CONS_INDEX 1 | |
60 | #define CONFIG_BAUDRATE 115200 | |
b5dc9b30 GL |
61 | |
62 | /*********************************************************** | |
63 | * Command definition | |
64 | ***********************************************************/ | |
0a0b606f | 65 | #define CONFIG_CMD_DATE |
b5dc9b30 | 66 | |
b5dc9b30 | 67 | |
7602ed50 | 68 | #define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */ |
0a0b606f GL |
69 | |
70 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
71 | "netdev=eth0\0" \ | |
72 | "uboot_addr=0xa0000000\0" \ | |
73 | "uboot=mx31ads/u-boot.bin\0" \ | |
74 | "kernel=mx31ads/uImage\0" \ | |
75 | "nfsroot=/opt/eldk/arm\0" \ | |
76 | "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \ | |
77 | "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \ | |
78 | "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ | |
79 | "bootcmd=run bootcmd_net\0" \ | |
80 | "bootcmd_net=run bootargs_base bootargs_nfs; " \ | |
81 | "tftpboot ${loadaddr} ${kernel}; bootm\0" \ | |
82 | "prg_uboot=tftpboot ${loadaddr} ${uboot}; " \ | |
83 | "protect off ${uboot_addr} 0xa003ffff; " \ | |
84 | "erase ${uboot_addr} 0xa003ffff; " \ | |
85 | "cp.b ${loadaddr} ${uboot_addr} ${filesize}; " \ | |
86 | "setenv filesize; saveenv\0" | |
b5dc9b30 | 87 | |
b1c0eaac BW |
88 | #define CONFIG_CS8900 |
89 | #define CONFIG_CS8900_BASE 0xb4020300 | |
90 | #define CONFIG_CS8900_BUS16 1 /* follow the Linux driver */ | |
d23ff682 GL |
91 | |
92 | /* | |
93 | * The MX31ADS board seems to have a hardware "peculiarity" confirmed under | |
94 | * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A | |
95 | * controller inverted. The controller is capable of detecting and correcting | |
96 | * this, but it needs 4 network packets for that. Which means, at startup, you | |
97 | * will not receive answers to the first 4 packest, unless there have been some | |
98 | * broadcasts on the network, or your board is on a hub. Reducing the ARP | |
99 | * timeout from default 5 seconds to 200ms we speed up the initial TFTP | |
100 | * transfer, should the user wish one, significantly. | |
101 | */ | |
102 | #define CONFIG_ARP_TIMEOUT 200UL | |
b5dc9b30 GL |
103 | |
104 | /* | |
105 | * Miscellaneous configurable options | |
106 | */ | |
6d0f6bcf | 107 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
6d0f6bcf | 108 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
b5dc9b30 | 109 | /* Print Buffer Size */ |
6d0f6bcf JCPV |
110 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
111 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
112 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
b5dc9b30 | 113 | |
6d0f6bcf JCPV |
114 | #define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ |
115 | #define CONFIG_SYS_MEMTEST_END 0x10000 | |
b5dc9b30 | 116 | |
6d0f6bcf | 117 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR |
b5dc9b30 | 118 | |
b5dc9b30 GL |
119 | #define CONFIG_CMDLINE_EDITING 1 |
120 | ||
b5dc9b30 GL |
121 | /*----------------------------------------------------------------------- |
122 | * Physical Memory Map | |
123 | */ | |
124 | #define CONFIG_NR_DRAM_BANKS 1 | |
125 | #define PHYS_SDRAM_1 CSD0_BASE | |
126 | #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) | |
4ac2e2d6 FE |
127 | #define CONFIG_BOARD_EARLY_INIT_F |
128 | ||
129 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 | |
130 | #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR | |
131 | #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE | |
132 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ | |
133 | GENERATED_GBL_DATA_SIZE) | |
134 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ | |
135 | CONFIG_SYS_GBL_DATA_OFFSET) | |
b5dc9b30 GL |
136 | |
137 | /*----------------------------------------------------------------------- | |
138 | * FLASH and environment organization | |
139 | */ | |
6d0f6bcf JCPV |
140 | #define CONFIG_SYS_FLASH_BASE CS0_BASE |
141 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
142 | #define CONFIG_SYS_MAX_FLASH_SECT 262 /* max number of sectors on one chip */ | |
143 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */ | |
144 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256KiB */ | |
b5dc9b30 | 145 | |
5a1aceb0 | 146 | #define CONFIG_ENV_IS_IN_FLASH 1 |
ba8dcca7 | 147 | #define CONFIG_ENV_SECT_SIZE (128 * 1024) |
0e8d1586 | 148 | #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE |
ba8dcca7 | 149 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
d23ff682 GL |
150 | |
151 | /* Address and size of Redundant Environment Sector */ | |
ba8dcca7 | 152 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) |
0e8d1586 | 153 | #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE |
d23ff682 | 154 | |
b5dc9b30 GL |
155 | /*----------------------------------------------------------------------- |
156 | * CFI FLASH driver setup | |
157 | */ | |
6d0f6bcf | 158 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */ |
00b1883a | 159 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ |
d23ff682 | 160 | #define CONFIG_FLASH_SPANSION_S29WS_N 1 /* A non-standard buffered write algorithm */ |
6d0f6bcf JCPV |
161 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ |
162 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */ | |
b5dc9b30 GL |
163 | |
164 | /* | |
165 | * JFFS2 partitions | |
166 | */ | |
68d7d651 | 167 | #undef CONFIG_CMD_MTDPARTS |
b5dc9b30 GL |
168 | #define CONFIG_JFFS2_DEV "nor0" |
169 | ||
170 | #endif /* __CONFIG_H */ |